TPIC1021A-Q1 www.ti.com.......................................................................................................................................................... SLIS117A – AUGUST 2007 – REVISED JUNE 2009 LIN PHYSICAL INTERFACE FEATURES 1 • • • • • • • • • LIN Physical Layer Specification Revision 2.0 Compliant and Conforms to SAEJ2602 Recommended Practice for LIN LIN Bus Speed up to 20-kbps LIN Specified Maximum Sleep Mode: Ultralow Current Consumption, Allows Wake-Up Events From LIN Bus, Wake-Up Input (External Switch), or Host MCU High-Speed Receive Capable ESD Protection to ±12 kV (Human-Body Model) on LIN Pin LIN Pin Handles Voltage From –40 V to 40 V Survives Transient Damage in Automotive Environment (ISO 7637) Extended Operation With Supply From 7 V to 27 V DC (LIN Specification 7 V to 18 V) Interfaces to MCU With 5-V or 3.3-V I/O Pins • • • • • • • • • • • Dominant State Timeout Protection Wake-Up Request on RXD Pin Control of External Voltage Regulator (INH Pin) Integrated Pullup Resistor and Series Diode for LIN Slave Applications Low Electromagnetic Emission (EME), High Electromagnetic Immunity (EMI) Bus Terminal Short Circuit Protected for Short to Battery or Short to Ground Thermally Protected Ground Disconnection Fail Safe at System Level Ground Shift Operation at System Level Unpowered Node Does Not Disturb the Network Supports ISO9141 (K-Line)-Like Functions FUNCTIONAL BLOCK DIAGRAM TPIC1021A INH VSUP RXD Receiver VSUP/2 EN Filter VSUP NWake Wake Up, State, and INH Control Filter Fault Detection and Protection TXD Dominant State Timeout Driver With Slope Control LIN GND 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007–2009, Texas Instruments Incorporated TPIC1021A-Q1 SLIS117A – AUGUST 2007 – REVISED JUNE 2009.......................................................................................................................................................... www.ti.com DESCRIPTION The TPIC1021A is the Local Interconnect Network (LIN) physical interface, which integrates the serial transceiver with wake-up and protection features. The LIN bus is a single-wire bidirectional bus typically used for low-speed in-vehicle networks using data rates between 2.4 kbps and 20 kbps. The LIN protocol output data stream on TXD is converted by the TPIC1021A into the LIN bus signal through a current-limited wave-shaping driver as outlined by the LIN Physical Layer Specification Revision 2.0. The receiver converts the data stream from the LIN bus and outputs the data stream via RXD. The LIN bus has two states: dominant state (voltage near ground) and the recessive state (voltage near battery). In the recessive state, the LIN bus is pulled high by the TPIC1021A’s internal pullup resistor (30 kΩ) and series diode, so no external pullup components are required for slave applications. Master applications require an external pullup resistor (1 kΩ) plus a series diode per the LIN specification. In sleep mode, the TPIC1021A requires low quiescent current even though the wake-up circuits remain active, allowing for remote wake up via the LIN bus or local wake up via the NWake or EN pins. The TPIC1021A has been designed for operation in the harsh automotive environment. The device can handle LIN bus voltage swings from 40 V down to ground and survive –40 V. The device also prevents back-feed current through LIN to the supply input, in case of a ground shift or supply voltage disconnection. It also features undervoltage, overtemperature, and loss-of-ground protection. In the event of a fault condition, the output is immediately switched off and remains off until the fault condition is removed. TERMINAL FUNCTIONS D PACKAGE (TOP VIEW) RXD EN NWake TXD 1 8 2 7 3 6 4 5 INH VSUP LIN GND TERMINAL ASSIGNMENTS PIN NAME NO. TYPE DESCRIPTION RXD 1 O RXD output (open drain) interface reporting state of LIN bus voltage EN 2 I Enable input NWake 3 I High voltage input for device wake up TXD 4 I TXD input interface to control state of LIN output GND 5 GND LIN 6 I/O VSUP 7 Supply INH 8 O Ground LIN bus single-wire transmitter and receiver Device supply voltage (connected to battery in series with external reverse blocking diode) Inhibit controls external voltage regulator with inhibit input ORDERING INFORMATION (1) (1) (2) 2 PART NUMBER PACKAGE (2) ORDERABLE PART NUMBER TOP-SIDE MARKING TPIC1021A-Q1 SOIC-8 – D TPIC1021AQDRQ1 (reel) T1021A For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): TPIC1021A-Q1 TPIC1021A-Q1 www.ti.com.......................................................................................................................................................... SLIS117A – AUGUST 2007 – REVISED JUNE 2009 Local Interconnect Network (LIN) Bus This I/O pin is the single-wire LIN bus transmitter and receiver. Transmitter Characteristics The driver is a low-side transistor with internal current limitation and thermal shutdown. There is an internal 30-kΩ pullup resistor with a serial diode structure to VSUP, so no external pullup components are required for LIN slave mode applications. An external pullup resistor of 1 kΩ, plus a series diode to VSUP must be added when the device is used for master node applications. Voltage on LIN can go from –40-V to 40-V dc without any currents other than through the pullup resistance. There are no reverse currents from the LIN bus to supply (VSUP), even in the event of a ground shift or loss of supply (VSUP). The LIN thresholds and ac parameters are LIN Protocol Specification Revision 2.0 compliant. During a thermal shut down condition the driver is disabled. Receiver Characteristics The receiver’s characteristic thresholds are ratio-metric with the device supply pin. Typical thresholds are 50%, with a hysteresis between 5% and 17.5% of supply. The receiver is capable of receiving higher data rates (>100 kbps) than supported by LIN or SAEJ2602 specifications. This allows the TPIC1021A to be used for high-speed downloads at end-of-line production or other applications. The actual data rates achievable depend on system time constants (bus capacitance and pullup resistance) and driver characteristics used in the system. Transmit Input (TXD) TXD is the interface to the MCU’s LIN protocol controller or SCI/UART used to control the state of the LIN output. When TXD is low, the LIN output is dominant (near ground). When TXD is high, the LIN output is recessive (near battery). The TXD input structure is compatible with microcontrollers with 3.3-V and 5-V I/O. TXD has an internal pulldown resistor. TXD Dominant State Timeout If TXD is inadvertently driven permanently low by a hardware or software application failure, the LIN bus is protected by TPIC1021A’s dominant state timeout timer. This timer is triggered by a falling edge on TXD. If the low signal remains on TXD for longer than tDST, the transmitter is disabled, thus allowing the LIN bus to return to the recessive state and communication to resume on the bus. The timer is reset by a rising edge on TXD. Receive Output (RXD) RXD is the interface to the MCU’s LIN protocol controller or SCI/UART, which reports the state of the LIN bus voltage. LIN recessive (near battery) is represented by a high level on RXD and LIN dominant (near ground) is represented by a low level on RXD. The RXD output structure is an open-drain output stage. This allows the TPIC1021A to be used with 3.3-V and 5-V I/O microcontrollers. If the microcontroller’s RXD pin does not have an integrated pullup, an external pullup resistor to the microcontroller I/O supply voltage is required. RXD Wake-up Request When the TPIC1021A has been in low-power mode and encounters a wake-up event from the LIN bus or NWake pin, RXD goes low, while the device enters and remains in standby mode (until EN is reasserted high and the device enters normal mode). Supply Voltage (VSUP) VSUP is the TPIC1021A device power supply pin. VSUP is connected to the battery through an external reverse battery blocking diode. The characterized operating voltage range for the TPIC1021A is from 7 V to 27 V. VSUP is protected for harsh automotive conditions up to 40 V. The device contains a reset circuit to avoid false bus messages during undervoltage conditions when VSUP is less than VSUP_UNDER. Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): TPIC1021A-Q1 3 TPIC1021A-Q1 SLIS117A – AUGUST 2007 – REVISED JUNE 2009.......................................................................................................................................................... www.ti.com Ground (GND) GND is the TPIC1021A device ground connection. The TPIC1021A can operate with a ground shift as long as the ground shift does not reduce VSUP below the minimum operating voltage. If there is a loss of ground at the ECU level, the TPIC1021A does not have a significant current consumption on LIN bus. Enable Input (EN) EN controls the operation mode of the TPIC1021A (normal or sleep mode). When EN is high, the TPIC1021A is in normal mode allowing a transmission path from TXD to LIN and from LIN to RXD. When EN is low the device is put into sleep mode and there are no transmission paths available. The device can enter normal mode only after being woken up. EN has an internal pulldown resistor to ensure the device remains in low-power mode even if EN floats. NWake Input (NWake) NWake is a high-voltage input used to wake up the TPIC1021A from low-power mode. NWake is usually connected to an external switch in the application. A low on NWake that is asserted longer than the filter time (tNWAKE) results in a local wake-up. NWake provides an internal pullup source to VSUP. Inhibit Output (INH) INH is used to control an external voltage regulator that has an inhibit input. When the TPIC1021A is in normal operating mode, the inhibit high-side switch is enabled and the external voltage regulator is activated. When TPIC1021A is in low-power mode, the inhibit switch is turned off, which disables the voltage regulator. A wake-up event on for the TPIC1021A returns INH to VSUP level. INH can also drive an external transistor connected to an MCU interrupt input. 4 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): TPIC1021A-Q1 TPIC1021A-Q1 www.ti.com.......................................................................................................................................................... SLIS117A – AUGUST 2007 – REVISED JUNE 2009 OPERATING STATES Unpowered System Vsup £ Vsup_under Vsup £ Vsup_under Vsup > Vsup_under EN = high Vsup £ Vsup_under Vsup £ Vsup_under Vsup > Vsup_under EN = low Standby Mode Driver : Off RXD: Low INH: High (On) Termination: 30 kW Sleep Mode Normal Mode Driver : On RXD: LIN bus data INH: High (On) Termination: 30 kW LIN Bus Wake-Up or Nwake Pin Wake-Up EN = high EN = low Driver : Off RXD: Floating INH: High impedance (Off) Termination: Weak pullup EN = high Figure 1. Operating States Diagram Table 1. Operating Modes EN RXD LIN BUS TERMINATION INH TRANSMITTER Sleep Low Floating Weak current pullup High impedance Off Standby Low Low 30 kΩ (typ) High Off Wake-up event detected, waiting on MCU to set EN Normal High LIN bus data 30 kΩ (typ) High On LIN transmission up to 20 kbps MODE COMMENTS Normal Mode This is the normal operational mode, in which the receiver and driver are active, and LIN transmission up to the LIN specified maximum of 20 kbps is supported. The receiver detects the data stream on the LIN bus and outputs it on RXD for the LIN controller, where recessive on the LIN bus is a digital high, and dominate on the LIN bus is digital low. The driver transmits input data on TXD to the LIN bus. Normal mode is entered as EN transitions high while the TPIC1021A is in sleep or standby mode. Sleep Mode Sleep mode is the power saving mode for the TPIC1021A and the default state after power up (assuming EN is low during power up). Even with the extremely low current consumption in this mode, the TPIC1021A can still wake up from LIN bus via a wake-up signal, a low on NWake, or if EN is set high. The LIN bus and NWake are filtered to prevent false wake-up events. The wake-up events must be active for their respective time periods (tLINBUS, tNWake). The sleep mode is entered by setting EN low. Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): TPIC1021A-Q1 5 TPIC1021A-Q1 SLIS117A – AUGUST 2007 – REVISED JUNE 2009.......................................................................................................................................................... www.ti.com While the device is in sleep mode, the following conditions exist: • The LIN bus driver is disabled and the internal LIN bus termination is switched off (to minimize power loss if LIN is short circuited to ground). However, the weak current pullup is active to prevent false wake-up events in case an external connection to the LIN bus is lost. • The normal receiver is disabled. • INH is high impedance. • EN input, NWake input, and the LIN wake-up receiver are active. Wake-Up Events There are three ways to wake up the TPIC1021A from sleep mode: • Remote wake-up via recessive (high) to dominant (low) state transition on LIN bus. The dominant state must be held for tLINBUS filter time and then the bus must return to the recessive state (to eliminate false wake-ups from disturbances on the LIN bus or if the bus is shorted to ground). • Local wake-up via a low on NWake, which is asserted low longer than the filter time tNWake (to eliminate false wake-ups from disturbances on NWake) • Local wake-up via EN being set high Standby Mode This mode is entered whenever a wake-up event occurs via LIN bus or NWake while the TPIC1021A is in sleep mode. The LIN bus slave termination circuit and INH are turned on when standby mode is entered. The application system powers up once INH is turned on, assuming the system is using a voltage regulator connected via INH. Standby mode is signaled via a low level on RXD. When EN is set high while the TPIC1021A is in standby mode the device returns to normal mode and the normal transmission paths from TXD to LIN bus and LIN bus to RXD are enabled. EN INH Vsup High Impedance TXD t > tgo_to_operate Vsup LIN RXD MODE Floating Sleep Normal Figure 2. Wake-Up Via EN 6 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): TPIC1021A-Q1 TPIC1021A-Q1 www.ti.com.......................................................................................................................................................... SLIS117A – AUGUST 2007 – REVISED JUNE 2009 LIN 0.6 × VSUP 0.4 × VSUP 0.6 × VSUP Vsup 0.4 × VSUP t < tLINBUS tLINBUS Vsup INH High Impedance TXD t > tgo_to_operate EN RXD MODE Floating Sleep Standby Normal Figure 3. Wake-Up Via LIN Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): TPIC1021A-Q1 7 TPIC1021A-Q1 SLIS117A – AUGUST 2007 – REVISED JUNE 2009.......................................................................................................................................................... www.ti.com NWake VIL NWake VIH NWake VIL NWake Vsup t < tNWake INH tNWake Vsup High Impedance TXD t > tgo_to_operate EN RXD Floating Vsup LIN MODE Sleep Standby Normal Figure 4. Wake-Up Via NWake 8 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): TPIC1021A-Q1 TPIC1021A-Q1 www.ti.com.......................................................................................................................................................... SLIS117A – AUGUST 2007 – REVISED JUNE 2009 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) PARAMETER RATING VSUP (2) Supply line supply voltage (3) VNWake NWake dc and transient input voltage (through 33-kΩ serial resistor) INWake NWake current if due to ground shifts VNWake ≤ VGND - 0.3V, thus the current into NWake must -3.6 mA be limited via a serial resistance. VINH INH voltage Logic pin input voltage VLIN 0 to 40 –0.3 to 40 RXD, TXD, EN –0.3 to 5.5 Human-Body Model All pins (5) –11 to 11 (4) kV –4 to 4 –1500 to 1500 TA Operational free-air temperature range –40 to 125 TJ Junction temperature range –40 to 150 Tstg Storage temperature range –40 to 165 RθJA Thermal resistance, junction to ambient 145 Thermal shutdown 200 Thermal shutdown hysteresis 25 (4) (5) V –12 to 12 NWake (4) All other pins Charge-Device Model (2) (3) mA –40 to 40 LIN (4) (1) V –0.3 to VSUP + 0.3 LIN dc-input voltage Electrostatic discharge -3.6 UNIT V °C °C/W °C Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to GND. The device is specified for operation in the range of VSUP from 7 V to 27 V. Operating the device above 27 V may significantly raise the junction temperature of the device and system level thermal design needs to be considered. The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin. Tested in accordance to JEDEC Standard 22, Test Method C101 (JESD22-C101). Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): TPIC1021A-Q1 9 TPIC1021A-Q1 SLIS117A – AUGUST 2007 – REVISED JUNE 2009.......................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS VSUP = 7 V to 27 V, TA = –40°C to 125°C (unless otherwise noted) MIN TYP (1) MAX Device is operational beyond the LIN 2.0 defined nominal supply line voltage range of 7 V < VSUP < 18 V 7 14 27 Normal and standby modes 7 14 18 Sleep mode 7 PARAMETER TEST CONDITIONS UNIT SUPPLY Operational supply voltage (2) Nominal supply line voltage 12 18 4.5 6.2 Normal mode, EN = High, Bus dominant (total bus load where RLIN ≥ 500 Ω and CLIN ≤ 10 nF (see Figure 7) (3), INH = VSUP, NWake = VSUP 1.2 7.5 mA Standby mode, EN = Low, Bus dominant (total bus load, where RLIN ≥ 500 Ω and CLIN ≤ 10 nF (see Figure 7) (3), INH = VSUP, NWake = VSUP 1 2.1 mA Normal mode, EN = High, Bus recessive, LIN = VSUP, INH = VSUP, NWake = VSUP 450 775 Standby mode, EN = Low, Bus recessive, LIN = VSUP, INH = VSUP, NWake = VSUP 450 775 15 30 µA 50 µA 5.5 V VSUP undervoltage threshold ICC Supply current V µA Sleep mode, EN = 0, 7 V < VSUP ≤ 12 V, LIN = VSUP, NWake = VSUP Sleep mode, EN = 0, 12 V < VSUP < 27 V, LIN = VSUP, NWake = VSUP RXD OUTPUT PIN VO Output voltage –0.3 IOL Low-level output current, open drain LIN = 0 V, RXD = 0.4 V 3.5 IIKG Leakage current, high-level LIN = VSUP, RXD = 5 V –5 mA 0 5 µA TXD INPUT PIN VIL Low-level input voltage –0.3 0.8 VIH High-level input voltage 2 5.5 VIT Input threshold hysteresis voltage 30 500 mV Pulldown resistor IIL (1) (2) (3) 10 Low-level input current TXD = Low V 125 350 800 kΩ –5 0 5 µA Typical values are given for VSUP = 14 V at 25°C, except for low power mode where typical values are given for VSUP = 12 V at 25°C. All voltages are defined with respect to ground; positive currents flow into the TPIC1021A device. In the dominant state, the supply current increases as the supply voltage increases due to the integrated LIN slave termination resistance. At higher voltages the majority of supply current is through the termination resistance. The minimum resistance of the LIN slave termination is 20 kΩ, so the maximum supply current attributed to the termination is: ISUP (dom) max termination ≈ (VSUP – (VLIN_Dominant + 0.7 V) / 20 kΩ Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): TPIC1021A-Q1 TPIC1021A-Q1 www.ti.com.......................................................................................................................................................... SLIS117A – AUGUST 2007 – REVISED JUNE 2009 ELECTRICAL CHARACTERISTICS (continued) VSUP = 7 V to 27 V, TA = –40°C to 125°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT LIN PIN (Referenced to VSUP) VOH High-level output voltage LIN recessive, TXD = High, IO = 0 mA, VSUP = 14 V VOL Low-level output voltage LIN dominant, TXD = Low, IO = 40 mA, VSUP = 14 V 0 Rslave Pullup resistor to VSUP Normal and standby modes 20 VSUP – 1 V 0.2 × VSUP 30 60 V kΩ –20 µA 160 250 mA 0 5 Pullup current source to VSUP Sleep mode, VSUP = 14 V, LIN = GND –2 IL Limiting current TXD = 0 V 45 ILKG Leakage current LIN = VSUP –5 ILKG Leakage current, loss of supply 7 V < LIN ≤ 12 V, VSUP = GND 5 12 V < LIN < 18 V, VSUP = GND 10 VIL Low-level input voltage LIN dominant VIH High-level input voltage LIN recessive VIT Input threshold voltage Vhys Hysteresis voltage VIL Low-level input voltage for wake-up µA 0.4 × VSUP 0.6 × VSUP 0.4 × VSUP 0.5 × VSUP 0.05 × VSUP 0.6 × VSUP V 0.175 × VSUP 0.4 × VSUP EN PIN VIL Low-level input voltage –0.3 0.8 VIH High-level input voltage 2 5.5 Vhys Hysteresis voltage 30 500 mV Pulldown resistor 125 350 800 kΩ –5 0 5 µA VSUP + 0.3 V 35 85 Ω 0 5 µA IIL Low-level input current EN = Low V INH PIN Vo DC output voltage –0.3 Ron On state resistance Between VSUP and INH, INH = 2-mA drive, Normal or standby mode IIKG Leakage current Low-power mode, 0 < INH < VSUP –5 NWake PIN VIL Low-level input voltage –0.3 VSUP – 3.3 VIH High-level input voltage VSUP – 1 VSUP + 0.3 IIKG Pullup current NWake = 0 V Leakage current VSUP = NWake –45 –10 –2 –5 0 5 V µA THERMAL SHUTDOWN Shutdown junction thermal temperature 190 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): TPIC1021A-Q1 °C 11 TPIC1021A-Q1 SLIS117A – AUGUST 2007 – REVISED JUNE 2009.......................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS (continued) VSUP = 7 V to 27 V, TA = –40°C to 125°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT AC CHARACTERISTICS Duty cycle 1 (4) THREC(max) = 0.744 × VSUP, THDOM(max) = 0.581 × VSUP, VSUP = 7 V to 18 V, tBIT = 50 µs (20 kbps), D1 = tBus_rec(min)/ (2 × tBIT). See Figure 5 Duty cycle 2 (4) THREC(min) = 0.422 × VSUP, THDOM(min) = 0.284 × VSUP, VSUP = 7.6 V to 18 V, tBIT = 50 µs (20 kbps), D2 = tBus_rec(max)/ (2 × tBIT). See Figure 5 Duty cycle 3 (4) THREC(max) = 0.778 × VSUP, THDOM(max) = 0.616 × VSUP, VSUP = 7 V to 18 V, tBIT = 96 µs (10.4 kbps), D3 = tBus_rec(min)/ (2 × tBIT). See Figure 5 D4 Duty cycle 4 (4) THREC(min) = 0.389 × VSUP, THDOM(min) = 0.251 × VSUP, VSUP = 7.6 V to 18 V, tBIT = 96 µs (10.4 kbps), D4 = tBus_rec(max)/ (2 × tBIT). See Figure 5 trx_pdr Receiver rising propagation delay time RRXD = 2.4 kΩ, CRXD = 20 pF See Figure 6 See Figure 7 6 trx_pdf Receiver falling propagation delay time RRXD = 2.4 kΩ, CRXD = 20 pF See Figure 6 See Figure 7 6 trx_sym Symmetry of receiver propagation delay time rising edge with respect to falling edge (trx_sym = trx_pdf - trx_pdr) RRXD = 2.4 kΩ, CRXD = 20 pF See Figure 6 See Figure 7 –2 tNWake NWake filter time for local wake-up See Figure 4 25 50 150 tLINBUS LIN wake-up filter time (dominant time for wake-up via LIN bus) See Figure 3 25 50 150 tDST Dominant state timeout (5) D1 D2 D3 tgo_to_operate (4) (5) 12 0.396 0.581 0.417 0.59 2 5.5 See Figure 2 to Figure 3 0.5 µs 20 ms 1 µs Duty cycles: LIN driver bus load conditions (CLINBUS, RLINBUS): Load1 = 1 nF, 1 kΩ; Load2 = 10 nF, 500 Ω. Duty cycles 3 and 4 are defined for 10.4-kbps operation. The TPIC1021A also meets these lower data rate requirements, while it is capable of the higher speed 20-kbps operation as specified by Duty cycles 1 and 2. SAEJ2602 derives propagation delay equations from the LIN 2.0 duty cycle definitions, for details see the SAEJ2602 specification. Dominant state timeout limits the minimum data rate to 2.4 kbps. Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): TPIC1021A-Q1 TPIC1021A-Q1 www.ti.com.......................................................................................................................................................... SLIS117A – AUGUST 2007 – REVISED JUNE 2009 TIMING DIAGRAMS tBit tBit RECESSIVE D = 0.5 TXD (Input) DOMINANT THRec(max) LIN Bus Signal Thresholds : Worst case 1 THDom(max) Vsup THRec(min) Thresholds : Worst case 2 THDom(min) tBus_dom(max) tBus_rec(max) D = tBus_rec(min)/(2 x tBit) RXD D1 (20 kbps) and D3 (10 kbps) case tBus_dom(min) tBus_rec(min) D = tBus_rec(max)/(2 x tBit) RXD D2 (20 kbps) and D4 (10 kbps) case Figure 5. Definition of Bus Timing Parameters Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): TPIC1021A-Q1 13 TPIC1021A-Q1 SLIS117A – AUGUST 2007 – REVISED JUNE 2009.......................................................................................................................................................... www.ti.com TIMING DIAGRAMS (continued) LIN Bus 0.6 VSUP VSUP 0.4 VSUP trx_pdf trx_pdr RXD 50% 50% Figure 6. Propagation Delay VCC TPIC1021A RRXD RXD INH CRXD VSUP 100 nF EN RLIN NWake LIN CLIN TXD GND Figure 7. Test Circuit for AC Characteristics 14 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): TPIC1021A-Q1 TPIC1021A-Q1 www.ti.com.......................................................................................................................................................... SLIS117A – AUGUST 2007 – REVISED JUNE 2009 APPLICATION INFORMATION VBAT VSUP TPSxxxx MASTER NODE VSUP VDD NWake VSUP INH VDD EN I/O 2 8 MCU w/o (2) pullup VDD I/O MCU TMS470 LIN Controller or SCI/UART(1) RXD TXD GND 3 Master Node Pullup(3) 7 1 kW TPIC1021A LIN 1 6 4 5 220 pF LIN Bus VDD VSUP SLAVE NODE TPSxxxx VSUP VDD NWake INH VSUP VDD EN I/O 2 MCU w/o pullup(2) VDD I/O MCU TMS470 LIN Controller or SCI/UART(1) GND RXD TXD 8 3 7 TPIC1021A LIN 1 4 6 5 (1) RXD on MCU or LIN slave has internal pullup, no external pullup resistor is needed. (2) RXD on MCU or LIN slave without internal pullup, requires external pullup resistor. (3) Master node applications require an external 1-kΩ pullup resistor and serial diode. 220 pF Figure 8. Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): TPIC1021A-Q1 15 TPIC1021A-Q1 SLIS117A – AUGUST 2007 – REVISED JUNE 2009.......................................................................................................................................................... www.ti.com Device Comparison: TPIC1021 vs TPIC1021A The TPIC1021A is pin-to-pin compatible to the TPIC1021 device. The TPIC1021A is an enhanced LIN transceiver, including enhanced immunity to RF disturbances. Table 2 is a summary of the differences between the two devices. Table 2. TPIC1021A vs TPIC1021 Differences SPECIFICATION TPIC1021A TPIC1021 LIN termination Weak current pullup in sleep mode High Ω in low-power mode LIN receiver Enhanced high-speed receive capable High-speed receive capable LIN leakage current (unpowered device): 7 V < LIN < 12 V, VSUP = GND <5 µA at 12 V (max) <10 µA at 12 V (typ) LIN bus wake-up Remote wake-up via recessive-to-dominant transition on LIN bus where dominant bus state is held for at least tLINBUS time followed by a transition back to the recessive state Remote wake-up via recessive-to-dominant transition on LIN bus where dominant bus state is held for at least tLINBUS time Low-power current <30 µA at 12 V (max) <50 µA at 14 V (max) INH pin Enhanced driving of bus master termination via lower Ron Driving of bus master termination 16 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): TPIC1021A-Q1 PACKAGE OPTION ADDENDUM www.ti.com 30-Aug-2010 PACKAGING INFORMATION Orderable Device TPIC1021AQDRQ1 Status (1) ACTIVE Package Type Package Drawing SOIC D Pins Package Qty 8 2500 Eco Plan (2) Green (RoHS & no Sb/Br) Lead/ Ball Finish MSL Peak Temp CU NIPDAU Level-1-260C-UNLIM (3) Samples (Requires Login) Request Free Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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