TI HVDA551QDRQ1

HVDA551-Q1
HVDA553-Q1
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SLLSEC4 – JUNE 2013
5-V CAN TRANSCEIVER
WITH I/O LEVEL ADAPTING AND LOW-POWER-MODE SUPPLY OPTIMIZATION
Check for Samples: HVDA551-Q1, HVDA553-Q1
FEATURES
– RXD Wake Up Request Lock Out on CAN
Bus Stuck Dominant Fault (HVDA551)
– Digital Inputs Compatible With 5-V
Microprocessors (HVDA553)
– Thermal Shutdown Protection
– Power-Up and -Down Glitch-Free Bus I/O
– High Bus Input Impedance When
Unpowered (No Bus Load)
1
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
Meets or Exceeds the Requirements of
ISO 11898-2 and ISO 11898-5
GIFT/ICT Compliant
ESD Protection up to ±12 kV (Human-Body
Model) on Bus Pins
I/O Voltage Level Adapting
– HVDA551: Adaptable I/O Voltage Range
(VIO) From 3 V to 5.33 V
SPLIT Voltage Source
– HVDA553: Common-Mode Bus Stabilization
Operating Modes:
– Normal Mode
– Low-Power Standby Mode with RXD WakeUp Request
High Electromagnetic Compliance (EMC)
Supports CAN Flexible Data-Rate (FD)
Protection
– Undervoltage Protection on VIO and VCC
– Bus-Fault Protection of –27 V to 40 V
– TXD Dominant State Time-Out
APPLICATIONS
•
•
•
•
•
SAE J2284 High-Speed CAN for Automotive
Applications
SAE J1939 Standard Data Bus Interface
GMW3122 Dual-Wire CAN Physical Layer
ISO 11783 Standard Data Bus Interface
NMEA 2000 Standard Data Bus Interface
DESCRIPTION
The device is designed and qualified for use in
automotive applications and meets or exceeds the
specifications of the ISO 11898 High Speed CAN
(Controller Area Network) Physical Layer standard
(transceiver).
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
HVDA551-Q1
HVDA553-Q1
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FUNCTIONAL BLOCK DIAGRAMS
VIO
VCC
5
3
VCC
OVER
TEMPERATURE
VIO
7
TXD
1
DOMINANT
TIME-OUT
6
VIO
STB
8
CANH
DRIVER
CANL
MODE SELECT
RXD
4
LOGIC
OUTPUT
MUX
UNDER
VOLTAGE
WAKE UP LOGIC /
MONITOR
2
GND
Figure 1. HVDA551
VCC
SPLIT
5
VCC
VCC / 2
3
VCC
OVER
TEMPERATURE
7
TXD
1
DOMINANT
TIME-OUT
6
VCC
STB
8
CANH
DRIVER
CANL
MODE SELECT
RXD
4
LOGIC
OUTPUT
MUX
UNDER
VOLTAGE
WAKE UP LOGIC /
MONITOR
2
GND
Figure 2. HVDA553
2
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Table 1. TERMINAL FUNCTIONS
TERMINAL
NAME
D Package (SOIC)
NO.
TYPE
DESCRIPTION
CANH
7
I/O
High level CAN bus line
CANL
6
I/O
Low level CAN bus line
GND
2
GND
RXD
4
O
CAN receive data output (low in dominant bus state, high in recessive bus state)
STB
8
I
Standby mode select pin (active high)
TXD
1
I
CAN transmit data input (low for dominant bus state, high for recessive bus state)
VCC
3
Supply
VIO /
SPLIT
5
Supply / O
Ground connection
Transceiver 5V supply voltage
VIO (HVDA551): Transceiver logic level (IO) supply voltage
SPLIT (HVDA553): Common mode stabilization output
Table 2. ORDERING INFORMATION (1)
PACKAGE (2)
TA
–40°C to 125°C
(1)
(2)
SOIC – D
Reel of 2500
ORDERABLE PART NUMBER
TOP-SIDE MARKING
HVDA551QDRQ1
H551Q
HVDA553QDRQ1
H553Q
For the most-current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
FUNCTIONAL DESCRIPTION
General Description
The device meets or exceeds the specifications of the ISO 11898 High Speed CAN (Controller Area Network)
Physical Layer standard (transceiver). This device provides CAN transceiver functions: differential transmit
capability to the bus and differential receive capability at data rates up to 1 megabit per second (Mbps). The
device includes many protection features providing device and CAN network robustness.
Operating Modes
These devices have two main operating modes: normal mode and standby mode. Operating mode selection is
made via the STB input pin.
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Table 3. Operating Modes
DEVICE
All Devices
(1)
(2)
STB
MODE
DRIVER
RECEIVER
RXD Pin
LOW
Normal Mode
Enabled (On)
Enabled (On)
Mirrors bus state (1)
HIGH
Standby mode
(RXD wake-up
request)
Disabled (Off)
Low-power wake-up
receiver and bus
monitor enabled
Mirrors bus state via wake-up filter (2)
Mirrors bus state: LOW if CAN bus is dominant, HIGH if CAN bus is recessive.
See Figure 5 and Figure 6 for operation of the low-power wake-up receiver and bus monitor for RXD wake-up request behavior and
Table 5 for the wake -up receiver threshold levels.
Bus States by Mode
The CAN bus has three valid states during powered operation, depending on the mode of the device. In normal
mode the bus may be dominant (logic LOW), where the bus lines are driven differentially apart, or recessive
(logic HIGH), where the bus lines are biased to VCC / 2 via the high-ohmic internal input resistors RIN of the
receiver. The third state is low-power standby mode where the bus lines are biased to GND via the high-ohmic
internal input resistors RIN of the receiver.
Typical Bus Voltage
CANH
Low Power
Standby Mode
Normal & Silent Mode
VCC/2
A
RXD
CANH
B
CANL
Vdiff
Vdiff
CANL
A: Normal Mode
B: Low Power Standby Mode
Recessive
Dominant
Recessive
Time, t
Figure 3. Bus States (Physical Bit Representation)
Figure 4. Simplified Common-Mode Bias and
Receiver Implementation
Normal Mode
This is the normal operating mode of the device. Normal mode is selected by setting STB low. The CAN driver
and receiver are fully operational and CAN communication is bidirectional. The driver is translating a digital input
on TXD to a differential output on CANH and CANL. The receiver is translating the differential signal from CANH
and CANL to a digital output on RXD. In recessive state, the CAN bus pins (CANH and CANL) are biased to 0.5
× VCC. In dominant state, the bus pins are driven differentially apart. Logic high is equivalent to recessive on the
bus, and logic low is equivalent to a dominant (differential) signal on the bus.
Standby Mode With RXD Wake-Up Request
This is the low-power mode of the device. Standby mode is selected by setting STB high. The CAN driver and
main receiver are turned off and bidirectional CAN communication is not possible. The low-power receiver and
bus monitor, both supplied via the VIO supply, are enabled to allow for RXD wake-up requests via the CAN bus.
The VCC (5-V) supply may be turned off for additional power savings at the system level. A wake-up request is
output to RXD (driven low) for any dominant bus transmissions longer than the filter time tBUS. The local protocol
controller (MCU) should monitor RXD for transitions and then reactivate the device to normal mode based on the
wake-up request. The 5-V (VCC) supply must be reactivated by the local protocol controller to resume normal
mode if it has been turned off for low-power standby operation. The CAN bus pins are weakly pulled to GND, see
Figure 3 and Figure 4.
4
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RXD Wake-Up Request Lockout for Bus-Stuck Dominant Fault (HVDA551)
If the bus has a fault condition where it is stuck dominant while the HVDA551 is placed into standby mode via the
STB pin, the device locks out the RXD wake-up request until the fault has been removed to prevent false wakeup signals in the system.
Standby Mode, STB = High
STB
Bus VDiff
tBUS
<tBUS
<tBUS
tBUS
<tBUS
RXD
Figure 5. HVDA551 RXD Wake-Up Request With No Bus Fault Condition
STB
Standby Mode, STB = High
Bus VDiff
tBUS
tBUS
tBUS
tClear
<tClear
tBUS
<tBUS
RXD
Figure 6. HVDA551 RXD Wake-Up Request Lockout During Bus Dominant Fault Condition
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Driver and Receiver Function Tables
Table 4. Driver Function Table
INPUTS
DEVICE
STB / S (1)
Both Devices
HVDA551, HVDA553 (2)
(1)
(2)
OUTPUTS
CANL (1)
DRIVEN BUS
STATE
TXD (1)
CANH (1)
L
L
H
L
Dominant
L
H
Z
Z
Recessive
L
Open
Z
Z
Recessive
H
X
Y
Y
Recessive
H = high level, L = low level, X = irrelevant, Y = common-mode bias to GND, Z = common mode bias
to VCC / 2. See Figure 3 and Figure 4 for common mode bias information.
HVDA551 and HVDA553 have internal pullup to VIO on the STB pin. If the STB pin is open, the pin is
pulled high and the device is in standby mode.
Table 5. Receiver Function Table
DEVICE MODE
CAN DIFFERENTIAL INPUTS
VID = V(CANH) – V(CANL)
BUS STATE
RXD PIN (1)
Standby with RXD
wake-up request
(HVDA551,
HVDA553) (2)
VID ≥ 1.15 V
DOMINANT
L
0.4 V < VID < 1.15 V
?
?
VID ≤ 0.4 V
RECESSIVE
H
NORMAL
VID ≥ 0.9 V
DOMINANT
L
0.5 V < VID < 0.9 V
?
?
VID ≤ 0.5 V
RECESSIVE
H
Open
N/A
H
ANY
(1)
(2)
H = high level, L = low level, X = irrelevant, ? = indeterminate.
While STB is high (standby mode) the RXD output of the HVDA551 functions according to the levels
above and the wake-up conditions shown in Figure 5 and Figure 6.
Digital Inputs and Outputs
The HVDA551 device has an I/O supply voltage input pin (VIO) to ratiometrically level shift the digital logic input
and output levels with respect to VIO for compatibility with protocol controllers having I/O supply voltages between
3 V and 5.33 V.
The HVDA553 devices have a single VCC supply (5 V). The digital logic input and output levels for these devices
are with respect to VCC for compatibility with protocol controllers having I/O supply voltages between 4.68 V and
5.33 V.
Using the HVDA553 With Split Termination
The SPLIT pin voltage output provides 0.5 × VCC in normal mode. The circuit may be used by the application to
stabilize the common-mode voltage of the bus by connecting it to the center tap of split termination for the CAN
network (see Figure 7 and Figure 20). This pin provides a stabilizing recessive voltage drive to offset leakage
currents of unpowered transceivers or other bias imbalances that might bring the network common-mode voltage
away from 0.5 × VCC. Using this feature in a CAN network improves electromagnetic emissions behavior of the
network by eliminating fluctuations in the bus common-mode voltage levels at the start of message
transmissions.
6
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Figure 7. SPLIT Pin Circuitry and Application
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Protection Features
TXD Dominant State Time Out
During normal mode, the only mode where the CAN driver is active, the TXD dominant time-out circuit prevents
the transceiver from blocking network communication in the event of a hardware or software failure where TXD is
held dominant longer than the time-out period t(DOM). The dominant time-out circuit is triggered by a falling edge
on TXD. If no rising edge is seen before the time-out constant of the circuit expires (t(DOM)) the CAN bus driver is
disabled, freeing the bus for communication between other network nodes. The CAN driver is re-activated when
a recessive signal is seen on the TXD pin, thus clearing the dominant-state time-out. The CAN bus pins are
biased to the recessive level during a TXD dominant-state time-out.
APPLICATION NOTE: The maximum dominant TXD time allowed by the TXD dominant-state time-out limits the
minimum possible data rate of the devices. The CAN protocol allows a maximum of eleven successive dominant
bits (on TXD) for the worst case, where five successive dominant bits are followed immediately by an error
frame. This, along with the t(DOM) minimum, limits the minimum bit rate. The minimum bit rate may be calculated
by: Minimum Bit Rate = 11 / t(DOM).
Thermal Shutdown
If the junction temperature of the device exceeds the thermal shutdown threshold, the device turns off the CAN
driver circuits. This condition is cleared once the temperature drops below the thermal shutdown temperature of
the device. The CAN bus pins are biased to the recessive level during a thermal shutdown.
Undervoltage Lockout or Unpowered Device
Both of the supply pins have undervoltage detection, which places the device in forced standby mode to protect
the bus during an undervoltage event on either the VCC or VIO supply pins. If VIO is undervoltage, the RXD pin is
forced to the high-impedance state and the device does not pass any wake-up signals from the bus to the RXD
pin. Because the device is placed into forced standby mode, the CAN bus pins have a common-mode bias to
ground, protecting the CAN network; see Figure 3 and Figure 4.
The device is designed to be an ideal passive load to the CAN bus if it is unpowered. The bus pins (CANH,
CANL) have extremely low leakage currents when the device is unpowered, so they do not load down the bus
but rather be a no-load. This is critical, especially if some nodes of the network are unpowered while the rest of
the network remains in operation.
APPLICATION NOTE: Once an undervoltage condition is cleared and VCC and VIO have returned to valid levels,
the device typically requires 300 µs to transition to normal operation.
Table 6. Undervoltage Protection
DEVICE
Both devices
VCC
VIO
(3)
BUS
RXD
Mirrors bus state via wake-up
filter (2)
Bad
Good
Forced Standby Mode
Common mode
bias to GND (1)
Good
Bad
Forced Standby Mode (3)
Common mode
bias to GND (1)
High Z
Unpowered
No load
High Z
Unpowered
(1)
(2)
DEVICE STATE
See Figure 3 and Figure 4 for common-mode bias information.
See Figure 5 and Figure 6 for operation of the low-power wake-up receiver and bus monitor for RXD wake-up request behavior and
Table 5 for the wake-up receiver threshold levels.
When VIO is undervoltage, the device is forced into standby mode with respect to the CAN bus, because there is not a valid digital
reference to determine the digital I/O states or power the wake-up receiver.
Floating Pins
The device has integrated pullups and pulldowns on critical pins to place the device into known states if the pins
float. The TXD and STB pins on the HVDA551 are pulled up to VIO. This forces a recessive input level on TXD in
the case of a floating TXD pin and prevents the device from entering into the low-power standby mode if the STB
pin floats. In the case of the HVDA553 both the TXD and STB pins are pulled up to VCC, which has the same
effect.
8
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CAN Bus Short-Circuit Current Limiting
The device has several protection features that limit the short-circuit current when a CAN bus line is shorted.
These include CAN driver-current limiting (dominant and recessive) and TXD dominant-state time-out to prevent
continuously driving dominant. During CAN communication, the bus switches between dominant and recessive
states; thus, the short-circuit current may be viewed either as the current during each bus state or as a dc
average current. For system current and power considerations in termination resistance and common-mode
choke ratings, the average short-circuit current should be used. The device has TXD dominant-state time-out,
which prevents permanently having the higher short-circuit current of dominant state. The CAN protocol also has
forced state changes and recessive bits such as bit stuffing, control fields, and interframe space. These ensure
there is a minimum recessive amount of time on the bus even if the data field contains a high percentage of
dominant bits.
APPLICATION NOTE: The short-circuit current of the bus depends on the ratio of recessive to dominant bits and
their respective short-circuit currents. The average short-circuit current may be calculated with the following
formula:
IOS(AVG) = %Transmit × [(%REC_Bits × IOS(SS)_REC) + (%DOM_Bits × IOS(SS)_DOM)] + [%Receive × IOS(SS)_REC]
where IOS(AVG) is the average short-circuit current, %Transmit is the percentage the node is transmitting CAN
messages, %Receive is the percentage the node is receiving CAN messages, %REC_Bits is the percentage
of recessive bits in the transmitted CAN messages, %DOM_Bits is the percentage of dominant bits in the
transmitted CAN messages, IOS(SS)_REC is the recessive steady-state short-circuit current and IOS(SS)_DOM is
the dominant steady-state short-circuit current.
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ABSOLUTE MAXIMUM RATINGS (1)
(2)
1.1 VCC
Supply voltage range
–0.3 V to 6 V
1.2 VIO
I/O supply voltage range
–0.3 V to 6 V
1.3
Voltage range at bus terminals (CANH,
CANL)
–27 V to 40 V
1.4 IO
Receiver output current (RXD)
20 mA
1.5 VI
Voltage input range (TXD, STB, S)
1.6 TJ
Operating virtual-junction temperature
range
(1)
(2)
HVDA55x
–0.3 V to 6 V and VI ≤ VIO + 0.3 V
HVDA553
–0.3 V to 6 V
–40°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to the ground terminal.
ELECTROSTATIC DISCHARGE AND TRANSIENT PROTECTION (1)
PARAMETER
2.1
CANH and CANL
Human-body model (2)
2.2
2.3
TEST CONDITIONS
Electrostatic discharge
2.4
VALUE
(3)
±12 kV
All pins
±4 kV
Charged-device model (4)
All pins
±1 kV
IEC 61000-4-2 according to IBEE CAN
EMC Test Specification (5)
CANH and CANL pins to GND
±7 kV
2.5
Pulse 1
–100 V
2.6
Pulse 2a
75 V
Pulse 3a
–150 V
Pulse 3b
100 V
2.7
ISO 7637 transients
ISO7637 transients according to IBEE
CAN EMC Test Specification (6)
2.8
(1)
(2)
(3)
(4)
(5)
(6)
Stresses beyond those listed under Electrostatic Discharge and Transient Protection may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliability.
HBM tested in accordance with AEC-Q100-002.
HBM test method based on AEC-Q100-002, CANH and CANL bus pins stressed with respect to each other and GND.
CDM tested in accordance with AEC-Q100-011.
IEC 61000-4-2 is a system-level ESD test. Results given here are specific to the IBEE CAN EMC Test specification conditions. Different
system-level configurations lead to different results.
ISO 7637 is a system level transient test. Results given here are specific to the IBEE CAN EMC Test specification conditions. Different
system level configurations lead to different results.
RECOMMENDED OPERATING CONDITIONS
MIN
MAX
UNIT
4.68
5.33
V
3
5.33
V
–12
12
V
0.7 × VIO
VIO
V
0
0.3 × VIO
V
Between CANH and CANL
–6
6
RXD
–2
3.1
VCC
Supply voltage
3.2
VIO
I/O supply voltage
3.3
VI or VIC
Voltage at any bus terminal (separately or common mode)
3.4
VIH
High-level input voltage
TXD, STB (for HVD553: VIO = VCC)
3.5
VIL
Low-level input voltage
TXD, STB (for HVD553: VIO = VCC)
3.6
VID
Differential input voltage, bus
3.7
IOH
High-level output current
3.8
IOL
Low-level output current
RXD
TA
Operating ambient free-air
temperature
See Thermal Characteristics table
3.9
10
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–40
V
mA
2
mA
125
°C
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ELECTRICAL CHARACTERISTICS
over recommended operating conditions, TJ = –40°C to 150°C (unless otherwise noted), HVDA553 VIO = VCC
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
Supply Characteristics (HVDA551)
Standby
mode
(HVDA551
only)
4.1
4.2
ICC
5-V supply current
4.3
STB at VIO, VCC = 5.33 V, VIO = 3 V,
TXD at VIO (2)
5
Normal mode
TXD at 0 V, 60-Ω load, STB at 0 V
(dominant)
50
70
6.75
10
6.5
15
Normal mode VCC = 5.33V, RXD floating, TXD at 0
(dominant)
V
85
300
Normal mode VCC = 5.33V, RXD floating, TXD at
(recessive)
VIO
70
300
3.6
4
mA
Normal mode
TXD at VIO, no load, STB at 0 V
(recessive)
4.4
Standby
mode
(HVDA551
Only)
4.5
IIO
I/O supply current
4.6
4.7
UVVCC
Undervoltage detection on VCC for
forced standby mode
4.8
VHYS(UVVCC)
Hysteresis voltage for
undervoltage detection on UVVCC
for standby mode
4.9
UVVIO
Undervoltage detection on VIO for
forced standby mode
4.10
VHYS(UVVIO)
Hysteresis voltage for
undervoltage detection on UVVIO
for forced standby mode
µA
STB at VIO , VCC = 5.33 V or 0 V,
RXD floating, TXD at VIO
TA = -40°C, 25°C, 125°C (3)
µA
3.2
200
1.9
2.45
V
mV
2.95
130
V
mV
Supply Characteristics (HVDA553)
Standby
mode
(HVDA553
only)
4.1-5
4.2-5
ICC
5-V supply current
4.3-5
Normal mode
TXD at 0 V, 60-Ω load, STB at 0 V
(dominant)
4.7-5
UVVCC
Undervoltage detection on VCC for
forced standby mode
4.8-5
VHYS(UVVCC)
Hysteresis voltage for
undervoltage detection on UVVCC
for standby mode
(3)
12
50
70
6.75
10
3.6
4
µA
mA
Normal mode
TXD at VCC, No load, STB at 0 V
(recessive)
4.4-5
(1)
(2)
STB at VCC, VCC = 5.33 V,
TXD at VCC (2)
3.2
200
V
mV
All typical values are at 25°C and supply voltages of VCC = 5 V and VIO = 3.3 V.
The VCC supply is not needed during standby mode so in the application ICC in standby mode may be zero. If the VCC supply remains,
then ICC is per specification with VCC.
See HVDA55x Errata, Literature number SLLZ073.
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ELECTRICAL CHARACTERISTICS (continued)
over recommended operating conditions, TJ = –40°C to 150°C (unless otherwise noted), HVDA553 VIO = VCC
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
Device Switching Characteristics: Propagation Time (Loop Time TXD to RXD)
5.1
5.2
tPROP(LOOP1)
Total loop delay, driver input
(TXD) to receiver output (RXD),
recessive to dominant
tPROP(LOOP2)
Total loop delay, driver input
(TXD) to receiver output (RXD),
dominant to recessive
70
230
Figure 15, STB at 0 V
ns
70
230
Driver Electrical Characteristics
6.1
CANH
VI = 0 V, STB at 0 V, RL = 60 Ω,
See Figure 8 and Figure 3
VO(D)
Bus output voltage
(dominant)
6.3
VO®)
Bus output voltage (recessive)
VI = VIO, VIO = 3 V, STB at 0 V,
RL = 60 Ω, See Figure 8 and
Figure 3
6.4
VO(STBY)
Bus output voltage, standby mode
(HVDA551 only)
STB at VIO, RL = 60 Ω,
See Figure 8 and Figure 3
VOD(D)
Differential output voltage
(dominant)
6.2
6.5
6.6
6.7
VOD®)
6.8
CANL
Differential output voltage
(recessive)
2.9
4.5
0.8
1.75
2
3
V
–0.1
0.1
V
VI = 0 V, RL = 60 Ω, STB at 0 V,
See Figure 8, Figure 3, and Figure 9
1.5
3
VI = 0 V, RL = 45 Ω, STB at 0 V,
See Figure 8, Figure 3, and Figure 9
1.4
3
VI = 3 V, STB at 0 V, RL = 60 Ω, See
Figure 8 and Figure 3
–0.012
0.012
–0.5
0.05
VI = 3 V, STB at 0 V, No load
2.5
V
V
V
6.9
VSYM
Output symmetry (dominant or
recessive) (VO(CANH) + VO(CANL))
STB at 0 V, RL = 60 Ω,
See Figure 18
0.9 VCC
VCC
1.1 VCC
V
6.10
VOC(SS)
Steady-state common-mode
output voltage
STB at 0 V, RL = 60 Ω,
See Figure 14
2
2.5
3
V
6.11
ΔVOC(SS)
Change in steady-state commonmode output voltage
STB at 0 V, RL = 60 Ω,
See Figure 14
6.12
IOS(SS)_DOM
Short-circuit steady-state output
current, dominant
6.13
6.14
IOS(SS)_REC
6.15
6.16
12
CO
Short-circuit steady-state output
current, recessive
Output capacitance
50
VCANH = 0 V, CANL open, TXD =
low,
See Figure 17
mV
–100
mA
VCANL = 32 V, CANH open, TXD =
low, See Figure 17
100
–20 V ≤ VCANH ≤ 32 V, CANL open,
TXD = high, See Figure 17
–10
10
–20 V ≤ VCANL ≤ 32 V, CANH open,
TXD = high, See Figure 17
–10
10
mA
See receiver input capacitance
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ELECTRICAL CHARACTERISTICS (continued)
over recommended operating conditions, TJ = –40°C to 150°C (unless otherwise noted), HVDA553 VIO = VCC
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
Driver Switching Characteristics
7.1
tPLH
Propagation delay time, low-tohigh level output
STB at 0 V, See Figure 10
65
ns
7.2
tPHL
Propagation delay time, high-tolow level output
STB at 0 V, See Figure 10
50
ns
7.3
tR
Differential output signal rise time
STB at 0 V, See Figure 10
25
ns
7.4
tF
Differential output signal fall time
STB at 0 V, See Figure 10
55
ns
7.5
tEN
Enable time from standby or silent
See Figure 13
mode to normal mode, dominant
7.6
t(DOM)
(4)
Dominant time-out
See Figure 16
1200
30
µs
2000
2800
µs
800
900
mV
Receiver Electrical Characteristics
8.1
VIT+
Positive-going input threshold
voltage, normal mode
STB at 0 V, See Table 7
8.2
VIT–
Negative-going input threshold
voltage, normal mode
STB at 0 V, See Table 7
8.3
Vhys
Hysteresis voltage (VIT+ – VIT–)
8.4
VIT(STBY)
Input threshold voltage,
standby mode (HVDA551 only)
STB at VIO
8.5
II(OFF_LKG)
Power-off (unpowered) bus input
leakage current
CANH = CANL = 5 V, VCC at 0 V,
VIO at 0 V, TXD at 0 V
8.6
CI
Input capacitance to ground
(CANH or CANL)
HVDA551: TXD at VIO, VIO at 3.3 V.
HVDA553: TXD at VCC
VI = 0.4 sin (4E6πt) + 2.5 V
13
pF
8.7
CID
Differential input capacitance
HVDA551: TXD at VIO, VIO at 3.3 V.
HVDA553: TXD at VCC
VI = 0.4 sin(4E6πt)
5
pF
8.8
RID
Differential input resistance
8.9
RIN
Input resistance (CANH or CANL)
8.10
RI(M)
Input resistance matching
V(CANH) = V(CANL)
[1 – RIN(CANH) / RIN(CANL))] × 100%
HVDA551: TXD at VIO, VIO = 3.3 V,
STB at 0 V
HVDA553: TXD at VCC, STB at 0 V
500
650
mV
125
mV
400
29
1150
mV
3
µA
80
kΩ
kΩ
14.5
25
40
–3%
0%
3%
Receiver Switching Characteristics
9.1
tPLH
Propagation delay time, low-tohigh-level output
STB at 0 V , See Figure 12
95
ns
9.2
tPHL
Propagation delay time, high-tolow-level output
STB at 0 V , See Figure 12
60
ns
9.3
tR
Output signal rise time
STB at 0 V , See Figure 12
13
ns
9.4
tF
Output signal fall time
STB at 0 V , See Figure 12
10
ns
tBUS
Dominant time required on bus for
wake-up from standby (HVDA551
only)
1.5
5
µs
tCLEAR
Recessive time on the bus to clear STB at VIO, See Figure 5 and
the standby mode receiver output Figure 6
(RXD) if standby mode is entered
while bus is dominant (HVDA551
only)
1.5
5
µs
9.5
9.6
(4)
The TXD dominant time out (t(DOM)) disables the driver of the transceiver once the TXD has been dominant longer than t(DOM), which
releases the bus lines to recessive, preventing a local failure from locking the bus dominant. The driver may only transmit dominant
again after TXD has been returned HIGH (recessive). While this protects the bus from local faults, locking the bus dominant, it limits the
minimum data rate possible. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD) for the worst case,
where five successive dominant bits are followed immediately by an error frame. This, along with the t(DOM) minimum, limits the
minimum bit rate. The minimum bit rate may be calculated by: Minimum Bit Rate = 11 / t(DOM) = 11 bits / 300 µs = 37 kbps
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ELECTRICAL CHARACTERISTICS (continued)
over recommended operating conditions, TJ = –40°C to 150°C (unless otherwise noted), HVDA553 VIO = VCC
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
TXD Pin Characteristics
10.1
VIH
High-level input voltage
HVD553: VIO = VCC
10.2
VIL
Low-level input voltage
HVD553: VIO = VCC
10.3
IIH
High-level input current
HVDA551: TXD at VIO HVDA553:
TXD at VCC
10.4
IIL
Low-level input current
TXD at 0 V
0.7 × VIO
V
0.3 × VIO
V
-2
2
µA
–100
-7
µA
RXD Pin Characteristics
11.1
VOH
High-level output voltage
IO = –2 mA, See Figure 12 HVD553:
VIO = VCC
11.2
VOL
Low-level output voltage
IO = 2 mA, See Figure 12 HVD553:
VIO = VCC
0.8 × VIO
V
0.2 × VIO
V
STB Pin Characteristics
12.1
VIH
High-level input voltage
HVD553: VIO = VCC
12.2
VIL
Low-level input voltage
HVD553: VIO = VCC
12.3
IIH
High-level input current
HVDA551: STB at VIO HVDA553:
STB at VCC
12.4
IIL
Low-level input current
STB at 0 V
0.7 × VIO
–2
V
0.3 × VIO
V
2
µA
–20
µA
SPLIT Pin (HVDA553 Only)
14.1
VO
Output Voltage
–500 µA < IO < 500 µA
14.2
IO(STB)
Leakage current, standby mode
STB at VCC, –12 V ≤ IO ≤ 12 V
14
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0.3 VCC 0.5 VCC
–5
0.7 VCC
V
5
µA
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SLLSEC4 – JUNE 2013
THERMAL CHARACTERISTICS
over recommended operating conditions, TJ = –40°C to 150°C (unless otherwise noted), HVDA553 VIO = VCC
THERMAL METRIC (1) (2)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
THERMAL METRIC - SOIC D PACKAGE
14.1-D
Low-K thermal resistance
(3)
140
High-K thermal resistance
(4)
112
θJA
Junction-to-air thermal
resistance
14.3-D
θJB
Junction-to-board thermal
resistance (5)
50
14.4-D
θJC(TOP)
Junction-to-case (top) thermal
resistance (6)
56
14.5-D
θJC(BOTTOM)
Junction-to-case (bottom)
thermal resistance (7)
14.6-D
ΨJT
Junction-to-top
characterization parameter (8)
13
14.7-D
ΨJB
Junction-to-board
characterization parameter (9)
55
14.2-D
°C/W
N/A
AVERAGE POWER DISSIPATION AND THERMAL SHUTDOWN
14.8
PD
Average power dissipation
14.9
14.10
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
VCC = 5 V, VIO = VCC, TJ = 27°C, RL = 60
Ω,
STB at 0 V, Input to TXD at 500 kHz,
50% duty cycle square wave,
CL at RXD = 15 pF
140
mW
VCC = 5.33 V, VIO = VCC, TJ = 130°C,
RL = 60 Ω, STB at 0 V,
Input to TXD at 500 kHz,
50% duty cycle square wave,
CL at RXD = 15 pF
Thermal shutdown
temperature
215
185
°C
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction temperature (TJ) is calculated using the following TJ = TA + (PD × θJA). θJAis PCB-dependent; both JEDEC-standard low-K
and high-K values are given as reference points to standardized reference boards.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, low-K board, as
specified in JESD51-3, in an environment described in JESD51-2a.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold-plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-case (top) thermal resistance is obtained by simulating a cold-plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold-plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-top characterization parameter, ΨJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ΨJB estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
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PARAMETER MEASUREMENT INFORMATION
Figure 8. Driver Voltage, Current, and Test Definition
Figure 9. Driver VOD Test Circuit
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle,
tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
B.
CL includes instrumentation and fixture capacitance within ±20%.
C.
For HVDA553 device versions, VIO = VCC.
Figure 10. Driver Test Circuit and Voltage Waveforms
16
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SLLSEC4 – JUNE 2013
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 11. Receiver Voltage and Current Definitions
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle,
tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
B.
CL includes instrumentation and fixture capacitance within ±20%.
C.
C. For HVDA553 device versions VIO = VCC.
Figure 12. Receiver Test Circuit and Voltage Waveforms
Table 7. Differential Input Voltage Threshold Test
INPUT
OUTPUT
VCANH
VCANL
|VID|
–11.1 V
–12 V
900 mV
L
R
12 V
11.1 V
900 mV
L
–6 V
–12 V
6V
L
12 V
6V
6V
L
–11.5 V
–12 V
500 mV
H
12 V
11.5 V
500 mV
H
–12 V
–6 V
6V
H
6V
12 V
6V
H
Open
Open
X
H
VOL
VOH
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A.
CL = 100 pF includes instrumentation and fixture capacitance within ±20%.
B.
All VI input pulses are from 0 V to VIO and supplied by a generator having the following characteristics: tr or tf ≤ 6 ns.
Pulse repetition rate (PRR) = 25 kHz, 50% duty cycle.
C.
C. For HVDA553 device versions, VIO = VCC.
Figure 13. tEN Test Circuit and Waveforms
A.
All VI input pulses are from 0 V to VIO and supplied by a generator having the following characteristics: tr or tf ≤ 6 ns.
Pulse repetition rate (PRR) = 125 kHz, 50% duty cycle.
Figure 14. Common-Mode Output Voltage Test and Waveforms
18
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A.
CL = 100 pF includes instrumentation and fixture capacitance within ±20%.
B.
All VI input pulses are from 0 V to VIO and supplied by a generator having the following characteristics: tr or tf ≤ 6 ns.
Pulse repetition rate (PRR) = 125 kHz, 50% duty cycle.
C.
For HVDA553 device versions, VIO = VCC.
Figure 15. tPROP(LOOP) Test Circuit and Waveform
A.
CL = 100 pF includes instrumentation and fixture capacitance within ±20%.
B.
All VI input pulses are from 0 V to VIO and supplied by a generator having the following characteristics: tr or tf ≤ 6 ns.
Pulse repetition rate (PRR) = 500 Hz, 50% duty cycle.
C.
For HVDA553 device versions, VIO = VCC.
Figure 16. TXD Dominant Time-Out Test Circuit and Waveforms
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A.
www.ti.com
For HVDA553 device versions VIO = VCC.
Figure 17. Driver Short-Circuit Current Test and Waveforms
A.
All VI input pulses are from 0 V to VIO and supplied by a generator having the following characteristics: tr and
tf ≤ 6 ns, pulse repetition rate (PRR) = 250 kHz, 50% duty cycle.
Figure 18. Driver Output Symmetry Test Circuit
20
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SLLSEC4 – JUNE 2013
APPLICATION INFORMATION
Figure 19. Typical Application Using the HVDA551 With 3.3-V I/O Voltage Level in Low-Power Mode
(5-V VCC Not Needed in Low-Power Mode)
Figure 20. Typical Application Using the HVDA553 With SPLIT Termination
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PACKAGE OPTION ADDENDUM
www.ti.com
28-Jun-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
HVDA551QDRQ1
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
H551Q
HVDA553QDRQ1
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
H553Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Jul-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
HVDA551QDRQ1
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
HVDA553QDRQ1
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Jul-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
HVDA551QDRQ1
SOIC
D
8
2500
367.0
367.0
35.0
HVDA553QDRQ1
SOIC
D
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
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