SN65HVDA540-Q1, SN65HVDA541-Q1, SN65HVDA542-Q1 SN65HVDA540-5-Q1, SN65HVDA541-5-Q1, SN65HVDA542-5-Q1 www.ti.com SLLS804B – MARCH 2009 – REVISED SEPTEMBER 2010 5-V CAN TRANSCEIVER WITH I/O LEVEL ADAPTING AND LOW-POWER MODE SUPPLY OPTIMIZATION Check for Samples: SN65HVDA540-Q1, SN65HVDA541-Q1, SN65HVDA542-Q1, SN65HVDA540-5-Q1, SN65HVDA541-5-Q1, SN65HVDA542-5-Q1 FEATURES 1 • • • • • • • • • Qualified for Automotive Applications Meets or Exceeds the Requirements of ISO 11898-2 and ISO 11898-5 GIFT/ICT Compliant ESD Protection up to ±12 kV (Human-Body Model) on Bus Pins I/O Voltage Level Adapting – SN65HVDA54x: Adaptable I/O Voltage Range (VIO) From 3 V to 5.33 V – SN65HVDA54x-5: 5 V VCC Device Version Operating Modes: – Normal Mode: All Devices – Low Power Standby Mode (VCC not required, only VIO Supply Needed Saving System Power) – SN65HVDA540: No Wake Up – SN65HVDA541: RXD Wake Up Request – Silent (Receive Only) Mode: SN65HVDA542 High Electromagnetic Compliance (EMC) Package Options: SOIC and VSON Protection – Undervoltage Protection on VIO and VCC – Bus-Fault Protection of –27 V to 40 V – TXD Dominant State Time Out – RXD Wake Up Request Lock Out on CAN Bus Stuck Dominant Fault (SN65HVDA541) – Thermal Shutdown Protection – Power-Up/Down Glitch-Free Bus I/O – High Bus Input Impedance When Unpowered (No Bus Load) DESCRIPTION The device is designed and qualified for use in automotive applications and meets or exceeds the specifications of the ISO 11898 High Speed CAN (Controller Area Network) Physical Layer standard (transceiver). FUNCTIONAL BLOCK DIAGRAM APPLICATIONS • • • • • SAE J2284 High-Speed CAN for Automotive Applications SAE J1939 Standard Data Bus Interface GMW3122 Dual-Wire CAN Physical Layer ISO 11783 Standard Data Bus Interface NMEA 2000 Standard Data Bus Interface A. SN65HVDA54x devices pin 5 is VIO. SN65HVDA54x-5 devices pin 5 is NC and VIO is internally connected to VCC. B. SN65HVDA54x-5 devices: VIO is internally connected to VCC 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009–2010, Texas Instruments Incorporated SN65HVDA540-Q1, SN65HVDA541-Q1, SN65HVDA542-Q1 SN65HVDA540-5-Q1, SN65HVDA541-5-Q1, SN65HVDA542-5-Q1 SLLS804B – MARCH 2009 – REVISED SEPTEMBER 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. TERMINAL FUNCTIONS TERMINAL NAME D Package (SOIC) NO. DSJ Package (VSON) NO. TYPE TXD 1 1 I GND 2 2 GND VCC 3 3 Supply RXD 4 4 O VIO / NC 5 5 Supply DESCRIPTION CAN transmit data input (low for dominant bus state, high for recessive bus state) Ground connection Transceiver 5V supply voltage CAN receive data output (low in dominant bus state, high in recessive bus state) HVDA54x: Transceiver logic level (IO) supply voltage HVDA54x-5: No connect CANL 6 10 I/O Low level CAN bus line CANH 7 11 I/O High level CAN bus line STB / S 8 12 I NC N/A 6, 7, 8, 9 NC Mode select: STB, Standby mode (SN65HVDA540/541) select pin (active high) S, Silent mode (SN65HVDA542) select pin (active high) No connect ORDERING INFORMATION (1) PACKAGE (2) TA –40°C to 125°C –40°C to 125°C (1) (2) (3) 2 SOIC – D VSON – DSJ Reel of 2500 Reel of 3000 ORDERABLE PART NUMBER TOP-SIDE MARKING HVDA540QDRQ1 H540Q HVDA541QDRQ1 H541Q HVDA542QDRQ1 H542Q HVDA5405QDRQ1 H5405Q HVDA5415QDRQ1 H5415Q HVDA5425QDRQ1 H5425Q HVDA540QDSJRQ1 (3) H540Q HVDA541QDSJRQ1 (3) H541Q For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. Product Preview Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): SN65HVDA540-Q1 SN65HVDA541-Q1 SN65HVDA540-5-Q1 SN65HVDA541-5-Q1 SN65HVDA542-5-Q1 SN65HVDA540-Q1, SN65HVDA541-Q1, SN65HVDA542-Q1 SN65HVDA540-5-Q1, SN65HVDA541-5-Q1, SN65HVDA542-5-Q1 www.ti.com SLLS804B – MARCH 2009 – REVISED SEPTEMBER 2010 FUNCTIONAL DESCRIPTION Generaral Description The device meets or exceeds the specifications of the ISO 11898 High Speed CAN (Controller Area Network) Physical Layer standard (transceiver). This device provides CAN transceiver functions: differential transmit capability to the bus and differential receive capability at data rates up to 1 megabit per second (Mbps). The device includes many protection features providing device and CAN network robustness. Operating Modes The device has two main operating modes: normal mode (all devices) and standby mode (SN65HVDA540 / 541) or silent mode (SN65HVDA542). Operating mode selection is made via the STB (SN65HVDA540 / 541) or the S (SN65HVDA542) input pin. Table 1. Operating Modes DEVICE STB / S MODE DRIVER RECEIVER RXD Pin All Devices LOW Normal Mode Enabled (On) Enabled (On) Mirrors bus state (1) SN65HVDA540 HIGH Standby Mode (No Wake Up) Disabled (Off) Disabled (Off) Recessive (HIGH) SN65HVDA541 HIGH Standby Mode (RXD Wake Up Request) Disabled (Off) Low power wake-up receiver and bus monitor enabled Mirrors bus state via wake-up filter (2) SN65HVDA542 HIGH Silent Mode Disabled (Off) Enabled (On) Mirrors bus state (1) (1) (2) Mirrors bus state: LOW if CAN bus is dominant, HIGH if CAN bus is recessive. See Figure 3 and Figure 4 for operation of the low power wake up receiver and bus monitor for RXD Wake Up Request behavior and Table 3 for the wake up receiver threshold levels. Bus States by Mode The CAN bus has three valid states during powered operation depending on the mode of the device. In normal mode the bus may be dominant (logic LOW) where the bus lines are driven differentially apart or recessive (logic HIGH) where the bus lines are biased to VCC/2 via the high-ohmic internal input resistors RIN of the receiver. The third state is low power standby mode where the bus lines will be biased to GND via the high-ohmic internal input resistors RIN of the receiver. Typical Bus Voltage CANH Low Power Standby Mode Normal & Silent Mode VCC/2 A RXD CANH B CANL Vdiff Vdiff CANL A: Normal Mode B: Low Power Standby Mode Recessive Dominant Recessive Time, t Figure 1. Bus States (Physical Bit Representation) Figure 2. Simplified Common Mode Bias and Receiver Implementation Normal Mode This is the normal operating mode of the device. It is selected by setting STB or S low. The CAN driver and receiver are fully operational and CAN communication is bi-directional. The driver is translating a digital input on TXD to a differential output on CANH and CANL. The receiver is translating the differential signal from CANH and CANL to a digital output on RXD. In recessive state the CAN bus pins (CANH and CANL) are biased to 0.5 × VCC. In dominant state the bus pins are driven differentially apart. Logic high is equivalent to recessive on the bus and logic low is equivalent to a dominant (differential) signal on the bus. Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65HVDA540-Q1 SN65HVDA541-Q1 SN65HVDA540-5-Q1 SN65HVDA541-5-Q1 SN65HVDA542-5-Q1 3 SN65HVDA540-Q1, SN65HVDA541-Q1, SN65HVDA542-Q1 SN65HVDA540-5-Q1, SN65HVDA541-5-Q1, SN65HVDA542-5-Q1 SLLS804B – MARCH 2009 – REVISED SEPTEMBER 2010 www.ti.com Standby Mode (SN65HVDA540) This is the low power mode of the device. It is selected by setting STB high. The CAN driver and receiver are turned off and bi-directional CAN communication is not possible. There is no wake up capability in the SN65HVDA540, the RXD pin will remain recessive (high) while the device is in standby mode. This state is supplied via the VIO supply, thus the VCC (5V) supply may be turned off for additional power savings at the system level. The local protocol controller (MCU) should reactivate the device to normal mode to enable communication via the CAN bus. The 5 V (VCC) supply needs to be reactivated by the local protocol controller to resume normal mode if it has been turned off for low-power standby operation. The CAN bus pins are weakly pulled to GND, see Figure 1 and Figure 2. Standby Mode with RXD Wake Up-Request (SN65HVDA541) This is the low power mode of the device. It is selected by setting STB high. The CAN driver and main receiver are turned off and bi-directional CAN communication is not possible. The low power receiver and bus monitor, both supplied via the VIO supply, are enabled to allow for RXD wake up requests via the CAN bus. The VCC (5V) supply may be turned off for additional power savings at the system level. A wake up request will be output to RXD (driven low) for any dominant bus transmissions longer than the filter time tBUS. The local protocol controller (MCU) should monitor RXD for transitions and then reactivate the device to normal mode based on the wake up request. The 5 V (VCC) supply needs to be reactivated by the local protocol controller to resume normal mode if it has been turned off for low-power standby operation. The CAN bus pins are weakly pulled to GND, see Figure 1 and Figure 2. RXD Wake Up Request Lock Out for Bus Stuck Dominant Fault (SN65HVDA541) If the bus has a fault condition where it is stuck dominant while the SN65HVDA541 is placed into standby mode via the STB pin, the device locks out the RXD wake up request until the fault has been removed to prevent false wake up signals in the system. Standby Mode, STB = High STB Bus VDiff tBUS <tBUS tBUS <tBUS <tBUS RXD Figure 3. SN65HVDA541 RXD Wake Up Request With No Bus Fault Condition STB Standby Mode, STB = High Bus VDiff tBUS tBUS tBUS tClear <tClear tBUS <tBUS RXD Figure 4. SN65HVDA541 RXD Wake Up Request Lock Out When Bus Dominant Fault Condition Silent (Receive Only) Mode (SN65HVDA542) This is the silent (receive only) mode of the device. It is selected by setting S high. The CAN driver is turned off while the receiver remains active and RXD will output the received bus state. There is no low power mode in the SN65HVDA542 except for VCC and VIO supply undervoltage conditions (see Undervoltage Lockout / Unpowered Device section of the datasheet). 4 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): SN65HVDA540-Q1 SN65HVDA541-Q1 SN65HVDA540-5-Q1 SN65HVDA541-5-Q1 SN65HVDA542-5-Q1 SN65HVDA540-Q1, SN65HVDA541-Q1, SN65HVDA542-Q1 SN65HVDA540-5-Q1, SN65HVDA541-5-Q1, SN65HVDA542-5-Q1 www.ti.com SLLS804B – MARCH 2009 – REVISED SEPTEMBER 2010 Driver and Receiver Function Tables Table 2. Driver Function Table INPUTS DEVICE STB / S (1) All Devices OUTPUTS CANL (1) DRIVEN BUS STATE TXD (1) CANH (1) L L H L Dominant L H Z Z Recessive L Open Z Z Recessive SN65HVDA540/541 (2) H X Y Y Recessive SN65HVDA542 (3) H X Z Z Recessive (1) (2) (3) H = high level, L = low level, X = irrelevant, Y = common mode bias to GND, Z = common mode bias to VCC/2. See Figure 1 and Figure 2 for common mode bias information. SN65HVDA540/541 have internal pull up to VIO on STB pin. If STB pin is open the pin will be pulled high and the device will be in standby mode. SN65HVDA542 has internal pull down to GND on S pin. If S pin is open the pin will be pulled low and the device will be in normal mode. Table 3. Receiver Function Table CAN DIFFERENTIAL INPUTS VID = V(CANH) – V(CANL) BUS STATE RXD PIN (1) STANDBY (SN65HVDA540) (2) X X H STANDBY WITH RXD WAKE UP REQUEST (SN65HVDA541) (3) VID ≥ 1.15 V DOMINANT L 0.4 V < VID < 1.15 V ? ? VID ≤ 0.4 V RECESSIVE H NORMAL OR SILENT VID ≥ 0.9 V DOMINANT L DEVICE MODE ANY (1) (2) (3) 0.5 V < VID < 0.9 V ? ? VID ≤ 0.5 V RECESSIVE H Open N/A H H = high level, L = low level, X = irrelevant, ? = indeterminate. While STB is high (standby mode) the RXD output of the SN65HVDA540 is always high (recessive) because it has no wake-up receiver. While STB is high (standby mode) the RXD output of the SN65HVDA541 functions according to the levels above and the wake-up conditions shown in Figure 3 and Figure 4. Digital Inputs and Outputs The SN65HVDA54x devices have an I/O supply voltage input pin (VIO) to ratiometrically level shift the digital logic input and output levels with respect to VIO for compatibility with protocol controllers having I/O supply voltages between 3 V and 5.33 V. The SN65HVDA54x-5 devices have a single VCC supply (5V). The digital logic input and output levels for these devices are with respect to VCC for compatibility with protocol controllers having I/O supply voltages between 4.68 V and 5.33 V. Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65HVDA540-Q1 SN65HVDA541-Q1 SN65HVDA540-5-Q1 SN65HVDA541-5-Q1 SN65HVDA542-5-Q1 5 SN65HVDA540-Q1, SN65HVDA541-Q1, SN65HVDA542-Q1 SN65HVDA540-5-Q1, SN65HVDA541-5-Q1, SN65HVDA542-5-Q1 SLLS804B – MARCH 2009 – REVISED SEPTEMBER 2010 www.ti.com Protection Features TXD Dominant State Time Out During normal mode, the only mode where the CAN driver is active, the TXD dominant time out circuit prevents the transceiver from blocking network communication in event of a hardware or software failure where TXD is held dominant longer than the time out period t(DOM). The dominant time out circuit is triggered by a falling edge on TXD. If no rising edge is seen before the time out constant of the circuit expires (t(DOM)) the CAN bus driver is disabled freeing the bus for communication between other network nodes. The CAN driver is re-activated when a recessive signal is seen on TXD pin, thus clearing the dominant state time out. The CAN bus pins will be biased to recessive level during a TXD dominant state time out. APPLICATION NOTE: The maximum dominant TXD time allowed by the TXD Dominant state time out limits the minimum possible data rate of the device. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD) for the worst case, where five successive dominant bits are followed immediately by an error frame. This, along with the t(DOM) minimum, limits the minimum bit rate. The minimum bit rate may be calculated by: Minimum Bit Rate = 11/t(DOM) Thermal Shutdown If the junction temperature of the device exceeds the thermal shut down threshold the device will turn off the CAN driver circuits. This condition is cleared once the temperature drops below the thermal shut down temperature of the device. The CAN bus pins will be biased to recessive level during a thermal shutdown. Undervoltage Lockout / Unpowered Device Both of the supply pins have undervoltage detection which place the device in forced standby mode to protect the bus during an undervoltage event on either the VCC or VIO supply pins. If VIO is undervoltage the RXD pin is tri-stated and the device does not pass any wake-up signals from the bus to the RXD pin. Since the device is placed into forced standby mode the CAN bus pins have a common mode bias to ground protecting the CAN network, see Figure 1 and Figure 2. The device is designed to be an "ideal passive" load to the CAN bus if it is unpowered. The bus pins (CANH, CANL) have extremely low leakage currents when the device is un-powered so they will not load down the bus but rather be "no load". This is critical, especially if some nodes of the network will be unpowered while the rest of the network remains in operation. APPLICATION NOTE: Once an undervoltage condition is cleared and the VCC and VIO have returned to valid levels the device will typically need 300 µs to transition to normal operation. Table 4. Undervoltage Protection DEVICE VCC VIO SN65HVDA540 SN65HVDA541 Bad Good SN65HVDA542 (3) 6 BUS RXD Forced Standby Mode Common mode bias to GND (1) HIGH (Recessive) Forced Standby Mode Common mode bias to GND (1) Mirrors bus state via wake-up filter (2) Forced Standby Mode Common mode bias to GND (1) HIGH (Recessive) SN65HVDA54x Good Bad Forced Standby Mode (3) Common mode bias to GND (1) tri-state SN65HVDA54x-5 Bad N/A Forced Standby Mode Common mode bias to GND (1) HIGH (Recessive) or tri-state Unpowered No Load High Z All Devices (1) (2) DEVICE STATE Unpowered See Figure 1 and Figure 2 for common mode bias information. See Figure 3 and Figure 4 for operation of the low power wake up receiver and bus monitor for RXD Wake Up Request behavior and Table 3 for the wake up receiver threshold levels. When VIO is undervoltage, the device is forced into standby mode with respect to the CAN bus since there is not a valid digital reference to determine the digital I/O states or power the wake-up receiver. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): SN65HVDA540-Q1 SN65HVDA541-Q1 SN65HVDA540-5-Q1 SN65HVDA541-5-Q1 SN65HVDA542-5-Q1 SN65HVDA540-Q1, SN65HVDA541-Q1, SN65HVDA542-Q1 SN65HVDA540-5-Q1, SN65HVDA541-5-Q1, SN65HVDA542-5-Q1 www.ti.com SLLS804B – MARCH 2009 – REVISED SEPTEMBER 2010 Floating Pins The device has integrated pull up and pull downs on critical pins to place the device into known states if the pins float. The TXD pin is pulled up to VIO to force a recessive input level if the pin floats. The STB is pulled up to the IO supply pin, VIO(SN65HVDA540 and SN65HVDA541), or VCC (SN65HVDA540-5 and SN65HVDA541-5) to force the device in standby mode (low power) if the pin floats. The S pin is pulled down to GND to force the device into normal mode if the pin floats (SN65HVDA542 and SN65HVDA542-5). CAN Bus Short Circuit Current Limiting The device has several protection features that limit the short circuit current when a CAN bus line is shorted. These include CAN driver current limiting (dominant and recessive) and TXD dominant state time out to prevent continuously driving dominant. During CAN communication the bus switches between dominant and recessive states, thus the short circuit current may be viewed either as the current during each bus state or as a DC average current. For system current and power considerations in termination resistance and common mode choke ratings the average short circuit current should be used. The device has TXD dominant state time out which prevents permanently having the higher short circuit current of dominant state. The CAN protocol also has forced state changes and recessive bits such as bit stuffing, control fields, and interframe space. These ensure there is a minimum recessive amount of time on the bus even if the data field contains a high percentage of dominant bits. APPLICATION NOTE: The short circuit current of the bus depends on the ratio of recessive to dominant bits and their respective short circuit currents. The average short circuit current may be calculated with the following formula: IOS(AVG) = %Transmit * [(%REC_Bits * IOS(SS)_REC) + (%DOM_Bits * IOS(SS)_DOM)] + [%Receive * IOS(SS)_REC] Where IOS(AVG) is the average short circuit current, %Transmit is the percentage the node is transmitting CAN messages, %Receive is the percentage the node is receiving CAN messages, %REC_Bits is the percentage of recessive bits in the transmitted CAN messages, %DOM_Bits is the percentage of dominant bits in the transmitted CAN messages, IOS(SS)_REC is the recessive steady state short circuit current and IOS(SS)_DOM is the dominant steady state short circuit current. PCB and Thermal Considerations for VSON Package The VSON package verson of this device has an exposed thermal pad which should be connected with vias to a thermal plane. Even though this pad is not electrically connected internally it is recommended that the exposed pad be connected to the GND plane. Please refer to the mechanical information on the package at the end of this datasheet and application report SLUA271 "QFN/SON PCB Attachement" for more information on proper use of this package. Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65HVDA540-Q1 SN65HVDA541-Q1 SN65HVDA540-5-Q1 SN65HVDA541-5-Q1 SN65HVDA542-5-Q1 7 SN65HVDA540-Q1, SN65HVDA541-Q1, SN65HVDA542-Q1 SN65HVDA540-5-Q1, SN65HVDA541-5-Q1, SN65HVDA542-5-Q1 SLLS804B – MARCH 2009 – REVISED SEPTEMBER 2010 ABSOLUTE MAXIMUM RATINGS (1) www.ti.com (2) 1.1 VCC Supply voltage range –0.3 V to 6 V 1.2 VIO I/O supply voltage range –0.3 V to 6 V 1.3 Voltage range at bus terminals (CANH, CANL) –27 V to 40 V 1.4 IO Receiver output current (RXD) 1.5 VI Voltage input range (TXD, STB, S) 1.6 TJ Operating virtual-junction temperature range 1.7 TLEAD Lead temperature (soldering, 10 seconds) (1) (2) 20 mA SN65HVDA54x –0.3 V to 6 V and VI ≤ VIO + 0.3 V SN65HVDA54x-5 –0.3 V to 6 V –40°C to 150°C 260°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential I/O bus voltages, are with respect to ground terminal. ELECTROSTATIC DISCHARGE AND TRANSIENT PROTECTION (1) PARAMETER 2.1 Human-Body Model (2) 2.2 2.3 TEST CONDITIONS Electrostatic Discharge Charged-Device Model (4) 2.4 Machine Model (5) 2.5 IEC 61000-4-2 according to IBEE CAN EMC Test Specification (6) VALUE CANH and CANL (3) ±12 kV All pins ±4 kV All pins ±1 kV ±200 V ±7 kV CANH and CANL pins to GND 2.6 Pulse 1 -100 V 2.7 Pulse 2a +75 V 2.8 ISO 7637 Transients ISO7637 transients according to IBEE CAN EMC Test Specification (7) 2.9 (1) (2) (3) (4) (5) (6) (7) Pulse 3a -150 V Pulse 3b +100 V Stresses beyond those listed under "electrostatic discharge and transient protection" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. HBM Tested in accordance with AEC-Q100-002. HBM test method based on AEC-Q100-002, CANH and CANL bus pins stressed with respect to each other and GND. CDM Tested in accordance with AEC-Q100-011. MM Tested in accordance with AEC-Q100-003. IEC 61000-4-2 is a system level ESD test. Results given here are specific to the IBEE CAN EMC Test specification conditions. Different system level configurations will lead to different results. ISO 7637 is a system level transient test. Results given here are specific to the IBEE CAN EMC Test specification conditions. Different system level configurations will lead to different results. RECOMMENDED OPERATING CONDITIONS 8 MIN MAX UNIT 4.68 5.33 V 3 5.33 V –12 12 V 0.7 × VIO VIO V 0 0.3 × VIO V Between CANH and CANL –6 6 RXD –2 3.1 VCC Supply voltage 3.2 VIO I/O supply voltage 3.3 VI or VIC Voltage at any bus terminal (separately or common mode) 3.4 VIH High-level input voltage TXD, STB, S(for SN65HVD54x-5: VIO = VCC) 3.5 VIL Low-level input voltage TXD, STB, S (for SN65HVD54x-5: VIO = VCC) 3.6 VID Differential input voltage, bus 3.7 IOH High-level output current 3.8 IOL Low-level output current RXD 3.9 TA Operating ambient free-air temperature See Thermal Characteristics table Submit Documentation Feedback -40 V mA 2 mA 125 °C Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): SN65HVDA540-Q1 SN65HVDA541-Q1 SN65HVDA540-5-Q1 SN65HVDA541-5-Q1 SN65HVDA542-5-Q1 SN65HVDA540-Q1, SN65HVDA541-Q1, SN65HVDA542-Q1 SN65HVDA540-5-Q1, SN65HVDA541-5-Q1, SN65HVDA542-5-Q1 www.ti.com SLLS804B – MARCH 2009 – REVISED SEPTEMBER 2010 ELECTRICAL CHARACTERISTICS over recommended operating conditions, TJ = –40°C to 150°C (unless otherwise noted), SN65HVDA54x-5 devices VIO = VCC PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT Supply Characteristics (SN65HVDA54x) Standby mode (SN65HVDA 540/541 Only) 4.1 STB at VIO, VCC = 5.33 V, VIO = 3 V, TXD at VIO (2) 5 Normal mode TXD at 0 V, 60-Ω load, STB / S at 0 (Dominant) V 50 70 4.3 Normal mode TXD at VIO, No load, STB / S at 0 V (Recessive) or S at VIO 5.5 10 4.4 Silent Mode (SN65HVDA 542 only) TXD at VIO, No load, STB / S at 0 V or S at VIO 5.5 10 4.5 Standby mode (SN65HVDA 540/541 Only) STB at VIO , VCC = 5.33 V or 0 V, RXD floating, TXD at VIO 7 15 Normal mode (recessive or dominant) and Silent Mode (SN65HVDA 542 Only) VCC = 5.33 V, RXD floating, TXD at 0 V or VIO. Normal Mode: STB or S at 0 V. Silent Mode (SN65HVDA542): S at VIO. 4.2 ICC 5-V supply current IIO I/O supply current 4.6 4.7 UVVCC Undervoltage detection on VCC for forced standby mode 4.8 VHYS(UVVCC) Hysteresis voltage for undervoltage detection on UVVCC for standby mode 4.9 UVVIO Undervoltage detection on VIO for forced standby mode 4.10 VHYS(UVVIO) Hysteresis voltage for undervoltage detection on UVVIO for forced standby mode µA mA µA 3.2 75 300 3.6 4 200 1.9 2.45 V mV 2.95 130 V mV Supply Characteristics (SN65HVDA54x-5) Standby mode (SN65HVDA 540-5/541-5 Only) 4.1-5 STB at VCC, VCC = 5.33 V, TXD at VCC (2) 20 Normal mode TXD at 0 V, 60-Ω load, STB / S at 0 (Dominant) V 50 70 4.3-5 Normal mode TXD at VIO, No load, STB / S at 0 V (Recessive) or S at VIO 5.5 10 4.4-5 Silent Mode (SN65HVDA 542 only) 5.5 10 3.6 4 4.2-5 ICC 5-V supply current 4.7-5 UVVCC Undervoltage detection on VCC for forced standby mode 4.8-5 VHYS(UVVCC) Hysteresis voltage for undervoltage detection on UVVCC for standby mode (1) (2) TXD at VIO, No load, STB / S at 0 V or S at VIO 3.2 240 µA mA V mV All typical values are at 25°C and supply voltages of VCC = 5 V and VIO = 3.3 V. The VCC supply is not needed during standby mode so in the application ICC in standby mode may be zero. If the VCC supply remains, then ICC is per specification with VCC. Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65HVDA540-Q1 SN65HVDA541-Q1 SN65HVDA540-5-Q1 SN65HVDA541-5-Q1 SN65HVDA542-5-Q1 9 SN65HVDA540-Q1, SN65HVDA541-Q1, SN65HVDA542-Q1 SN65HVDA540-5-Q1, SN65HVDA541-5-Q1, SN65HVDA542-5-Q1 SLLS804B – MARCH 2009 – REVISED SEPTEMBER 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) over recommended operating conditions, TJ = –40°C to 150°C (unless otherwise noted), SN65HVDA54x-5 devices VIO = VCC PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT Device Switching Characteristics: Propagation Time (Loop Time TXD to RXD) 5.1 5.2 tPROP(LOOP1) Total loop delay, driver input (TXD) to receiver output (RXD), recessive to dominant tPROP(LOOP2) Total loop delay, driver input (TXD) to receiver output (RXD), dominant to recessive 70 230 Figure 12, STB at 0 V ns 70 230 2.9 4.5 0.8 1.75 Driver Electrical Characteristics 6.1 CANH VI = 0 V, STB / S at 0 V, RL = 60 Ω, See Figure 5 and Figure 1 VO(D) Bus output voltage (dominant) 6.3 VO(R) Bus output voltage (recessive) VI = VIO, VIO = 3 V, STB at 0 V or S at X (3), RL = 60 Ω, See Figure 5 and Figure 1 6.4 VO(STBY) Bus output voltage, standby mode (SN65HVDA540, SN65HVDA541 only) STB / S at VIO, RL = 60 Ω, See Figure 5 and Figure 1 VOD(D) Differential output voltage (dominant) 6.2 6.5 6.6 6.7 CANL Differential output voltage (recessive) VOD(R) 6.8 3 V –0.1 0.1 V VI = 0 V, RL = 60 Ω, STB / S at 0 V, See Figure 5, Figure 1, and Figure 6 1.5 3 VI = 0 V, RL = 45 Ω, STB / S at 0 V, See Figure 5, Figure 1, and Figure 6 1.4 3 –0.012 0.012 –0.5 0.05 VI = 3 V, STB / S at 0 V, RL = 60 Ω, See Figure 5 and Figure 1 VI = 3 V, STB / S at 0 V, No load 2 2.5 V V V 6.9 VSYM Output symmetry (dominant or recessive) (VO(CANH) + VO(CANL)) STB / S at 0 V, RL = 60 Ω, See Figure 15 0.9 VCC VCC 1.1 VCC V 6.10 VOC(SS) Steady-state common-mode output voltage STB / S at 0 V, RL = 60 Ω, See Figure 11 2 2.5 3 V 6.11 ΔVOC(SS) Change in steady-state common-mode output voltage STB / S at 0 V, RL = 60 Ω, See Figure 11 6.12 IOS(SS)_DOM Short-circuit steady-state output current, Dominant 6.13 6.14 IOS(SS)_REC 6.15 6.16 (3) 10 CO Short-circuit steady-state output current, Recessive Output capacitance 40 VCANH = 0 V, CANL open, TXD = low, See Figure 14 mV -100 mA VCANL = 32 V, CANH open, TXD = low, See Figure 14 100 –20 V ≤ VCANH ≤ 32 V, CANL open, TXD = high, See Figure 14 -10 10 –20 V ≤ VCANL ≤ 32 V, CANH open, TXD = high, See Figure 14 -10 10 mA See receiver input capacitance For the SN65HVDA542 device the bus output voltage (recessive) will be the same if the device is in normal mode with S pin at 0 V or if the device is in silent mode with the S pin at HIGH. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): SN65HVDA540-Q1 SN65HVDA541-Q1 SN65HVDA540-5-Q1 SN65HVDA541-5-Q1 SN65HVDA542-5-Q1 SN65HVDA540-Q1, SN65HVDA541-Q1, SN65HVDA542-Q1 SN65HVDA540-5-Q1, SN65HVDA541-5-Q1, SN65HVDA542-5-Q1 www.ti.com SLLS804B – MARCH 2009 – REVISED SEPTEMBER 2010 ELECTRICAL CHARACTERISTICS (continued) over recommended operating conditions, TJ = –40°C to 150°C (unless otherwise noted), SN65HVDA54x-5 devices VIO = VCC PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT Driver Switching Characteristics 7.1 tPLH Propagation delay time, low-to-high level output STB / S at 0 V, See Figure 7 65 ns 7.2 tPHL Propagation delay time, high-to-low level output STB / S at 0 V, See Figure 7 50 ns 7.3 tR Differential output signal rise time STB / S at 0 V, See Figure 7 25 ns 7.4 tF Differential output signal fall time STB / S at 0 V, See Figure 7 55 ns 7.5 tEN Enable time from standby or silent See Figure 10 mode to normal mode dominant 7.6 t(DOM) (4) Dominant time out See Figure 13 300 20 µs 400 700 µs 800 900 mV Receiver Electrical Characteristics 8.1 VIT+ Positive-going input threshold voltage, normal mode STB / S at 0 V, See Table 5 8.2 VIT– Negative-going input threshold voltage, normal mode STB / S at 0 V, See Table 5 8.3 Vhys Hysteresis voltage (VIT+ – VIT–) 8.4 VIT(STBY) Input threshold voltage, standby mode (SN65HVDA541 only) STB at VIO 8.5 II(OFF_LKG) Power-off (unpowered) bus input leakage current CANH = CANL = 5 V, VCC at 0 V, VIO at 0 V, TXD at 0 V 8.6 CI Input capacitance to ground (CANH or CANL) SN65HVDA54x: TXD at VIO, VIO at 3.3 V. SN65HVDA54x-5: TXD at VCC VI = 0.4 sin (4E6pt) + 2.5 V 13 pF SN65HVDA54x: TXD at VIO, VIO at 3.3 V. SN65HVDA54x-5: TXD at VCC VI = 0.4 sin(4E6pt) 5 pF 8.7 CID Differential input capacitance 8.8 RID Differential input resistance 8.9 RIN Input resistance (CANH or CANL) 8.10 RI(M) Input resistance matching [1 – ®IN(CANH)/RIN(CANL))] × 100% SN65HVDA54x: TXD at VIO, VIO = 3.3 V, STB at 0 V SN65HVDA54x-5: TXD at VCC, STB at 0 V V(CANH) = V(CANL) 500 650 mV 100 125 mV 400 29 1150 mV 3 µA 80 kΩ 14.5 25 40 kΩ –3 0 3 % Receiver Switching Characteristics 9.1 tPLH Propagation delay time, low-to-high-level output STB / S at 0 V , See Figure 9 95 ns 9.2 tPHL Propagation delay time, high-to-low-level output STB / S at 0 V , See Figure 9 60 ns 9.3 tR Output signal rise time STB / S at 0 V , See Figure 9 13 ns 9.4 tF Output signal fall time STB / S at 0 V , See Figure 9 10 ns tBUS Dominant time required on bus for wake-up from standby (SN65HVDA541 only) 1.5 5 µs tCLEAR Recessive time on the bus to clear STB at VIO, See Figure 3 and the standby mode receiver output Figure 4 (RXD) if standby mode is entered while bus is dominant (SN65HVDA541 only) 1.5 5 µs 9.5 9.6 (4) The TXD dominant time out (t(DOM)) disables the driver of the transceiver once the TXD has been dominant longer than t(DOM), which releases the bus lines to recessive, preventing a local failure from locking the bus dominant. The driver may only transmit dominant again after TXD has been returned HIGH (recessive). While this protects the bus from local faults, locking the bus dominant, it limits the minimum data rate possible. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD) for the worst case, where five successive dominant bits are followed immediately by an error frame. This, along with the t(DOM) minimum, limits the minimum bit rate. The minimum bit rate may be calculated by: Minimum Bit Rate = 11/ t(DOM) = 11 bits / 300 µs = 37 kbps Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65HVDA540-Q1 SN65HVDA541-Q1 SN65HVDA540-5-Q1 SN65HVDA541-5-Q1 SN65HVDA542-5-Q1 11 SN65HVDA540-Q1, SN65HVDA541-Q1, SN65HVDA542-Q1 SN65HVDA540-5-Q1, SN65HVDA541-5-Q1, SN65HVDA542-5-Q1 SLLS804B – MARCH 2009 – REVISED SEPTEMBER 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) over recommended operating conditions, TJ = –40°C to 150°C (unless otherwise noted), SN65HVDA54x-5 devices VIO = VCC PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT TXD Pin Characteristics 10.1 VIH High-level input voltage SN65HVD54x-5: VIO = VCC 10.2 VIL Low-level input voltage SN65HVD54x-5: VIO = VCC 0.7 × VIO 10.3 IIH High-level input current SN65HVDA54x: TXD at VIO SN65HVDA54x-5: TXD at VCC 10.4 IIL Low-level input current TXD at 0 V V 0.3 × VIO V -2 2 µA –100 -7 µA RXD Pin Characteristics 11.1 VOH High-level output voltage IO = –2 mA, See Figure 9 SN65HVD54x-5: VIO = VCC 11.2 VOL Low-level output voltage IO = 2 mA, See Figure 9 SN65HVD54x-5: VIO = VCC 0.8 × VIO V 0.2 × VIO V STB Pin Characteristics (SN65HVDA540 and SN65HVDA541 Only) 12.1 VIH High-level input voltage SN65HVD54x-5: VIO = VCC 12.2 VIL Low-level input voltage SN65HVD54x-5: VIO = VCC 0.7 × VIO 12.3 IIH High-level input current SN65HVDA54x: STB at VIO SN65HVDA54x-5: STB at VCC 12.4 IIL Low-level input current STB at 0 V V 0.3 × VIO V 2 µA –2 –20 µA 0.7 × VIO V S Pin Characteristics (SN65HVDA542 Only) 13.1 VIH High-level input voltage SN65HVD54x-5: VIO = VCC 13.2 VIL Low-level input voltage SN65HVD54x-5: VIO = VCC 0.3 × VIO V 30 µA 2 µA 13.3 IIH High-level input current SN65HVDA54x: S at VIO SN65HVDA54x-5: S at VCC 13.4 IIL Low-level input current S at 0 V 12 Submit Documentation Feedback –2 Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): SN65HVDA540-Q1 SN65HVDA541-Q1 SN65HVDA540-5-Q1 SN65HVDA541-5-Q1 SN65HVDA542-5-Q1 SN65HVDA540-Q1, SN65HVDA541-Q1, SN65HVDA542-Q1 SN65HVDA540-5-Q1, SN65HVDA541-5-Q1, SN65HVDA542-5-Q1 www.ti.com SLLS804B – MARCH 2009 – REVISED SEPTEMBER 2010 THERMAL CHARACTERISTICS over recommended operating conditions, TJ = –40°C to 150°C (unless otherwise noted), SN65HVDA54x-5 devices VIO = VCC THERMAL METRIC (1) (2) TEST CONDITIONS MIN TYP MAX UNIT THERMAL METRIC - SOIC 'D' PACKAGE 14.1-D Low-K thermal resistance (3) 140 High-K thermal resistance (4) 112 qJA Junction-to-air thermal resistance 14.3-D qJB Junction-to-board thermal resistance (5) 50 14.4-D qJC(TOP) Junction-to-case (top) thermal resistance (6) 56 14.5-D qJC(BOTTOM) Junction-to-case (bottom) thermal resistance (7) 14.6-D ΨJT Junction-to-top characterization parameter (8) 13 14.7-D ΨJB Junction-to-board characterization parameter (9) 55 14.2-D °C/W N/A THERMAL METRIC - VSON 'DSJ' PACKAGE 14.1-DSJ 14.2-DSJ Junction-to-air thermal resistance qJA Low-K thermal resistance (3) 290 High-K thermal resistance (with thermal vias) (4) 52 14.3-DSJ qJB Junction-to-board thermal resistance (5) 14 14.4-DSJ qJC(TOP) Junction-to-case (top) thermal resistance (6) 56 14.5-DSJ qJC(BOTTOM) Junction-to-case (bottom) thermal resistance (7) 4.5 14.6-DSJ ΨJT Junction-to-top characterization parameter (8) 6 14.7-DSJ ΨJB Junction-to-board characterization parameter (9) 19 °C/W AVERAGE POWER DISSIPATION AND THERMAL SHUTDOWN 14.8 PD Average power dissipation 14.9 14.10 (1) (2) (3) (4) (5) (6) (7) (8) (9) Thermal shutdown temperature VCC = 5 V, VIO = VCC, TJ = 27°C, RL = 60 Ω, STB at 0 V, Input to TXD at 500 kHz, 50% duty cycle square wave, CL at RXD = 15 pF 140 mW VCC = 5.33 V, VIO = VCC, TJ = 130°C, RL = 60 Ω, STB at 0 V, Input to TXD at 500 kHz, 50% duty cycle square wave, CL at RXD = 15 pF 215 185 °C For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction temperature (TJ) is calculated using the following TJ = TA + (PD × qJA). qJAis PCB dependent, both JEDEC-standard Low-K and High-K values are given as reference points to standardized reference boards. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, Low-K board, as specified in JESD51-3, in an environment described in JESD51-2a. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-top characterization parameter, ΨJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining qJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ΨJB estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining qJA , using a procedure described in JESD51-2a (sections 6 and 7). Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65HVDA540-Q1 SN65HVDA541-Q1 SN65HVDA540-5-Q1 SN65HVDA541-5-Q1 SN65HVDA542-5-Q1 13 SN65HVDA540-Q1, SN65HVDA541-Q1, SN65HVDA542-Q1 SN65HVDA540-5-Q1, SN65HVDA541-5-Q1, SN65HVDA542-5-Q1 SLLS804B – MARCH 2009 – REVISED SEPTEMBER 2010 www.ti.com PARAMETER MEASUREMENT INFORMATION Figure 5. Driver Voltage, Current, and Test Definition Figure 6. Driver VOD Test Circuit A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω. B. CL includes instrumentation and fixture capacitance within ±20%. C. For SN65HVDA54x-5 device versions, VIO = VCC. Figure 7. Driver Test Circuit and Voltage Waveforms Figure 8. Receiver Voltage and Current Definitions 14 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): SN65HVDA540-Q1 SN65HVDA541-Q1 SN65HVDA540-5-Q1 SN65HVDA541-5-Q1 SN65HVDA542-5-Q1 SN65HVDA540-Q1, SN65HVDA541-Q1, SN65HVDA542-Q1 SN65HVDA540-5-Q1, SN65HVDA541-5-Q1, SN65HVDA542-5-Q1 www.ti.com SLLS804B – MARCH 2009 – REVISED SEPTEMBER 2010 PARAMETER MEASUREMENT INFORMATION (continued) A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω. B. CL includes instrumentation and fixture capacitance within ±20%. C. C. For SN65HVDA54x-5 device versions VIO = VCC. Figure 9. Receiver Test Circuit and Voltage Waveforms Table 5. Differential Input Voltage Threshold Test INPUT VCANH OUTPUT VCANL |VID| R –11.1 V –12 V 900 mV L 12 V 11.1 V 900 mV L –6 V –12 V 6V L 12 V 6V 6V L –11.5 V –12 V 500 mV H 12 V 11.5 V 500 mV H –12 V –6 V 6V H 6V 12 V 6V H Open Open X H VOL VOH A. CL = 100 pF includes instrumentation and fixture capacitance within ±20%. B. All VI input pulses are from 0 V to VIO and supplied by a generator having the following characteristics: tr or tf ≤ 6 ns. Pulse Repetition Rate (PRR) = 25 kHz, 50% duty cycle. C. C. For SN65HVDA54x-5 device versions VIO = VCC. Figure 10. tEN Test Circuit and Waveforms Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65HVDA540-Q1 SN65HVDA541-Q1 SN65HVDA540-5-Q1 SN65HVDA541-5-Q1 SN65HVDA542-5-Q1 15 SN65HVDA540-Q1, SN65HVDA541-Q1, SN65HVDA542-Q1 SN65HVDA540-5-Q1, SN65HVDA541-5-Q1, SN65HVDA542-5-Q1 SLLS804B – MARCH 2009 – REVISED SEPTEMBER 2010 A. www.ti.com All VI input pulses are from 0 V to VIO and supplied by a generator having the following characteristics: tr or tf ≤ 6 ns. Pulse Repetition Rate (PRR) = 125 kHz, 50% duty cycle. Figure 11. Common-Mode Output Voltage Test and Waveforms A. CL = 100 pF includes instrumentation and fixture capacitance within ±20%. B. All VI input pulses are from 0 V to VIO and supplied by a generator having the following characteristics: tr or tf ≤ 6 ns. Pulse Repetition Rate (PRR) = 125 kHz, 50% duty cycle. C. For SN65HVDA54x-5 device versions, VIO = VCC. Figure 12. tPROP(LOOP) Test Circuit and Waveform A. CL = 100 pF includes instrumentation and fixture capacitance within ±20%. B. All VI input pulses are from 0 V to VIO and supplied by a generator having the following characteristics: tr or tf ≤ 6 ns. Pulse Repetition Rate (PRR) = 500 Hz, 50% duty cycle. C. For SN65HVDA54x-5 device versions, VIO = VCC. Figure 13. TXD Dominant Time Out Test Circuit and Waveforms 16 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): SN65HVDA540-Q1 SN65HVDA541-Q1 SN65HVDA540-5-Q1 SN65HVDA541-5-Q1 SN65HVDA542-5-Q1 SN65HVDA540-Q1, SN65HVDA541-Q1, SN65HVDA542-Q1 SN65HVDA540-5-Q1, SN65HVDA541-5-Q1, SN65HVDA542-5-Q1 www.ti.com A. SLLS804B – MARCH 2009 – REVISED SEPTEMBER 2010 A. For SN65HVDA54x-5 device versions VIO = VCC. Figure 14. Driver Short-Circuit Current Test and Waveforms A. All VI input pulses are from 0 V to VIO and supplied by a generator having the following characteristics: tr/tf ≤ 6 ns, Pulse Repetition Rate (PRR) = 250 kHz, 50% duty cycle. Figure 15. Driver Output Symmetry Test Circuit Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65HVDA540-Q1 SN65HVDA541-Q1 SN65HVDA540-5-Q1 SN65HVDA541-5-Q1 SN65HVDA542-5-Q1 17 SN65HVDA540-Q1, SN65HVDA541-Q1, SN65HVDA542-Q1 SN65HVDA540-5-Q1, SN65HVDA541-5-Q1, SN65HVDA542-5-Q1 SLLS804B – MARCH 2009 – REVISED SEPTEMBER 2010 www.ti.com APPLICATION INFORMATION VBATTERY VOUT 3.3-V Voltage Regulator VIN VIO (e.g. TPSxxxx) VIO VCORE 5 Port x STB VCORE (e.g. TMS 470) RXD Port y EN 5-V Voltage Regulator TXD CANH 8 SN65HVDA540 or SN65HVDA541 MCU VIN 7 RXD TXD CAN Transceiver 4 1 3 6 2 VCC CANL GND (e.g. TPSxxxx) VOUT Figure 16. Typical Application Using 3.3-V I/O Voltage Level and Low-Power Mode (5-V VCC Not Needed in Low-Power Mode) VIGNITION VOUT VIN 3.3-V Voltage Regulator (e.g. TPSxxxx) VIO VIO VCORE 5 Port x S 7 CANH 8 VCORE MCU SN65HVDA542 (e.g. TMS 470) CAN Transceiver RXD VIN 5-V Voltage Regulator TXD RXD TXD 4 1 3 VCC 6 2 CANL GND (e.g. TPSxxxx) VOUT Figure 17. Typical Application Using 3.3-V I/O Voltage Level and No Low-Power Mode 18 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): SN65HVDA540-Q1 SN65HVDA541-Q1 SN65HVDA540-5-Q1 SN65HVDA541-5-Q1 SN65HVDA542-5-Q1 SN65HVDA540-Q1, SN65HVDA541-Q1, SN65HVDA542-Q1 SN65HVDA540-5-Q1, SN65HVDA541-5-Q1, SN65HVDA542-5-Q1 www.ti.com SLLS804B – MARCH 2009 – REVISED SEPTEMBER 2010 Figure 18. Typical Application Using 5-V MCU and Low-Power Mode Figure 19. Typical Application Using 5-V MCU and No Low-Power Mode Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65HVDA540-Q1 SN65HVDA541-Q1 SN65HVDA540-5-Q1 SN65HVDA541-5-Q1 SN65HVDA542-5-Q1 19 PACKAGE OPTION ADDENDUM www.ti.com 5-Sep-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) HVDA5405QDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM HVDA540QDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM HVDA540QDSJRQ1 PREVIEW VSON DSJ 12 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR HVDA5415QDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM HVDA541QDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM HVDA541QDSJRQ1 PREVIEW VSON DSJ 12 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR HVDA5425QDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM HVDA542QDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 5-Sep-2011 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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OTHER QUALIFIED VERSIONS OF SN65HVDA540-Q1 : • Catalog: SN65HVDA540 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant HVDA5405QDRQ1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 HVDA5405QDRQ1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 HVDA540QDRQ1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 HVDA540QDRQ1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 HVDA5415QDRQ1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 HVDA5415QDRQ1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 HVDA541QDRQ1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 HVDA541QDRQ1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 HVDA5425QDRQ1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 HVDA5425QDRQ1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 HVDA542QDRQ1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 HVDA542QDRQ1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) HVDA5405QDRQ1 SOIC D 8 2500 367.0 367.0 35.0 HVDA5405QDRQ1 SOIC D 8 2500 367.0 367.0 35.0 HVDA540QDRQ1 SOIC D 8 2500 367.0 367.0 35.0 HVDA540QDRQ1 SOIC D 8 2500 367.0 367.0 35.0 HVDA5415QDRQ1 SOIC D 8 2500 367.0 367.0 35.0 HVDA5415QDRQ1 SOIC D 8 2500 367.0 367.0 35.0 HVDA541QDRQ1 SOIC D 8 2500 367.0 367.0 35.0 HVDA541QDRQ1 SOIC D 8 2500 367.0 367.0 35.0 HVDA5425QDRQ1 SOIC D 8 2500 367.0 367.0 35.0 HVDA5425QDRQ1 SOIC D 8 2500 367.0 367.0 35.0 HVDA542QDRQ1 SOIC D 8 2500 367.0 367.0 35.0 HVDA542QDRQ1 SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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