TPIC1505 QUAD AND HEX POWER DMOS ARRAY SLIS058 – JUNE 1996 D D D D Low rDS(on): 0.25 Ω Typ (Full H-Bridge) 0.35 Ω Typ (Triple Half H-Bridge) Pulsed Current: 6 A Per Channel (Full H-Bridge) 4 A Per Channel (Triple Half H-Bridge) Matched Sense Transistor for Class A-B Linear Operation Fast Commutation Speed DW PACKAGE (TOP VIEW) OUTPUT1 GATE2C GATE1B GATE3B GND OUTPUT3 SOURCE OUTPUT5 GND GATE4B GATE2B GATE5B description The TPIC1505 is a monolithic power array that consists of ten electrically isolated N-channel enhancement-mode power DMOS transistors, four of which are configured as a full H-bridge and six as a triple half H-bridge. The lower stage of the full H-bridge features an integrated sense FET to allow biasing of the bridge in class A-B operation. 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 GATE3A GATE1A GATE4A VDD1 VDD3 OUTPUT4 VDD3 GATE5A VDD2 GATE2A SENSE OUTPUT2 The TPIC1505 is offered in a 24-pin wide-body surface-mount (DW) package and is characterized for operation over the case temperature range of – 40°C to 125°C. schematic VDD1 VDD2 21 16 Q2A Q1A 23 GATE1A 15 GATE2A 1 OUTPUT1 D1 D2 Q1B 3 GATE1B 13 OUTPUT2 Q2B 11 GATE2B Q4A 22 GATE4A Q3A 24 GATE3A 6 OUTPUT3 D3 Q3B 4 GATE3B 19 OUTPUT4 Q4B 10 GATE4B Q5A 17 GATE5A 8 OUTPUT5 Q5B 12 GATE5B 14 SENSE 2 VDD3 18, 20 7 SOURCE Q2C GATE2C 6V 5, 9 GND NOTES: A. Pins 5 and 9 must be externally connected. B. Pins 18 and 20 must be externally connected. C. No output may be taken greater than 0.5 V below GND. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1996, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TPIC1505 QUAD AND HEX POWER DMOS ARRAY SLIS058 – JUNE 1996 absolute maximum ratings, TC = 25°C (unless otherwise noted)† Supply-to-GND voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 V Source-to-GND voltage (Q3A, Q4A, Q5A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 V Output-to-GND voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 V Sense-to-GND voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 V Gate-to-source voltage range, VGS (Q1A, Q1B, Q2A, Q2B, Q3A, Q3B, Q4A, Q4B, Q5A, Q5B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 20 V Gate-to-source voltage, VGS (Q2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.7 V to 6 V Continuous gate-to-source zener-diode current (Q2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 10 mA Pulsed gate-to-source zener-diode current (Q2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous drain current, each output (Q1A, Q1B, Q2A, Q2B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 A Continuous drain current, each output (Q3A, Q3B, Q4A, Q4B, Q5A, Q5B) . . . . . . . . . . . . . . . . . . . . . . . . . 1 A Continuous drain current (Q2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA Continuous source-to-drain diode current (Q1A, Q1B, Q2A, Q2B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 A Continuous source-to-drain diode current (Q3A, Q3B, Q4A, Q4B, Q5A, Q5B) . . . . . . . . . . . . . . . . . . . . . . 1 A Continuous source-to-drain diode current (Q2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA Pulsed drain current, each output, Imax (Q1A, Q1B, Q2A, Q2B) (see Note 1 and Figure 24) . . . . . . . . . 6 A Pulsed drain current, each output, Imax (Q3A, Q3B, Q4A, Q4B, Q5A, Q5B) (see Note 1 and Figure 25) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 A Pulsed drain current, Imax (Q2C) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Continuous total power dissipation, TC = 70°C (see Note 2 and Figures 24 and 25) . . . . . . . . . . . . . 2.86 W Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 150°C Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 125°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Pulse duration = 10 ms, duty cycle = 2% 2. Package is mounted in intimate contact with infinite heat sink. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPIC1505 QUAD AND HEX POWER DMOS ARRAY SLIS058 – JUNE 1996 electrical characteristics, Q1A, Q1B, Q2A, Q2B, TC = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS V(BR)DSX Drain-to-source breakdown voltage VGS(th) Gate-to-source threshold voltage VGS(th)match Gate-to-source threshold voltage matching V(BR) Reverse drain-to-GND breakdown voltage V(BR)GS V(BR)SG Gate-to-source breakdown voltage, Q2C Source-to-gate breakdown voltage, Q2C ID = 250 µA, ID = 1 mA, See Figure 5 VGS = 0 VDS = VGS, ID = 1 mA, VDS = VGS Drain-to-GND current = 250 µA (D1, D2) IGS = 100 µA ISG = 100 µA MIN TYP MAX 20 1.5 V 1.9 2.2 V 40 mV 20 V 6 V 0.5 V V(DS)on Drain-to-source on-state voltage ID = 1.5 A, See Notes 3 and 4 VF Forward on-state voltage, GND-to-VDD1, GND-to-VDD2 ID = 1.5 A (D1, D2), See Notes 3 and 4 VF(SD) Forward on-state voltage, source-to-drain IS = 1.5 A, VGS = 0, See Notes 3 and 4 and Figure 19 IDSS Zero gate voltage drain current Zero-gate-voltage VDS = 16 V,, VGS = 0 TC = 25°C TC = 125°C IGSSF Forward gate current, drain short-circuited to source VGS = 16 V, VDS = 0 Ilk lkg Leakage g current,, VDD1-to-GND,, VDD2-to-GND, gate shorted to source VDGND = 16 V TC = 25°C TC = 125°C 0.05 1 0.5 10 0.25 0.3 Static drain-to-source drain to source on-state on state resistance VGS = 10 V, ID = 1.5 A,, See Notes 3 and 4 and Figure 9 TC = 25°C rDS(on) DS( ) TC = 125°C 0.4 0.48 VDS = 14 V, See Notes 3 and 4 ID = 0.75 A, gfs Forward transconductance Ciss Short-circuit input capacitance, common source Coss Short-circuit output capacitance, common source Crss Short-circuit reverse transfer capacitance, common source UNIT VGS = 10 V, 0.38 0.45 1.5 1 V V 1.2 0.05 1 0.5 10 10 100 V µA nA µA Ω 0.7 1.1 S 100 VDS = 14 V, f = 1 MHz, VGS = 0, See Figure 17 75 pF 60 αs Sense-FET drain current ratio VDS = 6 V, ID(Q2C) = 40 µA 100 150 NOTES: 3. Technique should limit TJ – TC to 10°C maximum. 4. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts. 200 source-to-drain diode characteristics, Q1A, Q2A, TC = 25°C PARAMETER trr Reverse-recovery time QRR Total diode charge TEST CONDITIONS IS = 750 mA, VDS = 14 V, V See Figures 1 and 23 POST OFFICE BOX 655303 VGS = 0, di/dt = 100 A/µs A/µs, • DALLAS, TEXAS 75265 MIN TYP MAX UNIT 18 ns 15 nC 3 TPIC1505 QUAD AND HEX POWER DMOS ARRAY SLIS058 – JUNE 1996 resistive-load switching characteristics, Q1A, Q1B, Q2A, Q2B, TC = 25°C PARAMETER TEST CONDITIONS MIN TYP td(on) td(off) Turn-on delay time tr tf Rise time Qg Total gate charge Qgs(th) Threshold gate-to-source charge Qgd Gate-to-drain charge L(drain) L(source) Internal drain inductance 7 Internal source inductance 7 r(gate) Internal gate resistance MAX UNIT 11 Turn-off delay time VDD = 14 V,, tdis = 10 ns, RL = 18.7 Ω,, See Figure 3 16 ten = 10 ns,, ns 3 Fall time 4 VDS = 14 V, V See Figure 4 ID = 750 mA, A VGS = 10 V, V 2 2.5 0.35 0.4 0.5 0.6 nC nH Ω 10 electrical characteristics, Q3A, Q3B, Q4A, Q4B, Q5A, Q5B, TC = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS V(BR)DSX Drain-to-source breakdown voltage VGS(th) Gate-to-source threshold voltage VGS(th)match V(BR) Gate-to-source threshold voltage matching Reverse drain-to-GND breakdown voltage ID = 250 µA, ID = 1 mA, See Figure 6 VGS = 0 VDS = VGS, ID = 1 mA, VDS = VGS Drain-to-GND current = 250 µA (D3) MIN TYP MAX 20 1.5 V 1.9 2.2 V 40 mV 20 V V(DS)on Drain-to-source on-state voltage ID = 1 A, VGS = 10 V, See Notes 3 and 4 VF Forward on-state voltage, GND-to-VDD3 ID = 1 A (D3), ID = 1 A (D3), See Notes 3 and 4 1.5 VF(SD) Forward on-state voltage, source-to-drain IS = 1 A, VGS = 0, See Notes 3 and 4 and Figure 20 0.9 1.2 IDSS Zero gate voltage drain current Zero-gate-voltage VDS = 16 V,, VGS = 0 TC = 25°C TC = 125°C 0.05 1 0.5 10 IGSSF Forward gate current, drain short-circuited to source VGS = 16 V, VDS = 0 10 100 Ilk lkg Leakage g current,, VDD3-to-GND,, gate shorted to source VDGND = 16 V TC = 25°C TC = 125°C 0.05 1 0.5 10 TC = 25°C 0.35 0.48 Static drain-to-source drain to source on-state on state resistance VGS = 10 V, ID = 1 A, See Notes 3 and 4 and Figure 10 rDS( DS(on)) Forward transconductance Ciss Short-circuit input capacitance, common source Coss Short-circuit output capacitance, common source Crss Short-circuit reverse transfer capacitance, common source 0.35 TC = 125°C 0.55 0.4 0.72 V V V µA nA µA 0.75 S 70 VDS = 14 V, f = 1 MHz, VGS = 0, See Figure 18 85 50 NOTES: 3: Technique should limit TJ – TC to 10°C maximum. 4: These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts. 4 0.48 Ω VDS = 14 V, ID = 500 mA, See Notes 3 and 4 gfs UNIT POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 pF TPIC1505 QUAD AND HEX POWER DMOS ARRAY SLIS058 – JUNE 1996 source-to-drain diode characteristics, Q3A, Q4A, Q5A, TC = 25°C PARAMETER trr Reverse-recovery time QRR Total diode charge TEST CONDITIONS IS = 500 mA, VDS = 14 V, V See Figures 2 and 23 MIN VGS = 0, di/dt = 100 A/µs A/µs, TYP MAX UNIT 15 ns 10 nC resistive-load switching characteristics, Q3A, Q3B, Q4A, Q4B, Q5A, Q5B, TC = 25°C PARAMETER TEST CONDITIONS MIN TYP td(on) td(off) Turn-on delay time tr tf Rise time Qg Total gate charge Qgs(th) Threshold gate-to-source charge Qgd Gate-to-drain charge L(drain) L(source) Internal drain inductance 7 Internal source inductance 7 r(gate) Internal gate resistance MAX UNIT 11 Turn-off delay time RL = 32 Ω,, See Figure 3 VDD = 14 V,, tdis = 10 ns, 16 ten = 10 ns,, ns 3 Fall time 4 VDS = 14 V, V See Figure 4 ID = 500 mA, A VGS = 10 V, V 1.7 2.1 0.35 0.45 0.4 0.5 nC nH Ω 10 thermal resistance PARAMETER TEST CONDITIONS MIN TYP RθJA Junction-to-ambient thermal resistance See Notes 5 and 8 90 RθJB Junction-to-board thermal resistance See Notes 6 and 8 52 RθJP Junction-to-pin thermal resistance See Notes 7 and 8 28 NOTES: 5. 6. 7. 8. MAX UNIT °C/W Package is mounted on a FR4 printed-circuit board with no heat sink. Package is mounted on a 24 in2, 4-layer FR4 printed-circuit board. Package is mounted in intimate contact with infinite heat sink. All outputs have equal power. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TPIC1505 QUAD AND HEX POWER DMOS ARRAY SLIS058 – JUNE 1996 PARAMETER MEASUREMENT INFORMATION 1 I SD – Source-to-Drain Diode Current – A 0.5 Reverse di/dt = 100 A/µs VDS = 14 V VGS = 0 TJ = 25°C Q1A, Q2A 0 25% of IRM† – 0.5 –1 Shaded Area = QRR IRM† – 1.5 trr –2 – 2.5 –3 0 10 20 30 40 50 60 Time – ns 70 80 90 100 † IRM = maximum recovery current Figure 1. Reverse-Recovery-Current Waveform of Source-to-Drain Diodes 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPIC1505 QUAD AND HEX POWER DMOS ARRAY SLIS058 – JUNE 1996 PARAMETER MEASUREMENT INFORMATION 1.5 VDS = 14 V VGS = 0 TJ = 25°C Q3A, Q4A, Q5A I SD – Source-to-Drain Diode Current – A 1 Reverse di/dt = 100 A/µs 0.5 0 25% of IRM† – 0.5 Shaded Area = QRR –1 IRM† trr – 1.5 –2 – 2.5 0 10 20 30 40 50 60 Time – ns 70 80 90 100 † IRM = maximum recovery current Figure 2. Reverse-Recovery-Current Waveform of Source-to-Drain Diodes VDD = 14 V RL Pulse Generator ten VDS 10 V VGS VGS 0 DUT Rgen tdis 50 Ω 50 Ω td(off) td(on) CL 30 pF (see Note A) tr tf VDD VDS VDS(on) VOLTAGE WAVEFORMS TEST CIRCUIT NOTE A: CL includes probe and jig capacitance. Figure 3. Resistive-Switching Test Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TPIC1505 QUAD AND HEX POWER DMOS ARRAY SLIS058 – JUNE 1996 PARAMETER MEASUREMENT INFORMATION Current Regulator 12-V Battery 0.2 µF Qg Same Type as DUT 50 kΩ 10 V 0.3 µF Qgs(th) VDD = 14 V VDS VGS DUT IG = 100 µA 0 Qgd Gate Voltage Time IG CurrentSampling Resistor ID CurrentSampling Resistor VOLTAGE WAVEFORM TEST CIRCUIT Figure 4. Gate-Charge Test Circuit and Voltage Waveform TYPICAL CHARACTERISTICS 2.5 VDS = VGS Q1A, Q1B, Q2A, Q2B 2 ID = 10 mA 1.5 ID = 1 mA ID = 100 µA 1 0.5 0 – 40 – 20 0 20 40 60 80 100 120 140 160 GATE-TO-SOURCE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE VGS(th) – Gate-to-Source Threshold Voltage – V VGS(th) – Gate-to-Source Threshold Voltage – V GATE-TO-SOURCE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 2.5 ID = 10 mA 2 1.5 ID = 100 µA ID = 1 mA 1 0.5 VDS = VGS Q3A, Q3B, Q4A, Q4B, Q5A, Q5B 0 – 40 – 20 TJ – Junction Temperature – °C 20 40 60 Figure 6 POST OFFICE BOX 655303 80 100 120 140 160 TJ – Junction Temperature – °C Figure 5 8 0 • DALLAS, TEXAS 75265 TPIC1505 QUAD AND HEX POWER DMOS ARRAY SLIS058 – JUNE 1996 TYPICAL CHARACTERISTICS STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE 0.45 0.35 0.3 VGS = 15 V 0.25 VGS = 12 V 0.2 0.15 ID = 1 A Q3A, Q3B, Q4A, Q4B, Q5A, Q5B 0.55 On-State Resistance – Ω r DS(on) – Static Drain-to-Source 0.6 VGS = 10 V On-State Resistance – Ω r DS(on) – Static Drain-to-Source 0.4 0.65 ID = 1.5 A Q1A, Q1B, Q2A, Q2B VGS = 10 V 0.5 0.45 0.4 VGS = 15 V 0.35 0.3 VGS = 12 V 0.25 0.2 0.1 – 40 – 20 0 20 40 60 0.15 – 40 – 20 80 100 120 140 160 TJ – Junction Temperature – °C 0 20 Figure 7 1 0.5 VGS = 10 V VGS = 15 V 0.1 VGS = 12 V 1 10 TJ = 25°C Q3A, Q3B, Q4A Q4B, Q5A, Q5B On-State Resistance – Ω r DS(on) – Static Drain-to-Source TJ = 25°C Q1A, Q1B, Q2A, Q2B On-State Resistance – Ω 80 100 120 140 160 STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE vs DRAIN CURRENT 1 r DS(on) – Static Drain-to-Source 60 Figure 8 STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE vs DRAIN CURRENT 0.1 0.01 40 TJ – Junction Temperature – °C 0.5 VGS = 10 V VGS = 12 V VGS = 15 V 0.1 0.01 ID – Drain Current – A Figure 9 0.1 1 ID – Drain Current – A 10 Figure 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TPIC1505 QUAD AND HEX POWER DMOS ARRAY SLIS058 – JUNE 1996 TYPICAL CHARACTERISTICS DRAIN CURRENT vs DRAIN-TO-SOURCE VOLTAGE DRAIN CURRENT vs DRAIN-TO-SOURCE VOLTAGE 6 4 ∆VGS = 1 V (unless otherwise noted) TJ = 25°C Q3A, Q3B, Q4A, Q4B, Q5A, Q5B VGS = 6 V 3.5 ∆VGS = 1 V (unless otherwise noted) TJ = 25°C Q1A, Q1B, Q2A, Q2B 4 3 I D – Drain Current – A I D – Drain Current – A 5 3 VGS = 4 V 2 2.5 VGS = 5 V 2 1.5 VGS = 4 V 1 1 VGS = 3 V VGS = 3 V 0.5 0 0 1 2 3 4 5 6 7 8 9 VDS – Drain-to-Source Voltage – V 0 10 1 2 3 Figure 11 7 8 9 10 40 gfs – Forward Transconductance – S Figure 14 • DALLAS, TEXAS 75265 0.75 0.745 0.74 gfs – Forward Transconductance – S Figure 13 POST OFFICE BOX 655303 0.735 0.73 0.725 0.715 1.19 1.184 1.178 1.172 1.166 1.16 1.154 0 1.148 0 1.142 10 1.136 10 0.71 20 0.705 20 30 Total Number of Units = 50 VDS = 14 V TJ = 25°C ID = 500 mA Q3A, Q3B, Q4A, Q4B, Q5A, Q5B 0.7 Percentage of Units – % Total Number of Units = 50 VDS =14 V TJ = 25°C ID = 750 mA Q1A, Q1B, Q2A, Q2B 1.13 Percentage of Units – % 6 DISTRIBUTION OF FORWARD TRANSCONDUCTANCE 40 10 5 Figure 12 DISTRIBUTION OF FORWARD TRANSCONDUCTANCE 30 4 VDS – Drain-to-Source Voltage – V 0.72 0 TPIC1505 QUAD AND HEX POWER DMOS ARRAY SLIS058 – JUNE 1996 TYPICAL CHARACTERISTICS DRAIN CURRENT vs GATE-TO-SOURCE VOLTAGE DRAIN CURRENT vs GATE-TO-SOURCE VOLTAGE 6 4 TJ = – 40°C TJ = – 40°C TJ = 25°C 5 3.5 3 I D – Drain Current – A I D – Drain Current – A TJ = 75°C TJ = 125°C 4 TJ = 25°C Q1A, Q1B, Q2A, Q2B TJ = 150°C 3 2 1 TJ = 75°C 2.5 TJ = 125°C 2 1.5 TJ = 150°C 1 Q3A, Q3B, Q4A, Q4B, Q5A, Q5B 0.5 0 0 0 1 2 3 4 5 6 7 8 0 1 2 VGS – Gate-to-Source Voltage – V Figure 15 6 7 8 9 CAPACITANCE vs DRAIN-TO-SOURCE VOLTAGE 240 220 VGS = 0 f = 1 MHz TJ = 25°C Q1A, Q1B, Q2A, Q2B 220 200 VGS = 0 f = 1 MHz TJ = 25°C Q3A, Q3B, Q4A, Q4B, Q5A, Q5B 200 180 180 C – Capacitance – pF C – Capacitance – pF 5 4 Figure 16 CAPACITANCE vs DRAIN-TO-SOURCE VOLTAGE 160 140 120 Ciss 100 Coss 80 Crss 60 3 VGS – Gate-to-Source Voltage – V 160 140 120 100 Coss 80 Ciss 60 Crss 40 40 20 0 2 4 6 8 10 12 14 16 VDS – Drain-to-Source Voltage – V 0 2 4 6 8 10 12 14 16 VDS – Drain-to-Source Voltage – V Figure 17 Figure 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TPIC1505 QUAD AND HEX POWER DMOS ARRAY SLIS058 – JUNE 1996 TYPICAL CHARACTERISTICS SOURCE-TO-DRAIN DIODE CURRENT vs SOURCE-TO-DRAIN VOLTAGE SOURCE-TO-DRAIN DIODE CURRENT vs SOURCE-TO-DRAIN VOLTAGE 10 10 I SD – Source-to-Drain Diode Current – A TJ = 150°C TJ = 25°C TJ = – 40°C 1 0.1 VGS = 0 Q3A, Q3B, Q4A, Q4B, Q5A, Q5B TJ = 150°C 1 TJ = 25°C TJ = – 40°C 0.1 0.1 10 1 VSD – Source-to-Drain Voltage – V 0.1 1 VSD – Source-to-Drain Voltage – V Figure 19 Figure 20 DRAIN-TO-SOURCE VOLTAGE AND GATE-TO-SOURCE VOLTAGE vs GATE CHARGE DRAIN-TO-SOURCE VOLTAGE AND GATE-TO-SOURCE VOLTAGE vs GATE CHARGE ID = 750 mA TJ = 25°C Q1A, Q1B, Q2A, Q2B See Figure 4 10 10 VDD = 10 V 8 6 6 VDD = 12 V 4 4 VDD = 14 V 2 VDD = 12 V 0 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VDS – Drain-to-Source Voltage – V 12 2 14 14 VGS – Gate-to-Source Voltage – V VDS – Drain-to-Source Voltage – V VDD = 10 V 12 8 16 16 16 16 14 14 VDD = 12 V VDD = 14 V 12 12 10 10 ID = 500 mA TJ = 25°C Q3A, Q3B, Q4A, Q4B, Q5A, Q5B See Figure 4 8 6 VDD = 10 V 4 2 0.25 0.5 0.75 1 1.25 1.5 1.75 Qg – Gate Charge – nC Figure 21 Figure 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 6 2 0 0 8 4 VDD = 12 V VDD = 14 V Qg – Gate Charge – nC 12 10 2 0 2.25 2.5 VGS – Gate-to-Source Voltage – V I SD – Source-to-Drain Diode Current – A VGS = 0 Q1A, Q1B, Q2A, Q2B TPIC1505 QUAD AND HEX POWER DMOS ARRAY SLIS058 – JUNE 1996 TYPICAL CHARACTERISTICS REVERSE RECOVERY TIME vs REVERSE di/dt 40 TJ = 25°C See Figures 1 and 2 trr – Reverse Recovery Time – ns 35 30 25 IS = 750 mA Q1A, Q2A 20 IS = 500 mA Q3A, Q4A, Q5A 15 10 5 0 0 20 40 60 80 100 120 140 160 180 200 Reverse di/dt – A/µs Figure 23 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 TPIC1505 QUAD AND HEX POWER DMOS ARRAY SLIS058 – JUNE 1996 THERMAL INFORMATION MAXIMUM DRAIN CURRENT vs DRAIN-TO-SOURCE VOLTAGE I D – Maximum Drain Current – A 10 TC = 25°C Q1A, Q1B, Q2A, Q2B 1 µs† 0.5 ms† 1ms† 10 ms† 1 θJC§ ÁÁ ÁÁ θJA‡ DC Conditions 0.1 0.1 1 10 100 VDS – Drain-to-Source Voltage – V Figure 24 MAXIMUM DRAIN CURRENT vs DRAIN-TO-SOURCE VOLTAGE I D – Maximum Drain Current – A 10 TC = 25°C Q3A, Q3B, Q4A, Q4B, Q5A, Q5B 1 µs† 0.5 ms† 1 ms† 10 ms† 1 θJC§ ÁÁ ÁÁ θJA‡ DC Conditions 0.1 0.1 1 10 VDS – Drain-to-Source Voltage – V Figure 25 † Less than 10% duty cycle ‡ Device is mounted on a 24 in2, 4 layer FR4 printed-circuit board. § Device is mounted in intimate contact with infinite heat sink. 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 100 TPIC1505 QUAD AND HEX POWER DMOS ARRAY SLIS058 – JUNE 1996 THERMAL INFORMATION DW PACKAGE† JUNCTION-TO-BOARD THERMAL RESISTANCE vs PULSE DURATION 100 DC Conditions RθJB – Junction-to-Board Thermal Resistance – °C/W d = 0.5 d = 0.2 10 d = 0.1 d = 0.05 d = 0.02 d = 0.01 1 Single Pulse tc tw ID 0 0.1 0.0001 0.001 0.01 0.1 1 10 100 tw – Pulse Duration – s † Device is mounted on 24 in2, 4-layer FR4 printed circuit board with no heat sink. NOTE A: ZθB(t) = r(t) RθJB tw = pulse duration tc = cycle time d = duty cycle = tw/tc Figure 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1998, Texas Instruments Incorporated