TI TPS1120YD

TPS1120, TPS1120Y
DUAL P-CHANNEL ENHANCEMENT-MODE MOSFETS
SLVS080A – MARCH 1994 – REVISED AUGUST 1995
D
D
D
D
D
D
Low rDS(on) . . . 0.18 Ω at VGS = – 10 V
3-V Compatible
Requires No External VCC
TTL and CMOS Compatible Inputs
VGS(th) = – 1.5 V Max
ESD Protection Up to 2 kV per
MIL-STD-883C, Method 3015
D PACKAGE
(TOP VIEW)
1SOURCE
1GATE
2SOURCE
2GATE
1
8
2
7
3
6
4
5
1DRAIN
1DRAIN
2DRAIN
2DRAIN
description
The TPS1120 incorporates two independent
p-channel enhancement-mode MOSFETs that
have been optimized, by means of the Texas
Instruments LinBiCMOS process, for 3-V or 5-V
power distribution in battery-powered systems. With a maximum VGS(th) of – 1.5 V and an IDSS of only 0.5 µA,
the TPS1120 is the ideal high-side switch for low-voltage portable battery-management systems, where
maximizing battery life is a primary concern. Because portable equipment is potentially subject to electrostatic
discharge (ESD), the MOSFETs have built-in circuitry for 2-kV ESD protection. End equipment for the TPS1120
includes notebook computers, personal digital assistants (PDAs), cellular telephones, bar-code scanners, and
PCMCIA cards. For existing designs, the TPS1120D has a pinout common with other p-channel MOSFETs in
small-outline integrated circuit SOIC packages.
The TPS1120 is characterized for an operating junction temperature range, TJ, from – 40°C to 150°C.
AVAILABLE OPTIONS
PACKAGED DEVICES†
TJ
SMALL OUTLINE
(D)
CHIP FORM
(Y)
– 40°C to 150°C
TPS1120D
TPS1120Y
† The D package is available taped and reeled. Add an R suffix to device
type (e.g., TPS1120DR). The chip form is tested at 25°C.
Caution. This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic
fields. These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to
MIL-STD-883C, Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than
maximum-rated voltages to these high-impedance circuits.
LinBiCMS is a trademark of Texas Instruments Incorporated.
Copyright  1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
TPS1120, TPS1120Y
DUAL P-CHANNEL ENHANCEMENT-MODE MOSFETS
SLVS080A – MARCH 1994 – REVISED AUGUST 1995
schematic
1SOURCE
2SOURCE
ESDProtection
Circuitry
ESDProtection
Circuitry
1GATE
2GATE
1DRAIN†
2DRAIN†
† For all applications, both drain pins for each device should be connected.
TPS1120Y chip information
This chip, when properly assembled, displays characteristics similar to the TPS1120C. Thermal compression
or ultrasonic bonding may be used on the doped aluminum bonding pads. The chip may be mounted with
conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
(4)
1SOURCE
1GATE
2SOURCE
(5)
(3)
(6)
2GATE
(1)
(8)
(2)
(7)
(3)
TPS1120Y
(4)
(6)
(5)
1DRAIN
1DRAIN
2DRAIN
2DRAIN
57
CHIP THICKNESS: 15 MILS TYPICAL
BONDING PADS: 4 × 4 MILS MINIMUM
TJmax = 150°C
(8)
(1)
TOLERANCES ARE ± 10%
(7)
(2)
ALL DIMENSIONS ARE IN MILS
64
2
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TPS1120, TPS1120Y
DUAL P-CHANNEL ENHANCEMENT-MODE MOSFETS
SLVS080A – MARCH 1994 – REVISED AUGUST 1995
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
UNIT
Drain-to-source voltage, VDS
–15
Gate-to-source voltage, VGS
2 or –15
VGS = – 2
2.7
7V
VGS = – 3 V
TA = 25°C
TA = 125°C
5V
VGS = – 4
4.5
TA = 25°C
TA = 125°C
± 0.74
VGS = – 10 V
TA = 25°C
TA = 125°C
± 1.17
Pulse drain current, ID
TA = 25°C
TA = 25°C
Continuous source current (diode conduction), IS
Continuous total power dissipation
V
± 0.39
TA = 25°C
TA = 125°C
Continuous drain current
current, each device (TJ = 150°C)
150°C), ID
V
± 0.21
± 0.5
± 0.25
A
± 0.34
± 0.53
±7
A
–1
A
See Dissipation Rating Table
Storage temperature range, Tstg
– 55 to 150
°C
Operating junction temperature range, TJ
– 40 to 150
°C
Operating free-air temperature range, TA
– 40 to 125
°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260
°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR‡
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
TA = 125°C
POWER RATING
D
840 mW
6.71 mW/°C
538 mW
437 mW
169 mW
‡ Maximum values are calculated using a derating factor based on RθJA = 149°C/W for the package. These devices are
mounted on an FR4 board with no special thermal considerations.
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3
TPS1120, TPS1120Y
DUAL P-CHANNEL ENHANCEMENT-MODE MOSFETS
SLVS080A – MARCH 1994 – REVISED AUGUST 1995
electrical characteristics at TJ = 25°C (unless otherwise noted)
static
PARAMETER
TEST CONDITIONS
VGS(th)
VSD
Gate-to-source threshold voltage
Source-to-drain voltage (diode forward voltage)†
VDS = VGS,
IS = – 1 A,
ID = – 250 µA
VGS = 0 V
IGSS
Reverse gate current, drain short circuited to source
VDS = 0 V,
IDSS
Zero gate voltage drain current
Zero-gate-voltage
VDS = – 12 V,,
VGS = 0 V
VGS = – 12 V
TJ = 25°C
VGS = – 10 V
VGS = – 4.5 V
Static drain-to-source
drain to source on-state
on state resistance†
rDS(
DS(on))
Forward transconductance†
gfs
† Pulse test: pulse width ≤ 300 µs, duty cycle ≤ 2%
TPS1120
TYP
MAX
–1
– 1.25
– 1.50
V
± 100
nA
– 0.9
V
– 0.5
TJ = 125°C
ID = – 1.5 A
180
ID = – 0.5 A
291
400
476
700
606
850
VGS = – 3 V
VGS = – 2.7 V
ID = – 0
0.2
2A
VDS = – 10 V,
ID = – 2 A
UNIT
MIN
– 10
2.5
µA
mΩ
S
static
PARAMETER
VGS(th)
VSD
TEST CONDITIONS
Gate-to-source threshold voltage
Source-to-drain voltage (diode forward voltage)†
Static drain-to-source
drain to source on-state
on state resistance†
rDS(
DS(on))
gfs
Forward transconductance†
† Pulse test: pulse width ≤ 300 µs, duty cycle ≤ 2%
VDS = VGS,
IS = – 1 A,
ID = – 250 µA
VGS = 0 V
VGS = – 10 V
VGS = – 4.5 V
ID = – 1.5 A
ID = – 0.5 A
VGS = – 3 V
VGS = – 2.7 V
ID = – 0
0.2
2A
VDS = – 10 V,
ID = – 2 A
TPS1120Y
MIN
TYP
MAX
UNIT
– 1.25
V
– 0.9
V
180
291
mΩ
476
606
2.5
S
dynamic
PARAMETER
TPS1120, TPS1120Y
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Qg
Total gate charge
Qgs
Gate-to-source charge
Qgd
Gate-to-drain charge
1.4
td(on)
td(off)
Turn-on delay time
4.5
ns
13
ns
tr
tf
Rise time
trr(SD)
Source-to-drain reverse recovery time
4
5.45
VDS = – 10 V,
Turn-off delay time
VDD = – 10 V,,
RG = 6 Ω,
VGS = – 10 V,
RL = 10 Ω,,
See Figures 1 and 2
Fall time
ID = – 1 A
ID = – 1 A,,
0.87
10
2
IF = 5.3 A,
POST OFFICE BOX 655303
di/dt = 100 A/µs
• DALLAS, TEXAS 75265
nC
16
ns
TPS1120, TPS1120Y
DUAL P-CHANNEL ENHANCEMENT-MODE MOSFETS
SLVS080A – MARCH 1994 – REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
VGS
RL
VDS
VGS
VDD
RG
0V
90%
–
+
10%
DUT
– 10 V
VDS
td(on)
td(off)
tr
Figure 1. Switching-Time Test Circuit
POST OFFICE BOX 655303
tf
Figure 2. Switching-Time Waveforms
• DALLAS, TEXAS 75265
5
TPS1120, TPS1120Y
DUAL P-CHANNEL ENHANCEMENT-MODE MOSFETS
SLVS080A – MARCH 1994 – REVISED AUGUST 1995
TYPICAL CHARACTERISTICS†
Table of Graphs
FIGURE
Drain current
vs Drain-to-source voltage
3
Drain current
vs Gate-to-source voltage
4
Static drain-to-source on-state resistance
vs Drain current
5
Capacitance
vs Drain-to-source voltage
6
Static drain-to-source on-state resistance (normalized)
vs Junction temperature
7
Source-to-drain diode current
vs Source-to-drain voltage
8
Static drain-to-source on-state resistance
vs Gate-to-source voltage
9
Gate-to-source threshold voltage
vs Junction temperature
10
Gate-to-source voltage
vs Gate charge
11
DRAIN CURRENT
vs
GATE-TO-SOURCE VOLTAGE
DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
–7
–7
VGS = – 8 V
VGS = – 7 V
–6
VDS = –10 V
–6
ÁÁ
ÁÁ
TJ = 25°C
VGS = – 6 V
–5
VGS = – 5 V
–4
VGS = – 3 V
–3
–2
VGS = – 2 V
–1
ÁÁ
ÁÁ
TJ = 25°C
0
0
I D – Drain Current – A
I D – Drain Current – A
VGS = – 4 V
– 1 – 2 – 3 – 4 – 5 – 6 – 7 – 8 – 9 – 10
VDS – Drain-to-Source Voltage – V
TJ = – 40°C
–4
–3
–2
–1
0
0
–1
–2
–3
Figure 4
† All characteristics data applies for each independent MOSFET incorporated on the TPS1120.
POST OFFICE BOX 655303
–4
–5
–6
VGS – Gate-to-Source Voltage – V
Figure 3
6
TJ = 150°C
–5
• DALLAS, TEXAS 75265
–7
TPS1120, TPS1120Y
DUAL P-CHANNEL ENHANCEMENT-MODE MOSFETS
SLVS080A – MARCH 1994 – REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
DRAIN CURRENT
CAPACITANCE
vs
DRAIN-TO-SOURCE VOLTAGE
350
0.7
VGS = 0
f = 1 MHz
TJ = 25°C
Ciss†
TJ = 25°C
300
VGS = – 2.7 V
0.5
C – Capacitance – pF
On-State Resistance – Ω
r DS(on) – Static Drain-to-Source
0.6
VGS = – 3 V
0.4
VGS = – 4.5 V
0.3
VGS = –10 V
0.2
200
Coss
150
Crss‡
100
0.1
50
0
– 0.1
–1
0
– 10
ID – Drain Current – A
0 – 1 – 2 – 3 – 4 – 5 – 6 – 7 – 8 – 9 –10 –11 –12
Figure 6
STATIC DRAIN-TO-SOURCE
ON-STATE RESISTANCE (NORMALIZED)
vs
JUNCTION TEMPERATURE
ds
) Cgd
–10
Pulse Test
I SD – Source-to-Drain Diode Current – A
VGS = – 10 V
ID = – 1A
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
– 50
≈ C
gd
SOURCE-TO-DRAIN DIODE CURRENT
vs
SOURCE-TO-DRAIN VOLTAGE
1.5
1.4
VDS – Drain-to-Source Voltage – V
+ Cgs ) Cgd, Cds(shorted)
iss
C gs C
gd
‡ C
rss + C gd, C oss + C ds ) C ) C
gs
† C
Figure 5
r DS(on) – Static Drain-to-Source
On-State Resistance (Normalized)
250
TJ = 150°C
–1
TJ = 25°C
TJ = – 40°C
– 0.1
0
50
100
150
0
– 0.2 – 0.4 – 0.6 – 0.8 – 1 –1.2 –1.4 –1.6 –1.8
TJ – Junction Temperature – °C
VSD – Source-to-Drain Voltage – V
Figure 7
Figure 8
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• DALLAS, TEXAS 75265
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TPS1120, TPS1120Y
DUAL P-CHANNEL ENHANCEMENT-MODE MOSFETS
SLVS080A – MARCH 1994 – REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
GATE-TO-SOURCE VOLTAGE
GATE-TO-SOURCE THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
VGS(th) – Gate-to-Source Threshold Voltage – V
r DS(on) – Static Drain-to-Source On-State
Resistance – Ω
0.7
ID = – 1 A
TJ = 25°C
0.6
0.5
0.4
0.3
0.2
0.1
0
–1
–3
–5
–7
–9
– 13
– 11
– 15
– 1.5
ID = – 250 µA
– 1.4
– 1.3
– 1.2
– 1.1
ÁÁ
ÁÁ
ÁÁ
–1
– 0.9
– 50
0
50
100
TJ – Junction Temperature – °C
VGS – Gate-to-Source Voltage – V
Figure 9
Figure 10
GATE-TO-SOURCE VOLTAGE
vs
GATE CHARGE
VGS – Gate-to-Source Voltage – V
– 10
VDS = – 10 V
ID = – 1 A
TJ = 25°C
–8
–6
–4
–2
0
0
1
2
3
4
5
Qg – Gate Charge – nC
Figure 11
8
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• DALLAS, TEXAS 75265
6
150
TPS1120, TPS1120Y
DUAL P-CHANNEL ENHANCEMENT-MODE MOSFETS
SLVS080A – MARCH 1994 – REVISED AUGUST 1995
THERMAL INFORMATION
DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
– 10
Single Pulse
See Note A
0.001 s
I D – Drain Current – A
0.01 s
–1
0.1 s
1s
– 0.1
10 s
DC
TJ = 150°C
TA = 25°C
– 0.001
– 0.1
–1
– 10
– 100
VDS – Drain-to-Source Voltage – V
NOTE A: FR4-board-mounted only
Figure 12
TRANSIENT JUNCTION-TO-AMBIENT
THERMAL IMPEDANCE
vs
PULSE DURATION
100
ZθJA – Transient Junction-to-Ambient
Thermal Impedance – °C/W
Single Pulse
See Note A
10
1
0.1
0.001
0.01
0.1
1
10
tw – Pulse Duration – s
NOTE A: FR4-board-mounted only
Figure 13
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9
TPS1120, TPS1120Y
DUAL P-CHANNEL ENHANCEMENT-MODE MOSFETS
SLVS080A – MARCH 1994 – REVISED AUGUST 1995
THERMAL INFORMATION
The profile of the heat sinks used for thermal measurements is shown in Figure 14. Board type is FR4 with 1-oz copper
and 1-oz tin/lead (63/37) plate. Use of vias or through-holes to enhance thermal conduction was avoided.
Figure 15 shows a family of RθJA curves. The RθJA was obtained for various areas of heat sinks while subject to air
flow. Power remained fixed at 0.25 W per device or 0.50 W per package. This testing was done at 25°C.
As Figure 14 illustrates, there are two separated heat sinks for each package. Each heat sink is coupled to the lead
that is internally tied to a single MOSFET source and is half the total area, as shown in Figure 15. For example, if the
total area shown in Figure 15 is 4 cm2, each heat sink is 2 cm2.
1SOURCE
1GATE
1DRAIN
The Combined Area
of These Two Heat
Sinks Is 4 cm2
2DRAIN
2SOURCE
2GATE
≅ 2 cm
TPS1120D IC
HS: 4 cm2
8P SOIC Thermal Analysis
Rθ JA – Thermal Resistance, Junction-to-Ambient – °C/W
Figure 14. Profile of Heat Sinks
THERMAL RESISTANCE, JUNCTION-TO-AMBIENT
vs
AIRFLOW, 25°C
150
0 cm2
140
130
TJ = 25°C
P = 0.5 W
Heat Sink Areas
as Shown
0.5 cm2
120
1 cm2
110
100
90
80
70
2 cm2
60
8 cm2
4 cm2
50
0
50
100
150
Airflow, 25°C – ft /min
Figure 15
10
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• DALLAS, TEXAS 75265
200
250
300
TPS1120, TPS1120Y
DUAL P-CHANNEL ENHANCEMENT-MODE MOSFETS
SLVS080A – MARCH 1994 – REVISED AUGUST 1995
THERMAL INFORMATION
Figure 16 illustrates the thermally enhanced (SO) lead frame. Attaching the two MOSFET dies directly to the source
terminals allows maximum heat transfer into a power plane.
Lead 1 1SOURCE
1DRAIN
Lead 8
1DRAIN
Lead 7
2DRAIN
Lead 6
2DRAIN
Lead 5
Pad 1
MOSFET 1
Lead 2 1GATE
Pad 1
Lead 3 2SOURCE
MOSFET 2
Lead 4 2GATE
Figure 16. TPS1120 Dual MOSFET SO-8 Lead Frame
APPLICATION INFORMATION
3 V or 5 V
5V
Microcontroller
Driver
Microcontroller
Load
Figure 17. Notebook Load Management
POST OFFICE BOX 655303
Charge
Pump
–4 V
GaAs FET
Amplifier
Figure 18. Cellular Phone Output Drive
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11
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