OKI MSM6669

E2B0025-27-Y2
¡ Semiconductor
MSM6669
¡ Semiconductor
This version: Nov.
1997
MSM6669
Previous version: Mar. 1996
80-DOT LCD SEGMENT DRIVER
GENERAL DESCRIPTION
The MSM6669 is a dot matrix LCD segment driver which is fabricated using CMOS low power
silicon gate technology.
This LSI consists of 80-bit latches I and II, 80-bit level shifter, and 80-bit 4-level driver.
It latches the 4-bit parallel display data from the LCD controller LSI or microcontroller, and then
outputs the signal for the LCD driving.
FEATURES
• Logic supply voltage
: 2.7V to 5.5V
• LCD driving voltage
: 14V to 28V
• Applicable LCD duty
: 1/64 to 1/256
• Bias voltage can be supplied externally
• LCD output
: 80
• 4-bit parallel data processing has improved the transfer speed to 1/4 that of the conventional
serial transfer, thereby achieving low power consumption
• Applicable common driver : MSM6778 (120 outputs)
• Structure:
TCP mounting with 35mm wide film (Product name: MSM6669AV-Z-05)
Sn-plated
Outer lead pitch
: 220mm
User area
: 7.5mm
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MSM6669
BLOCK DIAGRAM
O1 O2
V1
V3
V4
VEE
DF
DISP OFF
O79 O80
VDD
80-BIT 4-LEVEL DRIVER
VEE
80-BIT LEVEL SHIFTER
VDD
80-BIT LATCH (II)
LOAD
D0
D1
D2
D3
VSS
VDD
80-BIT LATCH (I)
VDD
VSS
CP
EI
CONTROL
CIRCUIT
EO
SHL
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MSM6669
PIN CONFIGURATION (TOP VIEW)
Dummy
Dummy
Dummy
O80
O79
O78
O3
O2
O1
Dummy
Dummy
Dummy
V1
V3
V4
VEE
VSS
SHL
VDD
EO
DISP OFF
DF
LOAD
CP
D3
D2
D1
D0
EI
VDD
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MSM6669
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Condition
Rating
Unit
Supply Voltage (1)
VDD
Ta=25°C
–0.3 to +6.5
V
Supply Voltage (2)
VLCD
Ta=25°C, VDD – VEE*
0 to 30
V
VI
Ta=25°C
–0.3 to VDD + 0.3
V
TSTG
—
–30 to +85
°C
Input Voltage
Storage Temperature
* V1 > V3 > V4 > VEE, VDD ≥ V1 > V3 ≥ VDD –10V, VEE +10V ≥ V4 > VEE
RECOMMENDED OPERATING CONDITIONS
Symbol
Condition
Min.
Typ.
Max.
Unit
Supply Voltage (1)
Parameter
VDD
—
2.7
5.0
5.5
V
Supply Voltage (2)
VLCD
VDD–VEE*
14
—
28
V
Top
—
–20
—
75
°C
Operating Temperature
* V1 > V3 > V4 > VEE, VDD ≥ V1 > V3 ≥ VDD –7V, VEE +7V ≥ V4 > VEE
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¡ Semiconductor
MSM6669
ELECTRICAL CHARACTERISTICS
DC Characteristics
(VDD = 2.7 to 5.5V, Ta = –20 to +75°C)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
0.8 VDD
—
VDD
V
"H" Input Voltage
VIH
*1
—
"L" Input Voltage
VIL
*1
—
"H" Input Current
IIH
*1
"L" Input Current
IIL
*1
"H" Output Voltage
VOH
*2
"L" Output Voltage
VOL
On Resistance
Stand-by Current
Supply Current (1)
Supply Current (2)
Input Capacitance
RON
IDDSBY
IDD1
IV
CI
—
—
0.2 VDD
V
VIH = VDD
VSS
—
1
µA
VIL = 0V
—
—
–1
µA
IO = –0.2mA
VDD – 0.4
—
—
V
*2
IO = 0.2mA
—
—
0.4
V
*4
VDD – VEE = 25V
VDD = 2.7V
VN – VO = 0.25V
—
1.5
3.0
kΩ
*3
fCP = 6.0MHz, VDD = 3.0V
VDD – VEE = 25V
No load, fLOAD = 21.6kHz
—
—
0.3
mA
*5
—
—
1.5 (VDD)
1.0 (VEE)
mA
—
—
100
µA
—
5
—
pF
fCP = 6.0MHz, VDD = 3.0V
VDD – VEE = 25V
No load, fLOAD = 21.6kHz
fCP = 6.0MHz, VDD = 3.0V
VDD – VEE = 25V
No load, fLOAD = 21.6kHz
f = 1MHz
*6
*7
Applicable to LOAD, CP, D0 to D3, EI , DF, DISP OFF pins.
Applicable to EO pin.
VN = V1 to VEE, V4 = 14/16 (VDD – VEE), V3 = 2/16 (VDD – VEE), VDD = V1.
Applicable to O1 to O80 pins.
Display data 1010, fDF = 45Hz, current that flows from VDD to Vss when the display
data is not clocked in.
*6 Display data 1010, fDF = 45Hz, current (VDD) that flows from VDD to VSS and VEE, and
current (VEE) that flows from VDD to VEE when the display data is clocked in.
*7 Display data 1010, fDF = 45Hz, current that flows to each of the V1, V3 and V4 pins.
*1
*2
*3
*4
*5
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¡ Semiconductor
MSM6669
Switching Characteristics
(VDD = 2.7 to 5.5V, Ta = –20 to +75°C, CL = 15pF)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
—
—
6.5
MHz
Clock Frequency
fCP
Duty = 50%
Clock Pulse Width
tW1
—
56
—
—
ns
Rise/Fall Time
tr , tf
—
—
—
20
ns
Data Setup Time
tDSU
—
50
—
—
ns
Data Hold Time
tDHD
—
50
—
—
ns
Load Pulse Width
tW2
tLSU
—
—
70
Load Setup Time
80
—
—
—
—
ns
ns
Load → Clock Time
tLC
—
80
—
—
ns
"H", "L" Propagation
Delay Time
tPLH
tPHL
—
—
—
236
ns
EI Setup Time
tESU
—
50
—
—
ns
tW1
CP
0.8 VDD
tf
tW1
tr
0.8 VDD
0.8 VDD
0.2 VDD
0.2 VDD
tDSU
tW1
0.8 VDD
tDHD
0.8 VDD
0.2 VDD
D0 - D3
tLSU
0.8 VDD
LOAD
tLC
0.8 VDD
0.2 VDD
0.2 VDD
tr
tW2
tf
0.8 VDD
1
CP
2
18
0.2 VDD
19
20
tPHL
LOAD
tPLH
EO
0.2 VDD
tESU
EI
0.2 VDD
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¡ Semiconductor
MSM6669
FUNCTIONAL DESCRIPTION
Pin Functional Description
• EI, EO
These are enable signal input and output pins. When a cascade connection is required, set the
first MSM6669's EI pin at "L" level and connect the EO pin to the next MSM6669's EI pin. When
a single MSM6669 is used, EI should be set at "L" level.
• CP
This is a pin for clocking the display data in. Display data is stored into the latch (I) at the
falling edge of a clock pulse. A clock pulse through this pin is enabled when the enable F/
F is set, and disabled when it is not set.
• LOAD
This is an input pin to latch the display data of one line stored in the latch (I). At the falling
edge of a load pulse, the display data stored in the latch (I) is transferred to the latch (II). The
control circuit to save the power is reset and the display data on the next line can be stored.
• DF
Synchronous signal input pin for alternate signal for LCD driving.
• VDD, VSS
These are power supply pins of this IC. The VDD pin is generally set to 2.7 to 5.5V. VSS is a
grounding pin, which is generally set to 0V.
• O1 to O80
These are output pins of the 4-level driver of this IC, which correspond directly to the bits of
the 80-bit latch (II). One of the four levels V1, V3, V4, and VEE is selected and output by a
combination of the latch contents (display data) and a DF signal. See the truth table.
Connect the output pins to the liquid crystal panel on the segment side.
• DISP OFF
This is an input pin to control the output pins O1 to O80. During low signal input, signals on
the V1 level are output from the output pins O1 to O80 irrespective of display data. See the
truth table.
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¡ Semiconductor
MSM6669
• D0, D1, D2, D3
These are display data input pins. Display data is input in synchronization with a clock pulse.
Table 1 gives the relation between the display data, DF, liquid crystal drive output, and liquid
crystal display.
Table 1
Display data
DF
Liquid crystal drive output
Liquid crystal display
L
L
Non-select level
(V3)
OFF
H
L
Select level
(V1)
ON
L
H
Non-select level
(V4)
OFF
H
H
Select level
(VEE)
ON
• SHL
This is an input pin used to change the loading direction of display data.
Table 2 shows the correspondence between the bit positions of the 4-bit data (D0 to D3), its
loading direction, and driver outputs (O1 to O80).
Table 2
Direction of data loading
SHL
L
H
D0
→ O1
→
O5
O77
D1
→ O2
→
O6
O78
D2
→ O3
→
O7
O79
D3
→ O4
→
O8
O80
D0
→ O80
→
O76
O4
D1
→ O79
→
O75
O3
D2
→ O78
→
O74
O2
D3
→ O77
→
O73
O1
Last data
First data
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MSM6669
• V1, V3, V4, VEE
Bias supply voltage pins to drive the LCD. Bias voltages for the LCD driving are supplied
from an external source.
Truth Table
Latch Data
DISP OFF
Driver Output Level (O1 - O80)
L
L
H
V3
L
H
H
V1
H
L
H
V4
H
H
H
VEE
X
L
V1
DF
X
X: Don't care
NOTES ON USE
Note the following when turning power on and off:
The LCD drivers of this IC require a high voltage. For this reason, if a high voltage is applied to
the LCD drivers with the logic power supply floating, excess current flows. This may damage
the IC. Be sure to carry out the following power-on and power-off sequences:
When turning power on:
First VDD ON, next VEE, V4, V3, V1 ON. Or both ON at the same time.
When turning power off:
First VEE, V4, V3, V1 OFF, next VDD OFF. Or both OFF at the same time.
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