LP38852 www.ti.com SNVS482E – JANUARY 2007 – REVISED APRIL 2013 1.5A Fast-Response High-Accuracy Adjustable LDO Linear Regulator with Enable and Soft-Start Check for Samples: LP38852 FEATURES DESCRIPTION • • The LP38852-ADJ is a high current, fast response regulator which can maintain output voltage regulation with extremely low input to output voltage drop. Fabricated on a CMOS process, the device operates from two input voltages: VBIAS provides voltage to drive the gate of the N-MOS power transistor, while VIN is the input voltage which supplies power to the load. The use of an external bias rail allows the part to operate from ultra low VIN voltages. Unlike bipolar regulators, the CMOS architecture consumes extremely low quiescent current at any output load current. The use of an NMOS power transistor results in wide bandwidth, yet minimum external capacitance is required to maintain loop stability. 1 2 • • • • • • Adjustable VOUT Range of 0.80V to 1.8V Wide VBIAS Supply Operating Range of 3.0V to 5.5V Stable with 10µF Ceramic Capacitors Dropout Voltage of 130 mV (Typical) at 1.5A Load Current Precision Output Voltage across All Line and Load Conditions: – ±1.5% VADJ for TJ = 25°C – ±2.0% VADJ for 0°C ≤ TJ ≤ +125°C – ±3.0% VADJ for -40°C ≤ TJ ≤ +125°C Over-Temperature and Over-Current Protection Available in 8 Lead SO PowerPAD, 7 Lead TO220 and 7 Lead DDPAK Packages −40°C to +125°C Operating Junction Temperature Range The fast transient response of this device makes it suitable for use in powering DSP, Microcontroller Core voltages and Switch Mode Power Supply post regulators. The part is available in the TO-220 and DDPAK 7-pin packages. Dropout Voltage: 130 mV (typical) at 1.5A load current. APPLICATIONS • • • • ASIC Power Supplies In: – Desktops, Notebooks, and Graphics Cards, Servers – Gaming Set Top Boxes, Printers and Copiers Server Core and I/O Supplies DSP and FPGA Power Supplies SMPS Post-Regulator Low Ground Pin Current: 10 mA (typical) at 1.5A load current. Soft-Start: Programmable Soft-Start time. Precision ADJ Voltage: ±1.5% for TJ = 25°C, and ±2.0% for 0°C ≤ TJ ≤ +125°C, across all line and load conditions Typical Application Circuit LP38852-ADJ VIN IN VBIAS VOUT OUT CIN CFF 10 PF Ceramic BIAS R1 CBIAS VEN 1 PF SS COUT 10 PF Ceramic ADJ EN R2 GND CSS GND GND 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007–2013, Texas Instruments Incorporated LP38852 SNVS482E – JANUARY 2007 – REVISED APRIL 2013 www.ti.com Connection Diagrams Top View SS EN IN GND ADJ OUT BIAS Figure 1. DDPAK-7 Package See Package Number KTW0007B 1 2 3 4 5 6 7 LP38852T-ADJ 1 2 3 4 5 6 7 LP38852S-ADJ SS EN IN GND ADJ OUT BIAS Top View TAB IS GND TAB IS GND Figure 2. TO-220-7 Package See Package Number NDZ0007B Top View ADJ 1 8 N/C OUT 2 7 IN BIAS 3 6 EN GND 4 5 SS DAP Connect to GND Figure 3. SO PowerPAD-8 Package See Package Number DDA0008A Pin Descriptions TO-220-7 and DDPAK-7 Packages TO-220–7 Pin # DDPAK–7 Pin # SO PowerPAD-8 Pin # Pin Symbol Pin Description 1 1 5 SS Soft-Start capacitor connection. Used to slow the rise time of VOUT at turn-on. 2 2 6 EN Device Enable, High = On, Low = Off. 3 3 7 IN The unregulated voltage input 4 4 4 GND Ground 5 5 1 ADJ The feedback connection to set the output voltage 6 6 2 OUT The regulated output voltage 7 7 3 BIAS The supply for the internal control and reference circuitry. - - 8 N/C No internal connection TAB TAB - TAB The TAB is a thermal and electrical connection that is physically attached to the backside of the die, and used as a thermal heat-sink connection. See the Application Informationsection for details. - - DAP DAP The DAP is a thermal connection only that is physically attached to the backside of the die, and used as a thermal heat-sink connection. See the Application Information section for details. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 2 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LP38852 LP38852 www.ti.com SNVS482E – JANUARY 2007 – REVISED APRIL 2013 Absolute Maximum Ratings (1) (2) −65°C to +150°C Storage Temperature Range Lead Temperature Soldering, 5 seconds ESD Rating Human Body Model (3) Power Dissipation (4) 260°C ±2 kV Internally Limited VIN Supply Voltage (Survival) −0.3V to +6.0V VBIAS Supply Voltage (Survival) −0.3V to +6.0V VSS SoftStart Voltage (Survival) −0.3V to +6.0V −0.3V to +6.0V VOUT Voltage (Survival) IOUT Current (Survival) Internally Limited Junction Temperature −40°C to +150°C (1) (2) (3) (4) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but does not ensure specific performance limits. For ensured specifications and conditions, see the Electrical Characteristics. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. The human body model is a 100 pF capacitor discharged through a 1.5k resistor into each pin. Test method is per JESD22-A114. Device power dissipation must be de-rated based on device power dissipation (PD), ambient temperature (TA), and package junction to ambient thermal resistance (θJA). Additional heat-sinking may be required to ensure that the device junction temperature (TJ) does not exceed the maximum operating rating. See the Application Information section for details. Operating Ratings (1) VIN Supply Voltage VBIAS Supply Voltage (2) (VOUT + VDO) to VBIAS 0.8V ≤ VOUT ≤ 1.2V 1.2V < VOUT ≤ 1.8V VEN Voltage 0 mA to 1.5A Junction Temperature Range (3) (2) (3) 4.5V to 5.5V 0.0V to VBIAS IOUT (1) 3.0V to 5.5V −40°C to +125°C Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but does not ensure specific performance limits. For ensured specifications and conditions, see the Electrical Characteristics. VIN cannot exceed either VBIAS or 4.5V, whichever value is lower. Device power dissipation must be de-rated based on device power dissipation (PD), ambient temperature (TA), and package junction to ambient thermal resistance (θJA). Additional heat-sinking may be required to ensure that the device junction temperature (TJ) does not exceed the maximum operating rating. See the Application Information section for details. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LP38852 3 LP38852 SNVS482E – JANUARY 2007 – REVISED APRIL 2013 www.ti.com Electrical Characteristics Unless otherwise specified: VOUT = 0.80V, VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, VEN = VBIAS, IOUT = 10 mA, CIN = COUT = 10 µF, CBIAS = 1 µF, CSS = open. Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are ensured through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Symbol Parameter Conditions VOUT(NOM)+1V ≤ VIN ≤ VBIAS ≤ 4.5V 3.0V ≤ VBIAS ≤ 5.5V, 10 mA ≤ IOUT ≤ 1.5A VADJ VADJ Accuracy MIN TYP MAX 492.5 485 500 507.5 515 Units (1) mV VOUT(NOM)+1V ≤ VIN ≤ VBIAS ≤ 4.5V (1) 3.0V ≤ VBIAS ≤ 5.5V, 10 mA ≤ IOUT ≤ 1.5A, 0°C ≤ TJ ≤ +125°C 490 3.0V ≤ VBIAS ≤ 5.5V 0.80 1.20 4.5V ≤ VBIAS ≤ 5.5V 0.80 1.80 500 510 VOUT VOUT Range ΔVOUT/ΔVIN Line Regulation, VIN (2) VOUT(NOM)+1V ≤ VIN ≤ VBIAS ≤ 4.5V - 0.04 - %/V ΔVOUT/ΔVBIAS Line Regulation, VBIAS (2) 3.0V ≤ VBIAS ≤ 5.5V - 0.10 - %/V 10 mA ≤ IOUT ≤ 1.5A - 0.2 - %/A mV ΔVOUT/ΔIOUT Output Voltage Load Regulation (3) (4) VDO Dropout Voltage IGND(IN) Quiescent Current Drawn from VIN Supply IGND(BIAS) Quiescent Current Drawn from VBIAS Supply V IOUT = 1.5A - 130 165 180 VOUT = 0.80V, VBIAS = 3.0V 10 mA ≤ IOUT ≤ 1.5A - 7.0 8.5 9.0 mA 1 100 300 μA 3.0 3.8 4.5 mA 100 170 200 μA 2.20 2.00 2.45 2.70 2.90 V 60 50 150 300 350 mV - 4.5 - A 11.0 13.5 16.0 kΩ - 675 - μs - VEN ≤ 0.5V 10 mA ≤ IOUT ≤ 1.5A - VEN ≤ 0.5V UVLO Under-Voltage Lock-Out Threshold VBIAS rising until device is functional UVLO(HYS) Under-Voltage Lock-Out Hysteresis VBIAS falling from UVLO threshold until device is non-functional ISC Output Short-Circuit Current VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, VOUT = 0.0V Soft-Start rSS Soft-Start internal resistance tSS Soft-Start time tSS = CSS × rSS × 5 CSS = 10 nF Enable VEN = VBIAS 0.01 - VEN = 0.0V, VBIAS = 5.5V -19 -13 -30 -40 -51 Enable Voltage Threshold VEN rising until Output = ON 1.00 0.90 1.25 1.50 1.55 V VEN(HYS) Enable Voltage Hysteresis VEN falling from VEN(ON) until Output = OFF 50 30 100 150 200 mV tOFF Turn-OFF Delay Time RLOAD x COUT << tOFF - 20 - tON Turn-ON Delay Time RLOAD x COUT << tON - 15 - IEN ENABLE pin Current VEN(ON) (1) (2) (3) (4) 4 μA µs VIN cannot exceed either VBIAS or 4.5V, whichever value is lower. Output voltage line regulation is defined as the change in output voltage from nominal value resulting from a change in input voltage. Output voltage load regulation is defined as the change in output voltage from nominal value as the load current increases from no load to full load. Dropout voltage is defined the as input to output voltage differential (VIN - VOUT) where the input voltage is low enough to cause the output voltage to drop 2% from the nominal value. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LP38852 LP38852 www.ti.com SNVS482E – JANUARY 2007 – REVISED APRIL 2013 Electrical Characteristics (continued) Unless otherwise specified: VOUT = 0.80V, VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, VEN = VBIAS, IOUT = 10 mA, CIN = COUT = 10 µF, CBIAS = 1 µF, CSS = open. Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are ensured through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Symbol Parameter Conditions MIN TYP MAX VIN = VOUT(NOM) + 1V, f = 120 Hz - 80 - VIN = VOUT(NOM) + 1V, f = 1 kHz - 65 - VBIAS = VOUT(NOM) + 3V, f = 120 Hz - 58 - VBIAS = VOUT(NOM) + 3V, f = 1 kHz - 58 - f = 120 Hz - 1 - BW = 10 Hz − 100 kHz - 150 - BW = 300 Hz − 300 kHz - 90 - Units AC Parameters PSRR (VIN) PSRR (VBIAS) Ripple Rejection for VIN Input Voltage Ripple Rejection for VBIAS Voltage Output Noise Density en Output Noise Voltage dB µV/√Hz µVRMS Thermal Parameters TSD Thermal Shutdown Junction Temperature - 160 - TSD(HYS) Thermal Shutdown Hysteresis - 10 - TO-220-7 - 60 - θJ-A Thermal Resistance, Junction to Ambient (5) DDPAK-7 - 60 - SO PowerPAD-8 - 168 - TO-220-7 - 3 - DDPAK-7 - 3 - SO PowerPAD-8 - 11 - θJ-C (5) (6) Thermal Resistance, Junction to Case (5) (6) °C °C/W Device power dissipation must be de-rated based on device power dissipation (PD), ambient temperature (TA), and package junction to ambient thermal resistance (θJA). Additional heat-sinking may be required to ensure that the device junction temperature (TJ) does not exceed the maximum operating rating. See the Application Information section for details. For TO-220 and DDPAK: θJ-C refers to the BOTTOM surface of the package, under the epoxy body, as the 'CASE'. For SO PowerPAD8: θJ-C refers to the DAP (aka: Exposed Pad) on BOTTOM surface of the package as the 'CASE'. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LP38852 5 LP38852 SNVS482E – JANUARY 2007 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics Refer to the Typical Application Circuit. Unless otherwise specified: TJ = 25°C, R1 = 1.40 kΩ, R2 = 1.00 kΩ, CFF= 0.01 µF, VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, IOUT = 10 mA, CIN = 10 µF Ceramic, COUT = 10 µF Ceramic, CBIAS = 1 µF Ceramic, CSS = Open. 6 VBIAS Ground Pin Current (IGND(BIAS)) vs VBIAS VBIAS Ground Pin Current (IGND(BIAS)) vs Temperature Figure 4. Figure 5. VIN Ground Pin Current vs Temperature Load Regulation vs Temperature Figure 6. Figure 7. Dropout Voltage (VDO) vs Temperature Output Current Limit (ISC) vs Temperature Figure 8. Figure 9. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LP38852 LP38852 www.ti.com SNVS482E – JANUARY 2007 – REVISED APRIL 2013 Typical Performance Characteristics (continued) Refer to the Typical Application Circuit. Unless otherwise specified: TJ = 25°C, R1 = 1.40 kΩ, R2 = 1.00 kΩ, CFF= 0.01 µF, VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, IOUT = 10 mA, CIN = 10 µF Ceramic, COUT = 10 µF Ceramic, CBIAS = 1 µF Ceramic, CSS = Open. VOUT vs Temperature VOUT vs VIN Figure 10. Figure 11. UVLO Thresholds vs Temperature Soft-Start rSS Variation vs Temperature Figure 12. Figure 13. VOUT vs CSS, 10 nF to 47 nF Enable Thresholds (VEN) vs Temperature Figure 14. Figure 15. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LP38852 7 LP38852 SNVS482E – JANUARY 2007 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) Refer to the Typical Application Circuit. Unless otherwise specified: TJ = 25°C, R1 = 1.40 kΩ, R2 = 1.00 kΩ, CFF= 0.01 µF, VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, IOUT = 10 mA, CIN = 10 µF Ceramic, COUT = 10 µF Ceramic, CBIAS = 1 µF Ceramic, CSS = Open. 8 Enable Pull-Down Current (IEN) vs Temperature Enable Pull-Up Resistor (rEN) vs Temperature Figure 16. Figure 17. VIN Line Transient Response VIN Line Transient Response Figure 18. Figure 19. VBIAS Line Transient Response VBIAS Line Transient Response Figure 20. Figure 21. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LP38852 LP38852 www.ti.com SNVS482E – JANUARY 2007 – REVISED APRIL 2013 Typical Performance Characteristics (continued) Refer to the Typical Application Circuit. Unless otherwise specified: TJ = 25°C, R1 = 1.40 kΩ, R2 = 1.00 kΩ, CFF= 0.01 µF, VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, IOUT = 10 mA, CIN = 10 µF Ceramic, COUT = 10 µF Ceramic, CBIAS = 1 µF Ceramic, CSS = Open. Load Transient Response, COUT = 10 µF Ceramic Load Transient Response, COUT = 10 µF Ceramic Figure 22. Figure 23. Load Transient Response, COUT = 100 µF Ceramic Load Transient Response, COUT = 100 µF Ceramic Figure 24. Figure 25. Load Transient Response, COUT = 100 µF Tantalum Load Transient Response, COUT = 100 µF Tantalum Figure 26. Figure 27. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LP38852 9 LP38852 SNVS482E – JANUARY 2007 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) Refer to the Typical Application Circuit. Unless otherwise specified: TJ = 25°C, R1 = 1.40 kΩ, R2 = 1.00 kΩ, CFF= 0.01 µF, VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, IOUT = 10 mA, CIN = 10 µF Ceramic, COUT = 10 µF Ceramic, CBIAS = 1 µF Ceramic, CSS = Open. VBIAS PSRR VIN PSRR Figure 28. Figure 29. Output Noise Figure 30. 10 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LP38852 LP38852 www.ti.com SNVS482E – JANUARY 2007 – REVISED APRIL 2013 Block Diagram OUT IN LP38852-ADJ BIAS Under-Voltage Lock-Out Thermal Shut Down rEN ADJ EN Enable 1.2V rSS VREF SS ILIMIT GND 0.6V APPLICATION INFORMATION EXTERNAL CAPACITORS To assure regulator stability, input and output capacitors are required as shown in the Typical Application Circuit. Output Capacitor A minimum output capacitance of 10 µF, ceramic, is required for stability. The amount of output capacitance can be increased without limit. The output capacitor must be located less than 1 cm from the output pin of the IC and returned to the device ground pin with a clean analog ground. Only high quality ceramic types such as X5R or X7R should be used, as the Z5U and Y5F types do not provide sufficient capacitance over temperature. Tantalum capacitors will also provide stable operation across the entire operating temperature range. However, the effects of ESR may provide variations in the output voltage during fast load transients. Using the minimum recommended 10 µF ceramic capacitor at the output will allow unlimited capacitance, Tantalum and/or Aluminum, to be added in parallel. Input Capacitor The input capacitor must be at least 10 µF, but can be increased without limit. It's purpose is to provide a low source impedance for the regulator input. A ceramic capacitor, X5R or X7R, is recommended. Tantalum capacitors may also be used at the input pin. There is no specific ESR limitation on the input capacitor (the lower, the better). Aluminum electrolytic capacitors can be used, but are not recommended as their ESR increases very quickly at cold temperatures. They are not recommended for any application where the ambient temperature falls below 0°C. Bias Capacitor The capacitor on the bias pin must be at least 1 µF, and can be any good quality capacitor (ceramic is recommended). Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LP38852 11 LP38852 SNVS482E – JANUARY 2007 – REVISED APRIL 2013 www.ti.com Feed Forward Capacitor, CFF (Refer to the Typical Application Circuit) When using a ceramic capacitor for COUT, the typical ESR value will be too small to provide any meaningful positive phase compensation, FZ, to offset the internal negative phase shifts in the gain loop. FZ = (1 / (2 x π x COUT x ESR) ) (1) A capacitor placed across the gain resistor R1 will provide additional phase margin to improve load transient response of the device. This capacitor, CFF, in parallel with R1, will form a zero in the loop response given by the formula: FZ = (1 / (2 x π x CFF x R1) ) (2) For optimum load transient response select CFF so the zero frequency, FZ, falls between 10 kHz and 15 kHz. (CFF = (1 / (2 x π x R1 x FZ) (3) The phase lead provided by CFF diminishes as the DC gain approaches unity, or VOUT approaches VADJ. This is because CFF also forms a pole with a frequency of: FP = (1 / (2 x π x CFF x (R1 || R2) ) ) (4) It's important to note that at higher output voltages, where R1 is much larger than R2, the pole and zero are far apart in frequency. At lower output voltages the frequency of the pole and the zero mover closer together. The phase lead provided from CFF diminishes quickly as the output voltage is reduced, and has no effect when VOUT = VADJ. For this reason, relying on this compensation technique alone is adequate only for higher output voltages. For the LP38852, the practical minimum VOUT is 0.8V when a ceramic capacitor is used for COUT. Figure 31. FZERO and FPOLE vs Gain SETTING THE OUTPUT VOLTAGE (Refer to the Typical Application Circuit) The output voltage is set using the external resistive divider R1 and R2. The output voltage is given by the formula: § § R1 ·· VOUT = VADJ x ¨1 + ¨ ¸¨ © © R2 ¹¹ (5) The resistors used for R1 and R2 should be high quality, tight tolerance, and with matching temperature coefficients. It is important to remember that, although the value of VADJ is ensured, the use of low quality resistors for R1 and R2 can easily produce a VOUT value that is unacceptable. It is recommended that the values selected for R1 and R2 are such that the parallel value is less than 10 kΩ. This is to prevent internal parasitic capacitances on the ADJ pin from interfering with the FZ pole set by R1 and CFF. ( (R1 x R2) / (R1 + R2) ) ≤ 10 kΩ 12 (6) Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LP38852 LP38852 www.ti.com SNVS482E – JANUARY 2007 – REVISED APRIL 2013 Table 1 lists some suggested, best fit, standard ±1% resistor values for R1 and R2, and a standard ±10% capacitor values for CFF, for a range of VOUT values. Other values of R1, R2, and CFF are available that will give similar results. Table 1. VOUT R1 R2 CFF FZ 0.8V 1.07 kΩ 1.78 kΩ 12 nF 12.4 kHz 0.9V 1.50 kΩ 1.87 kΩ 8.2 nF 12.9 kHz 1.0V 1.00 kΩ 1.00 kΩ 12 nF 13.3 kHz 1.1V 1.65 kΩ 1.37 kΩ 8.2 nF 11.8 kHz 1.2V 1.40 kΩ 1.00 kΩ 10 nF 11.4 kHz 1.3V 1.15 kΩ 715 Ω 12 nF 11.5 kHz 1.4V 1.07 kΩ 590 Ω 12 nF 12.4 kHz 1.5V 2.00 kΩ 1.00 kΩ 6.8 nF 11.7 kHz 1.6V 1.65 kΩ 750 Ω 8.2 nF 11.8 kHz 1.7V 2.55 kΩ 1.07 kΩ 5.6 nF 11.1 kHz 1.8V 2.94 kΩ 1.13 kΩ 4.7 nF 11.5 kHz Please refer to Application Note 1378 for additional information on how resistor tolerances affect the calculated VOUT value. INPUT VOLTAGE The input voltage (VIN) is the high current external voltage rail that will be regulated down to a lower voltage, which is applied to the load. The input voltage must be at least VOUT + VDO, and no higher than whatever value is used for VBIAS. BIAS VOLTAGE The bias voltage (VBIAS) is a low current external voltage rail required to bias the control circuitry and provide gate drive for the N-FET pass transistor. When VOUT is set to 1.20V, or less, VBIAS may be anywhere in the operating range of 3.0V to 5.5V. If VOUT is set higher than 1.20V, VBIAS must be between 4.5V and 5.5V to ensure proper operation of the device. UNDER VOLTAGE LOCKOUT The bias voltage is monitored by a circuit which prevents the device from functioning when the bias voltage is below the Under-Voltage Lock-Out (UVLO) threshold of approximately 2.45V. As the bias voltage rises above the UVLO threshold the device control circuitry becomes active. There is approximately 150 mV of hysteresis built into the UVLO threshold to provide noise immunity. When the bias voltage is between the UVLO threshold and the Minimum Operating Rating value of 3.0V the device will be functional, but the operating parameters will not be within the ensured limits. SUPPLY SEQUENCING There is no requirement for the order that VIN or VBIAS are applied or removed. One practical limitation is that the Soft-Start circuit starts charging CSS when both VBIAS rises above the UVLO threshold and the Enable pin is above the VEN(ON) threshold. If the application of VIN is delayed beyond this point the benefits of Soft-Start will be compromised. In any case, the output voltage cannot be specified until both VIN and VBIAS are within the range of specified operating values. If used in a dual-supply system where the regulator output load is returned to a negative supply, the output pin must be diode clamped to ground. A Schottky diode is recommended for this diode clamp. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LP38852 13 LP38852 SNVS482E – JANUARY 2007 – REVISED APRIL 2013 www.ti.com REVERSE VOLTAGE A reverse voltage condition will exist when the voltage at the output pin is higher than the voltage at the input pin. Typically this will happen when VIN is abruptly taken low and COUT continues to hold a sufficient charge such that the input to output voltage becomes reversed. The NMOS pass element, by design, contains no body diode. This means that, as long as the gate of the pass element is not driven, there will not be any reverse current flow through the pass element during a reverse voltage event. The gate of the pass element is not driven when VBIAS is below the UVLO threshold, or when the Enable pin is held low. When VBIAS is above the UVLO threshold, and the Enable pin is above the VEN(ON) threshold, the control circuitry is active and will attempt to regulate the output voltage. Since the input voltage is less than the output voltage the control circuit will drive the gate of the pass element to the full VBIAS potential when the output voltage begins to fall. In this condition, reverse current will flow from the output pin to the input pin , limited only by the RDS(ON) of the pass element and the output to input voltage differential. Discharging an output capacitor up 1000 µF in this manner will not damage the device as the current will rapidly decay. However, continuous reverse current should be avoided. SOFT-START The LP38852 incorporates a Soft-Start function that reduces the start-up current surge into the output capacitor (COUT) by allowing VOUT to rise slowly to the final value. This is accomplished by controlling VREF at the SS pin. The soft-start timing capacitor (CSS) is internally held to ground until both VBIAS rises above the Under-Voltage Lock-Out threshold (ULVO) and the Enable pin is higher than the VEN(ON) threshold. VREF will rise at an RC rate defined by the internal resistance of the SS pin (rSS), and the external capacitor connected to the SS pin. This allows the output voltage to rise in a controlled manner until steady-state regulation is achieved. Typically, five time constants are recommended to assure that the output voltage is sufficiently close to the final steady-state value. During the soft-start time the output current can rise to the built-in current limit. Soft-Start Time = CSS × rSS × 5 (7) Since the VOUT rise will be exponential, not linear, the in-rush current will peak during the first time constant (τ), and VOUT will require four additional time constants (4τ) to reach the final value (5τ) . After achieving normal operation, should either VBIAS fall below the ULVO threshold, or the Enable pin fall below the VEN(OFF) threshold, the device output will be disabled and the Soft-Start capacitor (CSS) discharge circuit will become active. The CSS discharge circuit will remain active until VBIAS falls to 500 mV (typical). When VBIAS falls below 500 mV (typical), the CSS discharge circuit will cease to function due to a lack of sufficient biasing to the control circuitry. Since VREF appears on the SS pin, any leakage through CSS will cause VREF to fall, and thus affect VOUT. A leakage of 50 nA (about 10 MΩ) through CSS will cause VOUT to be approximately 0.1% lower than nominal, while a leakage of 500 nA (about 1 MΩ) will cause VOUT to be approximately 1% lower than nominal. Typical ceramic capacitors will have a factor of 10X difference in leakage between 25°C and 85°C, so the maximum ambient temperature must be included in the capacitor selection process. Typical CSS values will be in the range of 1 nF to 100 nF, providing typical Soft-Start times in the range of 70 μs to 7 ms (5τ). Values less than 1 nF can be used, but the Soft-Start effect will be minimal. Values larger than 100 nF will provide soft-start, but may not be fully discharged if VBIAS falls from the UVLVO threshold to less than 500 mV in less than 100 µs. Figure 32 shows the relationship between the COUT value and a typical CSS value. 14 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LP38852 LP38852 www.ti.com SNVS482E – JANUARY 2007 – REVISED APRIL 2013 Figure 32. Typical CSS vs COUT Values The CSS capacitor must be connected to a clean ground path back to the device ground pin. No components, other than CSS, should be connected to the SS pin, as there could be adverse effects to VOUT. If the Soft-Start function is not needed the SS pin should be left open, although some minimal capacitance value is always recommended. ENABLE OPERATION The Enable pin (EN) provides a mechanism to enable, or disable, the regulator output stage. The Enable pin has an internal pull-up, through a typical 180 kΩ resistor, to VBIAS. If the Enable pin is actively driven, pulling the Enable pin above the VEN threshold of 1.25V (typical) will turn the regulator output on, while pulling the Enable pin below the VEN threshold will turn the regulator output off. There is approximately 100 mV of hysteresis built into the Enable threshold provide noise immunity. If the Enable function is not needed this pin should be left open, or connected directly to VBIAS. If the Enable pin is left open, stray capacitance on this pin must be minimized, otherwise the output turn-on will be delayed while the stray capacitance is charged through the internal resistance (rEN). POWER DISSIPATION AND HEAT-SINKING Additional copper area for heat-sinking may be required depending on the maximum device dissipation (PD) and the maximum anticipated ambient temperature (TA) for the device. Under all possible conditions, the junction temperature must be within the range specified under operating conditions. The total power dissipation of the device is the sum of three different points of dissipation in the device. The first part is the power that is dissipated in the NMOS pass element, and can be determined with the formula: PD(PASS) = (VIN - VOUT) × IOUT (8) The second part is the power that is dissipated in the bias and control circuitry, and can be determined with the formula: PD(BIAS) = VBIAS × IGND(BIAS) where • IGND(BIAS) is the portion of the operating ground current of the device that is related to VBIAS (9) The third part is the power that is dissipated in portions of the output stage circuitry, and can be determined with the formula: PD(IN) = VIN × IGND(IN) where • IGND(IN) is the portion of the operating ground current of the device that is related to VIN (10) The total power dissipation is then: PD = PD(PASS) + PD(BIAS) + PD(IN) (11) Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LP38852 15 LP38852 SNVS482E – JANUARY 2007 – REVISED APRIL 2013 www.ti.com The maximum allowable junction temperature rise (ΔTJ) depends on the maximum anticipated ambient temperature (TA) for the application, and the maximum allowable operating junction temperature (TJ(MAX)). 'J = TJ(MAX) - TA(MAX) (12) The maximum allowable value for junction to ambient Thermal Resistance, θJA, can be calculated using the formula: TJA d 'TJ PD (13) Heat-Sinking the TO-220 Package The TO-220 package has a θJA rating of 60°C/W and a θJC rating of 3°C/W. These ratings are for the package only, no additional heat-sinking, and with no airflow. If the needed θJA, as calculated above, is greater than or equal to 60°C/W then no additional heat-sinking is required since the package can safely dissipate the heat and not exceed the operating TJ(MAX). If the needed θJA is less than 60°C/W then additional heat-sinking is needed. The thermal resistance of a TO-220 package can be reduced by attaching it to a heat sink or a copper plane on a PC board. If a copper plane is to be used, the values of θJA will be same as shown in next section for DDPAK package. The heat-sink to be used in the application should have a heat-sink to ambient thermal resistance, θHA: T H d T J - (T C + T J ) A A H C where • • • θJA is the required total thermal resistance from the junction to the ambient air θCH is the thermal resistance from the case to the surface of the heart-sink θJC is the thermal resistance from the junction to the surface of the case (14) For this equation, θJC is about 3°C/W for a TO-220 package. The value for θCH depends on method of attachment, insulator, etc. θCH varies between 1.5°C/W to 2.5°C/W. Consult the heat-sink manufacturer datasheet for details and recommendations. Heat-Sinking the DDPAK Package The DDPAK package has a θJA rating of 60°C/W, and a θJC rating of 3°C/W. These ratings are for the package only, no additional heat-sinking, and with no airflow. The DDPAK package uses the copper plane on the PCB as a heat-sink. The tab of this package is soldered to the copper plane for heat sinking. shows a curve for the θJA of DDPAK package for different copper area sizes, using a typical PCB with 1 ounce copper and no solder mask over the copper area for heat-sinking. Figure 33. θJA vs Copper (1 Ounce) Area for the DDPAK package Figure 33 shows that increasing the copper area beyond 1 square inch produces very little improvement. The minimum value for θJA for the DDPAK package mounted to a PCB is 32°C/W. 16 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LP38852 LP38852 www.ti.com SNVS482E – JANUARY 2007 – REVISED APRIL 2013 Figure 34. Maximum Power Dissipation vs Ambient Temperature for the DDPAK Package Figure 34 shows the maximum allowable power dissipation for DDPAK packages for different ambient temperatures, assuming θJA is 35°C/W and the maximum junction temperature is 125°C. Heat-Sinking the SO PowerPAD-8 Package The LP38852MR package has a θJA rating of 168°C/W, and a θJC rating of 11°C/W. The θJA rating of 168°C/W includes the device DAP soldered to an area of 0.008 square inches (0.09 in x 0.09 in) of 1 ounce copper, with no airflow. Figure 35. θJA vs Copper (1 Ounce) Area for the SO PowerPAD-8 Package Increasing the copper area soldered to the DAP to 1 square inch of 1 ounce copper, using a dog-bone type layout, will improve the θJA rating to 98°C/W. Figure 35 shows that increasing the copper area beyond 1 square inch produces very little improvement. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LP38852 17 LP38852 SNVS482E – JANUARY 2007 – REVISED APRIL 2013 www.ti.com Figure 36. Maximum Power Dissipation vs Ambient Temperature for the SO PowerPAD-8 Package Figure 36 shows the maximum allowable power dissipation for the SO PowerPAD-8 package for a range of ambient temperatures, assuming that θJA is 98°C/W and the maximum junction temperature is 125°C. 18 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LP38852 LP38852 www.ti.com SNVS482E – JANUARY 2007 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision D (April 2013) to Revision E • Page Changed layout of National Data Sheet to TI format .......................................................................................................... 18 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LP38852 19 PACKAGE OPTION ADDENDUM www.ti.com 7-Oct-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) LP38852MR-ADJ/NOPB ACTIVE SO PowerPAD DDA 8 95 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 L38852 MRADJ LP38852MRX-ADJ/NOPB ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 L38852 MRADJ LP38852S-ADJ/NOPB ACTIVE DDPAK/ TO-263 KTW 7 45 Pb-Free (RoHS Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP38852S -ADJ LP38852SX-ADJ/NOPB ACTIVE DDPAK/ TO-263 KTW 7 500 Pb-Free (RoHS Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP38852S -ADJ LP38852T-ADJ/NOPB ACTIVE TO-220 NDZ 7 45 Green (RoHS & no Sb/Br) CU SN Level-1-NA-UNLIM -40 to 125 LP38852T -ADJ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 7-Oct-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LP38852MRX-ADJ/NOPB SO Power PAD DDA 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LP38852SX-ADJ/NOPB DDPAK/ TO-263 KTW 7 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP38852MRX-ADJ/NOPB SO PowerPAD DDA 8 2500 367.0 367.0 35.0 LP38852SX-ADJ/NOPB DDPAK/TO-263 KTW 7 500 367.0 367.0 45.0 Pack Materials-Page 2 MECHANICAL DATA NDZ0007B TA07B (Rev E) www.ti.com MECHANICAL DATA DDA0008A MRA08A (Rev D) www.ti.com MECHANICAL DATA KTW0007B TS7B (Rev E) BOTTOM SIDE OF PACKAGE www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2013, Texas Instruments Incorporated