TI UCC28060DR

UCC2
8060
UCC28060
www.ti.com .................................................................................................................................................... SLUS767E – MAY 2007 – REVISED NOVEMBER 2008
Natural Interleaving™ DUAL-PHASE TRANSITION-MODE PFC CONTROLLER
NATURAL INTERLEAVING FEATURES
SYSTEM FEATURES
• Easy Phase Management Facilitates
Compliance to Light-Load Efficient Standards
• FailSafe OVP with Dual Paths Prevents Output
Over-voltage Conditions Caused by
Voltage-Sensing Failures
• Sensorless Current Shaping Simplifies Board
Layout and Improves Efficiency
• Inrush Safe Current Limiting:
– Prevents MOSFET conduction during
inrush
– Eliminates reverse recovery events in
output rectifiers
•
•
1
234
85-265VAC
EMI
Filter
•
•
•
•
•
•
•
400 VDC
-
Cost Savings
Improved Efficiency and Design Flexibility
over Traditional, Single-Phase Continuous
Conduction Mode (CCM)
Input Filter and Output Capacitor Current
Cancellation:
– Reduced current ripple for higher system
reliability and smaller bulk capacitor
– Reduced EMI filter size
Enables Use of Low-Cost Diodes without
Extensive Snubber Circuitry
Improved Light-Load Efficiency
Improved Transient Response
Complete System-Level Protection
1-A Source/1.8-A Sink Gate Drivers
Operating Temperature Range: –40°C to
+125°C in an SOIC 16-pin package
+
VCC
APPLICATIONS
ZCDA
GDA
CS
VINAC
ZCDB
UCC28060
GDB
TSET
PWMCNTL
Power-Good to Downstream Converter
•
•
•
•
•
100-W to 800-W Power Supplies
LCD, Plasma, and DLP® TVs
Computer Power Supplies
Entry Level Servers
Electronic Lighting Ballasts
VSENSE
5
POUT = 600 W
VOUT = 400 V
COMP
PHB
HVSEN
AGND
PGND
Typical Application Circuit
Capacitor Ripple Current (A)
VREF
4
1-Phase TM
3
1-Phase CCM
2
2-Phase TM Interleave
1
70
120
170
220
270
Input Voltage (V)
Ripple Current Reduction
1
2
3
4
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DLP is a registered trademark of Texas Instruments.
Natural Interleaving is a trademark of Texas Instuments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2008, Texas Instruments Incorporated
UCC28060
SLUS767E – MAY 2007 – REVISED NOVEMBER 2008 .................................................................................................................................................... www.ti.com
CONTENTS
•
•
•
•
•
•
•
•
Ordering Information 2
Electrical Characteristics 4
Device Information 7
Functional Block Diagram 9
Typical Characteristics 10
Application Information 17
Design Example 23
Additional References 30
DESCRIPTION
Optimized for high-volume consumer applications, this solution extends the advantages of transition mode—high
efficiency with low-cost components—to higher power ratings than previously possible. By utilizing a Natural
Interleaving technique, both channels operate as masters (that is, there is no slave channel) synchronized to the
same frequency. This approach delivers inherently strong matching, faster responses, and ensures that each
channel operates in transition mode.
Complete system-level protections feature input brownout, output over-voltage, open-loop, overload, soft-start,
phase-fail detection, and thermal shutdown. The additional FailSafe over-voltage protection (OVP) feature
protects against shorts to an intermediate voltage that, if undetected, could lead to catastrophic device failure.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
(1)
(2)
2
PART NUMBER
PACKAGE (2)
OPERATING TEMPERATURE RANGE, TA
UCC28060D
SOIC 16-Pin (D)
–40°C to +125°C
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
SOIC (D) package is available taped and reeled by adding R to the above part number. Reeled quantities for UCC28060DR are 2500
devices per reel.
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ABSOLUTE MAXIMUM RATINGS (1)
All voltages are with respect to GND, –40°C < TJ = TA < +125°C, and currents are positive into and negative out of the
specified terminal, unless otherwise noted.
UCC28060
Input voltage range
VCC (2)
–0.5 to +21
PWMCNTL
–0.5 to +20
COMP (3), CS, PHB, HVSEN (4), VINAC (4), VSENSE (4)
–0.5 to +7
ZCDA, ZCDB
–0.5 to +4
Continuous input current
VCC
20
Input current
PWMCNTL
10
Input current range
ZCDA, ZCDB, VSENSE
Output current
VREF
–10
Continuous gate current
GDA, GDB (5)
±25
Junction temperature, TJ
Lead temperature, TSOL
(1)
(2)
(3)
(4)
(5)
UNIT
V
–5 to +5
mA
Operating
–40 to +125
Storage
–65 to +150
Soldering, 10s
°C
+260
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other condition beyond those included under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods of time may affect device reliability.
Voltage on VCC is internally clamped. VCC may exceed the absolute maximum input voltage if the source is current limited below the
absolute maximum continuous VCC input current level.
In normal use, COMP is connected to capacitors and resistors and is internally limited in voltage swing.
In normal use, VINAC, VSENSE, and HVSEN are connected to resistors and are internally limited in voltage swing. Although not
recommended for extended use, VINAC, VSENSE, and HVSEN can survive input currents as high as ±10 mA from high voltage
sources.
No GDA or GDB current limiting is required when driving a power MOSFET gate. However, a small series resistor may be required to
damp ringing due to stray inductance. See Figure 13 and Figure 14 for details.
DISSIPATION RATINGS
(1)
PACKAGE
THERMAL IMPEDANCE
JUNCTION-TO-AMBIENT
TA = +25°C POWER RATING
TA = +85°C POWER RATING
SOIC 16-Pin (D)
140°C/W (1)
890 mW (1)
460 mW (1)
Tested per JEDEC EIA/JESD 51-1. Thermal resistance is a strong function of board construction and layout. Air flow will reduce thermal
resistance. This number is only a general guide; see TI document SPRA953 device Thermal Metrics.
RECOMMENDED OPERATING CONDITIONS
All voltages are with respect to GND, –40°C < TJ = TA < +125°C, and currents are positive into and negative out of the
specified terminal, unless otherwise noted.
MIN
MAX
VCC input voltage from a low-impedance source
14
21
V
VCC input current from a high-impedance source
8
18
mA
VREF load current
0
–2
mA
VINAC Input voltage
0
6
V
ZCDA, ZCDB series resistor
TSET resistor to program PWM on-time
HVSEN input voltage
PWMCNTL pull-up resistor to VREF
UNIT
20
80
kΩ
66.5
270
kΩ
0.8
4.5
V
1
10
kΩ
ELECTROSTATIC DISCHARGE (ESD) PROTECTION
RATING
UNIT
Human body model (HBM)
2000
V
Charged device model (CDM)
500
V
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ELECTRICAL CHARACTERISTICS
At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 5 V, RTSET = 133 kΩ; all voltages
are with respect to GND, all outputs unloaded, –40°C < TJ = TA < +125°C, and currents are positive into and negative out of
the specified terminal, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCC BIAS SUPPLY
VCC(shunt)
VCC shunt voltage (1)
IVCC = 10 mA
24
26
V
IVCC(stby)
VCC current, disabled
VSENSE = 0 V
100
200
µA
IVCC(on)
VCC current, enabled
VSENSE = 6 V
5
8
mA
22
UNDERVOLTAGE LOCKOUT (UVLO)
VCC(on)
VCC turn-on threshold
11.5
12.6
13.5
V
VCC(off)
VCC turn-off threshold
9.5
10.35
11.5
V
1.85
2.25
2.65
V
5.82
UVLO Hysteresis
REFERENCE
VREF
VREF output voltage, no load
IVREF = 0 mA
6.00
6.18
VREF change with load
0 mA ≤ IVREF ≤ –2 mA
1
6
mV
V
VREF change with VCC
12 V ≤ VCC ≤ 20 V
1
10
mV
5.85
6.00
6.15
5.82
6.00
6.18
V
800
nA
ERROR AMPLIFIER
VSENSE input regulation voltage
TA = +25°C
VSENSE input regulation voltage
gm
VOVP
V
VSENSE input bias current
In regulation
125
300
COMP high voltage, clamped
VSENSE = 5.8 V
4.70
4.95
5.10
V
COMP low voltage, saturated
VSENSE = 6.2 V
0.03
0.125
V
VSENSE to COMP transconductance
COMP = 3 V,
5.94 V < VSENSE < 6.06 V
75
96
110
µS
COMP source current, overdriven
VSENSE = 5 V, COMP = 3 V
–120
–160
–190
µA
COMP sink current
VSENSE = 6.4 V, COMP = 3 V
18
25
32
µA
VSENSE threshold for COMP offset enable, down
from VREF
Voltage below VREF
135
185
235
mV
VSENSE over-voltage threshold, rising
6.25
6.45
6.7
V
VSENSE over-voltage hysteresis
0.1
0.2
0.4
V
VSENSE enable threshold, rising
1.15
1.25
1.35
V
VSENSE enable hysteresis
0.02
0.05
0.2
V
2.50
2.65
V
OUTPUT MONITORING
VPWMCNTL
(1)
4
HVSEN threshold to PWMCNTL
HVSEN rising
2.35
HVSEN input bias current, high
HVSEN = 3 V
–0.5
0.5
µA
HVSEN input bias current, low
HVSEN = 2 V
28
36
41
µA
HVSEN rising threshold to over-voltage fault
4.64
4.87
5.1
V
HVSEN falling threshold to over-voltage fault
4.45
4.67
4.80
V
8
14
20
ms
1
µA
0.2
0.5
V
Phase Fail filter time to PWMCNTL high
PHB = 5 V,
ZCDA switching, ZCDB = 0.5 V
PWMCNTL leakage current high
HVSEN = 2 V, PWMCNTL = 15 V
PWMCNTL output voltage low
HVSENS = 3 V, IPWMCNTL = 5 mA
–1
Excessive VCC input voltage and current will damage the device. This clamp does not protect the device from an unregulated supply. If
an unregulated supply is used, a Fixed Positive Voltage Regulator such as the UA78L15A is recommended. See the Absolute Maximum
Ratings table for the limits on VCC voltage and current.
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ELECTRICAL CHARACTERISTICS (continued)
At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 5 V, RTSET = 133 kΩ; all voltages
are with respect to GND, all outputs unloaded, –40°C < TJ = TA < +125°C, and currents are positive into and negative out of
the specified terminal, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
GATE DRIVE (2)
GDA, GDB output voltage high
IGDA, IGDB = –100 mA
11.5
13
15
V
GDA, GDB output voltage high, clamped
VCC = 20 V, IGDA, IGDB = –5 mA
12
13.5
15
V
GDA, GDB output voltage high, low VCC
VCC = 12 V, IGDA, IGDB = –5 mA
10
10.5
11.5
V
GDA, GDB on-resistance high
IGDA, IGDB = –100 mA
8
14
Ω
GDA, GDB output voltage low
IGDA, IGDB = 100 mA
0.15
0.3
V
GDA, GDB on-resistance low
IGDA, IGDB = 100 mA
2
3
Ω
Rise time
1 V to 9 V, CLOAD = 1 nF
18
30
ns
Fall time
9 V to 1 V, CLOAD = 1 nF
12
25
ns
GDA, GDB output voltage UV
IGDA, IGDB = 2.5 mA
1.6
2
V
ZERO CURRENT DETECTOR
ZCDA, ZCDB voltage threshold, falling
0.8
1.0
1.2
V
ZCDA, ZCDB voltage threshold, rising
1.5
1.68
1.88
V
3.0
3.4
V
0.5
µA
–0.2
0
V
45
100
ns
ZCDA, ZCDB clamp, high
IZCDA = +2 mA, IZCDB = +2 mA
2.6
ZCDA, ZCDB input bias current
ZCDA = 1.4 V, ZCDB = 1.4 V
–0.5
IZCDA = –2 mA, IZCDB = –2 mA
–0.4
ZCDA, ZCDB clamp, low
ZCDA, ZCDB delay to GDA, GDB outputs
(2)
Respective gate drive output rising 10%
from zero crossing input falling to 1 V
CURRENT SENSE
–150
–250
µA
CS current limit rising threshold
–0.18
–0.20
–0.22
V
CS current limit falling threshold
–0.005
–0.015
–0.029
V
60
100
ns
CS input bias current
CS current limit response time
At rising threshold
From CS exceeding threshold –0.05 V to
GDx dropping 10%
(2)
MAINS INPUT
VINAC input bias current
VINAC = 2 V
–0.5
0.5
µA
VINAC line range threshold, rising
To PWM on-time change
3.25
3.45
3.60
V
3.05
3.20
3.35
V
18
26
36
VINAC line range threshold, falling
VINAC line falling range change filter time (2)
VINAC line changes for less than the range
change filter time
VINAC brownout threshold
VINAC falling
1.34
1.39
1.44
V
VINAC brownout current
VINAC = 1 V
5
7
9
µA
VINAC brownout filter time
VINAC fails to exceed the brownout
threshold for the brownout filter time
340
440
540
ms
ms
BROWNOUT
(2)
Refer to Figure 13, Figure 14, Figure 15, and Figure 16 in the Typical Characteristics for typical gate drive waveforms.
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ELECTRICAL CHARACTERISTICS (continued)
At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 5 V, RTSET = 133 kΩ; all voltages
are with respect to GND, all outputs unloaded, –40°C < TJ = TA < +125°C, and currents are positive into and negative out of
the specified terminal, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PULSE-WIDTH MODULATOR
On-time factor, phases A and B, high range
VINAC = 3.75 V, VSENSE = 5.8 V (3)
1.25
1.35
1.5
µs/V
KTHS
On-time factor, single-phase, A, high range
VINAC = 3.75 V, VSENSE = 5.8 V,
PHB = 0 V (3)
2.4
2.7
3.0
µs/V
KTL
On-time factor, phases A and B, low range
VINAC = 3.2 V, VSENSE = 5.8 V (3)
3.6
4.0
4.4
µs/V
On-time factor, single-phase, A, low range
VINAC = 3.2 V, VSENSE = 5.8 V,
PHB = 0 V (3)
7.2
8
8.9
µs/V
Phase B to phase A on-time matching,
low line range
VSENSE = 5.8 V, VINAC = 3.2 V
–6
6
%
Phase B to phase A on-time matching,
high line range
VSENSE = 5.8V, VINAC = 3.75 V
–6
6
%
KTH
KTLS
Zero-crossing distortion correction additional on
time
T(min)
COMP = 0.25 V, VINAC = 1 V
COMP = 0.25 V, VINAC = 0.1 V
2
µs
20
µs
PHB threshold falling, to single-phase operation,
low line range
To GDB output shutdown VINAC = 1.5 V
0.7
0.8
0.9
V
PHB threshold rising, to two-phase operation,
low line range
To GDB output running VINAC = 1.5 V
0.9
1.0
1.1
V
PHB threshold falling, to single-phase operation,
high line range
To GDB output shutdown VINAC = 4.0 V
1.0
1.1
1.2
V
PHB threshold rising, to two-phase operation,
high line range
To GDB output running VINAC = 4.0 V
1.2
1.3
1.4
V
COMP threshold falling to shutdown
GDA and GDB outputs shutdown
0.125
0.150
0.175
V
COMP threshold rising to run
GDA and GDB outputs running
0.17
0.20
0.23
V
Minimum switching period
RTSET = 133 kΩ (3)
1.7
2.2
2.5
µs
PWM restart time
ZCDA = ZCDB = 2 V (4)
165
200
265
µs
THERMAL SHUTDOWN
(3)
(4)
(5)
6
Thermal shutdown temperature
TJ, temperature rising (5)
+160
°C
Thermal restart temperature
TJ, temperature falling (5)
+140
°C
Gate drive on-time is proportional to VCOMP – 125 mV. The on-time proportionality factor, KT, is different in high and low ranges and also
different in two-phase and single-phase modes. The on-time factor, KT, scales linearly with the value of RTSET. The minimum switching
period is proportional to RTSET.
An output on-time is generated at both GDA and GDB if both ZCDA and ZCDB negative-going edges are not detected for the restart
time. In single-phase mode, the restart time applies for the ZCDA input and the GDA output.
Thermal shutdown occurs at temperatures higher than the normal operating range. Device performance above the normal operating
temperature is not specified or assured.
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DEVICE INFORMATION
UCC28060D
SOIC 16-Pin (D)
Top View
ZCDB
1
16
ZCDA
VSENSE
2
15
VREF
TSET
3
14
GDA
PHB
4
13
PGND
COMP
5
12
VCC
AGND
6
11
GDB
VINAC
7
10
CS
HVSEN
8
9
PWMCNTL
TERMINAL FUNCTIONS
TERMINAL
DESCRIPTION
NAME
NO.
I/O
AGND
6
—
Analog ground: Connect analog signal bypass capacitors, compensation components, and analog
signal returns to this pin. Connect the analog and power grounds at a single point to isolate high-current
noise signals of the power components from interference with the low-current analog circuits.
O
Error amplifier output: The error amplifier is a transconductance amplifier, so this output is a
high-impedance current source. Connect voltage regulation loop compensation components from this
pin to AGND. The on-time seen at the gate drive outputs is proportional to the voltage at this pin minus
an offset of approximately 125 mV. During soft-start events (undervoltage, brownout, or disable), COMP
is pulled low. Normal operation only resumes after the soft-start event clears and COMP has been
discharged below 0.5 V, making sure that the circuit restarts with a low COMP voltage and a short
on-time. Do not connect COMP to a low-impedance source that would interfere with COMP falling below
0.5 V.
Current sense input: Connect the current sense resistor and the negative terminal of the diode bridge
to this pin. Connect the return of the current sense resistor to the AGND pin with a separate trace. As
input current increases, the voltage on CS goes more negative. This cycle-by-cycle over-current
protection limits input current by turning off both gate driver (GDx) outputs when CS is more negative
than the CS rising threshold (approximately –200 mV). The GD outputs remain low until CS falls to the
CS falling threshold (approximately –15 mV). Current sense is blanked for approximately 100 ns
following the falling edge of either GD output. This blanking filters noise that occurs when current
switches from a power FET to a boost diode. In most cases, no additional current sense filtering is
required. If filtering is required, the filter series resistance must be under 100 Ω to maintain accuracy. To
prevent excessive negative voltage on the CS pin during inrush conditions, connect the current sensing
resistor to the CS pin through a low value external resistor. As with the filter series resistance, this
external resistor needs to be under 100 Ω to maintain accuracy.
COMP
5
CS
10
I
GDA
14
O
GDB
11
O
HVSEN
8
I
PGND
13
—
Channel A and channel B gate drive output: Connect these pins to the gate of the power FET for
each phase through the shortest connection practical. If it is necessary to use a trace longer than 0.5 in
(12.6 mm) for this connection, some ringing may occur due to trace series inductance. This ringing can
be reduced by adding a 5-Ω to 10-Ω resistor in series with GDA and GDB.
High voltage output sense: The UCC28060 incorporates FailSafe OVP so that any single failure does
not allow the output to boost above safe levels. Output over-voltage is monitored by both VSENSE and
HVSEN and shuts down the PWM if either pin exceeds the appropriate over-voltage threshold. Using
two pins to monitor for over-voltage provides redundant protection and fault tolerance. HVSEN can also
be used to enable a downstream power converter when the voltage on HVSEN is within the operating
region. Select the HVSEN divider ratio for the desired over-voltage and power-good thresholds. Select
the HVSEN divider impedance for the desired power-good hysteresis. During operation, HVSEN must
never fall below 0.8 V. Dropping HVSEN below 0.8 V puts the UCC28060 into a special test mode, used
only for factory testing. A bypass capacitor from HVSEN to AGND is recommended to filter noise and
prevent false over-voltage shutdown.
Power ground for the integrated circuit: Connect this pin to AGND through a separate short trace to
isolate gate driver noise from analog signals.
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TERMINAL FUNCTIONS (continued)
TERMINAL
NAME
DESCRIPTION
I/O
PHB
4
I
Phase B enable: This pin turns on/off channel B of the boost converter. The commanded on-time for
channel A is immediately doubled when channel B is disabled, which helps to keep COMP voltage
constant during the phase management transient. The PHB thresholds change with line range for the
best efficiency when PHB is connected to COMP. PHB can also be driven by external logic signals to
allow customized phase management. To disable phase management, connect the PHB pin to the
VREF pin.
PWMCNTL
9
O
PWM enable logic output: This open-drain output goes low when HVSEN is within the HVSEN good
region and the ZCDA and ZCDB inputs are switching correctly if operating in two-phase mode (see PHB
Pin). Otherwise, PWMCNTL is high impedance.
TSET
3
I
Timing set: PWM on-time programming input. Connect a resistor from TSET to AGND to set the
on-time versus COMP voltage and the minimum period at the gate drive outputs.
VCC
12
—
Bias supply input: Connect this pin to a controlled bias supply of between 14 V and 21 V. Also connect
a 0.1-µF ceramic bypass capacitor from this pin to PGND. This supply powers all circuits in the device
and must be capable of delivering 6 mA dc plus the transient power MOSFET gate charging current.
VINAC
7
I
Input ac voltage sense: For normal operation, connect this pin to a voltage divider across the rectified
input power mains. This input senses input voltage range to set the ramp rate and senses brownout.
Input voltage range changes when the peak voltage on VINAC becomes and stays below the range
change threshold for the range change filter time or the peak voltage on VINAC becomes above the
range change threshold. When the voltage on VINAC remains below the brownout threshold for more
than the brownout filter time, the device enters a brownout mode and both output drives are disabled.
Select the input voltage divider ratio for the desired brownout threshold and power line range. Select the
divider impedance for the desired brownout hysteresis.
VREF
15
O
Voltage reference output: Connect a 0.1-µF ceramic bypass capacitor from this pin to AGND.
This 6 VDC reference can be used to bias other circuits requiring less than 2 mA of total supply current.
I
Output dc voltage sense: Connect this pin to a voltage divider across the output of the power
converter. The error amplifier reference voltage is 6 V. Select the output voltage divider ratio for the
desired output voltage. Connect the ground side of this divider to ground through a separate short trace
for best output regulation accuracy and noise immunity. VSENSE can be pulled low by an open-drain
logic output or 6-V logic output in series with a low-leakage diode to disable the outputs and reduce
VCC current. If VSENSE is disconnected, open-loop protection provides an internal current source to
pull VSENSE low, turning off the gate drivers.
I
Zero current detection inputs: These inputs expect to see a negative edge when the inductor current
in the respective phases go to zero. The inputs are clamped at 0 V and 3 V. Signals should be coupled
through a series resistor that limits the clamping current to less than ±3 mA. Connect these pins through
a current limiting resistor to the zero crossing detection windings of the appropriate boost
I
inductor. The inductor winding must be connected so that this voltage drops when inductor current
decays to zero. When the inductor current drops to zero, the ZCD input must drop below the falling
threshold, approximately 1 V, to cause the gate drive output to rise. When the power MOSFET turns off,
the ZCD input must rise above the rising threshold, approximately 1.7 V, to arm the logic for another
falling ZCD edge.
VSENSE
ZCDA
ZCDB
8
NO.
2
16
1
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FUNCTIONAL BLOCK DIAGRAM
Overcurrent
CS
VINAC
10
-0.2V/-0.015V
+
1.4V
+
HVSENOV
OV
TSD
OC
Burst Operation
SinglePhase
OC
440ms Delay
STOPB
Brownout
7
Thermal
ShutDown
TJ
(UCC28060 only)
7mA
STOPA
12.6V
10.35V
TSD
160C
12
VCC
14
GDA
11
GDB
13
PGND
8
HVSEN
24V
_26 ms
H L Delay
3.20V
UV
+
Input Range
+
+
STOPA
13.5V
Crossover
Notch
Reduction
TSET
3
ZCDA
16
Interleave
Control
ZCA
Phase B
On Time Control
ZCB
1
+
1.68V/1V
VREF
150mV
+
6V
15
+
4.87V
EN
+
2
Burst Operation
(UCC28060 only) STOPB
Brownout
HVSEN OV
UV
EN
OV (UCC28061 only)
UV
VSENSE
PGND
13.5V
+
1.68V/1V
ZCDB
Phase A
On Time Control
gm
+
4.95V
96ms
1.25V
1.1V (HIGH-LINE
UCC28060 only)
0.8V (LOW-LINE)
+
2.5V
SinglePhase
EN
36mA
Phase Fail
Detector
6.45V
+
+
OV
Phase
OK
300nA
5
4
6
9
COMP
PHB
AGND
PWMCNTL
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TYPICAL CHARACTERISTICS
At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 5 V, RTSET = 133 kΩ; all voltages
are with respect to GND, all outputs unloaded, TJ = TA = +25°C, and currents are positive into and negative out of the
specified terminal, unless otherwise noted.
BIAS SUPPLY CURRENT
vs
BIAS SUPPLY VOLTAGE
BIAS SUPPLY CURRENT
vs
TEMPERATURE
5.5
6.0
5.0
5.8
4.5
IVCC - Bias Supply Current - mA
IVCC - Bias Supply Current - mA
Operating
4.0
3.5
3.0
2.5
VCC Turn-Off
VCC Turn-On
2.0
1.5
1.0
5.6
5.4
5.2
5.0
4.8
4.6
4.4
4.2
0.5
4.0
0
0
2
4
6
8
10
12
14
16
18
20
-40
-20
0
20
40
60
80
100
120
TJ - Temperature - °C
VVCC - Bias Supply Voltage - V
Figure 1.
Figure 2.
BIAS SUPPLY CURRENT
vs
TEMPERATURE
ERROR AMPLIFIER TRANSFER FUNCTION
40
140
20
Transconductance 96 mS
0
ICOMP - Output Current - mA
IVCC - Bias Supply Current - mA
120
100
80
60
40
20
-20
Input Regulation Voltage
0 mA at 6.0 V
-40
-60
-80
COMP Offset Enable
165 mV Down from
Regulation Voltage
-100
-120
-140
-160
Disabled
Source Current Overdriven -160 mA
0
-180
-40
-20
0
20
40
60
80
100
120
5.5
TJ - Temperature - °C
5.6 5.7 5.8 5.9 6.0 6.1 6.2 6.3 6.4
6.5
VVSENSE - Input Voltage - V
Figure 4.
Figure 3.
10
Sink Current
25 mA
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TYPICAL CHARACTERISTICS (continued)
At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 5 V, RTSET = 133 kΩ; all voltages
are with respect to GND, all outputs unloaded, TJ = TA = +25°C, and currents are positive into and negative out of the
specified terminal, unless otherwise noted.
ERROR AMPLIFIER TRANSCONDUCTANCE
vs
TEMPERATURE
ERROR AMPLIFIER OUTPUT CURRENT
vs
OUTPUT VOLTAGE
11
110
5.94 V < VSENSE < 6.06 V
10
9
ICOMP - Output Current - mA
gm - Transconductance - ms
105
100
95
90
8
7
6
5
4
3
2
85
1
VSENSE = 6.1 V
80
0
-40
-20
0
20
40
60
80
100
120
0
1
TJ - Temperature - °C
Figure 5.
ERROR AMPLIFIER INPUT BIAS CURRENT
vs
INPUT VOLTAGE
3
4
5
CURRENT SENSE INPUT BIAS CURRENT
vs
TEMPERATURE
150
ICS - Current Sense Input Bias Current - mA
440
400
IVSENSE - Input BiasCurrent - nA
2
VCOMP - Output Voltage - V
Figure 6.
360
320
280
240
200
160
120
80
40
145
140
135
130
125
0
0
0.6 1.2 1.8 2.4 3.0 3.6 4.2 4.8 5.4
6.0
-40
VVSENSE - Input Voltage - V
Figure 7.
-20
0
20
40
60
80
100
120
TJ - Temperature - °C
Figure 8.
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TYPICAL CHARACTERISTICS (continued)
At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 5 V, RTSET = 133 kΩ; all voltages
are with respect to GND, all outputs unloaded, TJ = TA = +25°C, and currents are positive into and negative out of the
specified terminal, unless otherwise noted.
ZERO CURRENT DETECT CLAMP CURRENT
vs
HIGH INPUT VOLTAGE
ZERO CURRENT DETECT CLAMP CURRENT
vs
LOW INPUT VOLTAGE
5
0
-0.5
IZCD - Clamp Current - mA
IZCD - Clamp Current - mA
4
3
2
-1.0
-1.5
-2.0
-2.5
1
-3.0
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
-3.5
-0.4
4.0
-0.3
-0.2 -0.1
VZCD - Input Voltage - V
0
0.1
0.2
0.3
0.4
VZCD - Input Voltage - V
Figure 10.
Figure 9.
BROWNOUT FILTER DELAY TIME
vs
TEMPERATURE
RANGE CHANGE FILTER DELAY TIME
vs
TEMPERATURE
500
30
490
29
Range Charge Filter Delay Time - ms
Brownout Filter Delay Time - ms
480
470
460
450
440
430
420
410
400
390
380
370
28
27
26
25
24
23
22
21
360
350
20
-40
-20
0
20
40
60
80
100
120
-40
TJ - Temperature - °C
0
20
40
60
80
100
120
TJ - Temperature - °C
Figure 11.
12
-20
Figure 12.
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TYPICAL CHARACTERISTICS (continued)
At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 5 V, RTSET = 133 kΩ; all voltages
are with respect to GND, all outputs unloaded, TJ = TA = +25°C, and currents are positive into and negative out of the
specified terminal, unless otherwise noted.
GATE DRIVE RISING
vs
TIME
GATE DRIVE FALLING
vs
TIME
10
2.0
GD Voltage:
VCC = 20 V
VCC = 12 V
8
GD Source Current:
VCC = 20 V
VCC = 12 V
1.0
10
1.0
4
0.5
2
0
2
0
0
-0.5
0
-1.0
-2
50
100
150
200
250
300
350
GD Voltage:
VCC = 20 V
VCC = 12 V
-0.5
-1.0
0
20
40
Time - ns
Figure 13.
60
80
100
120
140
Time - ns
Figure 14.
GATE DRIVE RISING
vs
TIME AND DELAY FROM ZCD INPUT
GATE DRIVE FALLING
vs
TIME AND DELAY FROM CS INPUT
7
500
14
14
CLOAD = 4.7 nF
CLOAD = 4.7 nF
5
GD Output:
TJ = -40°C
TJ = +25°C
TJ = +125°C
4
3
12
400
12
10
300
10
200
8
8
6
2
4
1
2
0
0
Gate Drive Output - V
Current Sense Input - mV
6
ZCD Input - V
1.5
6
0.5
0
2.0
GD Sink Current:
VCC = 20 V
VCC = 12 V
8
4
-2
2.5
100
CS Input
Voltage
6
GD Output:
TJ = -40°C
TJ = +25°C
TJ = +125°C
0
4
-100
2
-200
0
Gate Drive Output - V
6
1.5
3.0
VCC = 20 V and 12 V
CLOAD = 4.7 nF
12
2.5
Gate Drive Source Current - A
Gate Drive Output - V
12
Gate Drive Output - V
14
3.0
VCC = 20 V and 12 V
CLOAD = 4.7 nF
Gate Drive Source Current - A
14
ZCD Input Voltage
-300
-1
-2
-25 0
50
100
150
200
250
300
-2
-25 0
Time - ns
Figure 15.
50
100
150
200
250
300
Time - ns
Figure 16.
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TYPICAL CHARACTERISTICS (continued)
At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 5 V, RTSET = 133 kΩ; all voltages
are with respect to GND, all outputs unloaded, TJ = TA = +25°C, and currents are positive into and negative out of the
specified terminal, unless otherwise noted.
GATE DRIVE OUTPUT HIGH
vs
VCC
GATE DRIVE OUTPUT IN UVLO
vs
SINK CURRENT
2.5
15
RLOAD = 2.7 kW
TJ = -40°C
2.0
13
TJ = +25°C
TJ = +125°C
12
11
10
Gate Drive Voltage - V
Gate Drive Voltage - V
14
TJ = -40°C
1.5
TJ = +25°C
1.0
TJ = +125°C
0.5
9
0
8
10
11
13
14
15
16
17
18
19
0
20
1
2
3
4
5
6
7
8
VVCC - Bias Supply Voltage - V
Figure 17.
Gate Drive Sink Current - mA
Figure 18.
GATE DRIVE HIGH VOLTAGE
vs
TEMPERATURE
ON-TIME FACTOR
vs
TIME SETTING RESISTOR
15
10
14
9
13
9
10
8
Clamped VCC ³ 15 V
KT - On-Time Factor - ms/V
Gate Drive Voltage - V
12
12
11
Unclamped VCC = 12 V
10
9
8
KTL
7
6
5
4
(UCC28060 only)
3
KTH
2
7
1
6
RLOAD = 2 kW
0
5
-40
-20
0
20
40
60
60
100
120
60
80 100 120 140 160 180 200 220 240 260 280
RTSET - Time Setting Resistor - kW
TJ - Temperature - °C
Figure 19.
14
Figure 20.
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TYPICAL CHARACTERISTICS (continued)
At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 5 V, RTSET = 133 kΩ; all voltages
are with respect to GND, all outputs unloaded, TJ = TA = +25°C, and currents are positive into and negative out of the
specified terminal, unless otherwise noted.
ON-TIME FACTOR PHASE A AND B, LOW RANGE
vs
TEMPERATURE
ON-TIME FACTOR PHASE A AND B, HIGH RANGE
vs
TEMPERATURE
3.0
RTSET = 266 kW
9
8
2.5
KTH - On-Time Factor - ms/V
KTL - On-Time Factor - ms/V
RTSET = 266 kW
7
6
5
RTSET = 133 kW
4
3
2
RTSET = 66 kW
2.0
1.5
RTSET = 133 kW
1.0
RTSET = 66 kW
0.5
1
0
0
-40
0
-20
20
40
60
80
100
120
-40
-20
0
40
60
80
20
TJ - Temperature - °C
Figure 22.
TJ - Temperature - °C
Figure 21.
ON-TIME FACTOR
vs
PHASE SHIFT
100
120
100
120
PWM RESTART TIME
vs
TEMPERATURE
300
110
GDA
108
RTSET = 266 kW
GDB
275
RTSET = 133 kW
106
KT/KT0 - %
PWM Restart Time - ms
250
104
RTSET = 66 kW
102
100
98
96
225
200
175
150
94
2(KTA ´ KTB)
KT0 =
92
125
KTA + KTB
100
90
150
160
170
180
190
200
210
-40
Phase Shift of GDA Relative to GDB - Degrees
Figure 23.
-20
0
20
40
60
80
TJ - Temperature - °C
Figure 24.
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TYPICAL CHARACTERISTICS (continued)
At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 5 V, RTSET = 133 kΩ; all voltages
are with respect to GND, all outputs unloaded, TJ = TA = +25°C, and currents are positive into and negative out of the
specified terminal, unless otherwise noted.
ADDITIONAL ON-TIME
vs
VINAC ZERO-CROSSING DISTORTION CORRECTION
100
RTSET = 266 kW
Additional On-Time - ms
RTSET = 133 kW
RTSET = 66 kW
10
1
0.1
0
0.5
1.0
1.5
2.0
2.5
3.0
VVINAC - Input AC Voltage Sense - V
Figure 25.
16
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APPLICATION INFORMATION
Theory of Operation
The UCC28060 contains the control circuits for two boost pulse-width modulation (PWM) power converters. The
boost PWM power converters ramp current in the boost inductors for a time period proportional to the voltage on
the error amplifier output. Each power converter then turns off the power MOSFET until current in the boost
inductor decays to 0, as sensed on the zero current detection inputs (ZCDA and ZCDB). Once the inductor
current decays to 0, the power converter starts another cycle. This on/off cycling produces a triangle wave of
current, with peak current set by the on-time and power mains input voltage, as shown in Equation 1.
VINAC (t) ´ TON
IPEAK (t) =
L
(1)
The average line current is exactly equal to half of the peak line current, as shown in Equation 2.
VINAC (t) ´ TON
IAVG (t) =
2´L
(2)
With TON and L being essentially constant during an ac line period, the resulting triangular current waveform
during each switching cycle has an average value proportional to the instantaneous value of the rectified ac line
voltage. This architecture results in a resistive input impedance characteristic at the line frequency and a
near-unity power factor.
The outputs of the two PWMs operate 180° out-of-phase so that power-line ripple current for the two PWMs is
greatly reduced from the ripple current of each individual PWM. This design reduces ripple current at the input
and output, allowing the reduction in size and cost of input and output filters.
Optimal phase balance occurs if the individual power stages and the on-times are well-matched. Mismatches in
inductor values do not affect the phase relationship.
On-Time Control, Maximum Frequency Limiting, and Restart Timer
Gate drive on-time varies with the error amplifier output voltage by a factor called KT, as shown in Equation 3.
TON = KT (VCOMP - 125 mV)
(3)
Where:
VCOMP is the output of the error amplifier, and 125 mV is a modulator offset.
To compensate for the effects of line voltage changes on loop gain, KT is three times larger in low-line range than
in high-line range, as shown in Equation 4.
KTL = 3 ´ KTH
(4)
To provide smooth transition between two-phase and single-phase operation, KT increases by a factor of two in
single-phase mode:
• KTHS = 2 × KTH; active in high-line range and single-phase operation
• KTLS = 2 × KTL; active in low-line range and single-phase operation
The clamped maximum output of the error amplifier is limited to 4.95 V. This value, less the 125 mV modulator
offset, limits on-time to Equation 5.
TON(max) = KT ´ 4.825 V
(5)
This on-time limit sets the maximum power that can be delivered by the converter at a given input voltage level.
The switching frequency of each phase is limited by minimum period timers. If the current decays to 0 before the
minimum period timer elapses, turn-on is delayed, resulting in discontinuous phase current.
The restart timer ensures starting under all circumstances by restarting both phases if either phase ZCD input
has not transitioned high-to-low for approximately 200 µs. To prevent the circuit from operating in continuous
conduction mode (CCM), the restart time does not trigger turn-on until both phase currents return to 0.
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The on-time factors (KTH, KTHS, KTL, KTLS) and the minimum switching period TMIN are proportional to the time
setting resistor RTSET, the resistor from the TSET pin to ground, and they can be calculated by Equation 6
through Equation 8:
ms
RTSET
KTH =
; Active in High-Line Range (UCC28060 only)
´ 1.35
V
133 kW
(6)
ms
RTSET
KTL =
; Active in Low-Line Range
´ 4.0
V
133 kW
(7)
RTSET
TMIN =
´ 2.2ms; Minimum Switching Period
133 kW
(8)
The proper value of RTSET results in the clamped maximum on-time, TON(max), required by the converter operating
at the minimum input line and maximum load.
Natural Interleaving
Under normal operating conditions, the UCC28060 regulates the relative phasing of the channel A and channel B
inductor currents to be very close to 180°, minimizing the ripple currents seen at the line source and output
capacitor. The phase control function differentially modulates the on-times of the A and B channels based on the
phase and frequency relationship. This natural interleaving method allows the converter to achieve 180° phase
shift and transition mode operation for both phases without the requirements on boost inductor tolerance. As a
result, the current sharing of the A and B channels are proportional to the inductor tolerance. The best current
sharing is achieved when both inductors are exactly the same value.
Easy Phase Management
At light load conditions, because of the small conduction losses resulting from small load current and large
switching losses caused by the discharging of the MOSFET junction capacitors, shutting down one of the power
stages reduces switching loss and increases conduction loss. At certain power levels, the reduction of switching
losses is greater than the increase in conduction losses; better efficiency can be realized. This feature is one of
the major benefits of interleaved power factor correction (PFC) and it is especially valuable for meeting light-load
efficient standards design requirements.
The easy phase management function allows the user to shut down one of the power stages to achieve higher
efficiency at light load conditions by connecting the COMP pin to the PHB pin. Based on theoretical analysis and
experimental results, the UCC28060 preset phase management thresholds can achieve maximum efficiency
improvement. According to the COMP pin voltage, easy phase management shuts down phase B at
corresponding power levels. The thresholds and corresponding power levels are listed in Table 1.
Table 1. PHB Management Performance with PHB Connected to COMP
PHB THRESHOLDS
PHB THRESHOLD VOLTAGE
VACRMS
COMP VOLTAGE AT
FULL POWER
HIGH TO LOW
85
4.85 V
115
133
PERCENTAGE OF FULL POWER
LOW TO HIGH
HIGH TO LOW
(PHASE B OFF)
LOW TO HIGH
(PHASE B ON)
0.8 V
1.0 V
14%
19%
2.7 V
0.8 V
1.0 V
26%
34%
2.1 V
0.8 V
1.0 V
35%
45%
187
3.1 V
1.1 V
1.3 V
33%
40%
230
2.1 V
1.1 V
1.3 V
50%
61%
265
1.6 V
1.1 V
1.3 V
67%
81%
The PHB pin can also be driven by an external logic signal to allow customized phase management. To disable
phase management, connect the PHB pin to the VREF pin.
18
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Zero Crossing Detection and Valley Switching
In transition-mode PFC circuits, the MOSFET turns on when the boost inductor current crosses 0. Because of the
resonance between the boost inductor and the parasitic capacitor at the MOSFET drain node, part of the energy
stored in the MOSFET junction capacitor can be recovered, reducing switching losses. Furthermore, when the
rectified input voltage is less than half of the output voltage, all the energy stored in the MOSFET junction
capacitor can be recovered and zero-voltage switching (ZVS) can be realized. By adding an appropriate delay,
the MOSFET can be turned on at the valley of its resonating drain voltage (valley switching). In this way, the
energy recovery can be maximized and switching loss is minimized.
The RC time constant is generally derived empirically, but a good starting point is a value equal to 25% of the
resonant period of the drain circuit. The delay can be realized by a simple RC filter, as shown in Figure 26.
Because the ZCD pin is internally clamped, a more accurate delay can also be realized by using Figure 27.
R
R1
ZCD
ZCD
CT
C
CT
Figure 26. Simple RC Delay Circuit
C
R2
Figure 27. More Accurate Time Delay Circuit
Brownout Protection
As the power line RMS voltage decreases, RMS input current increases to maintain the output voltage constant
for a specific load. Brownout protection prevents the RMS input current from exceeding a safe operating level.
Power line RMS voltage is sensed at VINAC. When the voltage applied to VINAC fails to exceed the brownout
threshold for the brownout filter time, a brownout condition is detected and both gate drive outputs immediately
pull low. During brownout, COMP is actively pulled low. Gate drive outputs remain low until the voltage on VINAC
rises above the brownout threshold. After a brownout, the power stage soft-starts as COMP rises.
The brownout detection threshold and its hysteresis are set by the voltage divider ratio and resistor values. This
pin also detects the input line range to set the corresponding on-time factors. Both the brownout protection and
line range detection are based on VINAC peak voltage; the threshold and hysteresis are also based on line peak
voltage. The peak VINAC voltage can be easily translated into RMS value. Suggested resistor values for the
voltage divider are 3 MΩ ±1% from the rectified input voltage to VINAC and 46.4 kΩ ±1% from VINAC to ground.
These resistors set the typical thresholds for RMS line voltages, as shown in Table 2.
Table 2. Brownout and Range Change Thresholds
THRESHOLD
BROWNOUT (RMS)
MAINS SELECT (RMS)
Falling
65 V
150.9 V
Rising
79.8 V
161.2 V
Failsafe OVP—Output Over-Voltage Protection
FailSafe OVP prevents any single failure from allowing the output to boost above safe levels. Redundant paths
for output voltage sensing provide additional protection against output over-voltage. Over-voltage protection is
implemented through two independent paths: VSENSE and HVSEN. The converter shuts down if either input
senses an over-voltage condition. The output voltage can still maintain a safe level with either loop failure. The
device is re-enabled when both sense inputs fall back into the normal range. At that time, the gate drive outputs
resume switching under PWM control. Output over-voltage does not cause soft-start and the COMP pin is not
discharged during an output over-voltage event.
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Over-Current Protection
Under certain conditions (such as inrush, brownout recovery, and output overload), the PFC power stage sees
large currents. It is critical that the power devices be protected from switching during these conditions.
The conventional current sensing method uses a shunt resistor in series with the MOSFET source to sense the
converter current, resulting in multiple ground points and high power dissipation. Furthermore, since no current
information is available when the MOSFETs are off, the source resistor current sensing method requires
repeated turn-ons of the MOSFETs during over-current conditions. As a result, the converter may temporarily
operate in continuous current mode (CCM) and experience failures induced by excessive reverse recovery
currents in the boost diode.
The UCC28060 uses a single resistor to continuously sense the total inductor (input) current. This way, turn-on of
the MOSFETs is completely avoided when the inductor currents are excessive. The drive to the MOSFETs is
inhibited until total inductor current drops to near zero, precluding reverse recovery induced failures (these
failures are most likely to occur when the ac line recovers from a brownout condition).
Following an over-current condition, both MOSFETs are turned on in phase when the input current drops to near
0. Because two phase currents are temporarily operating in phase, set the over-current protection threshold to
more than twice of each phase maximum current ripple value in order to allow a return to normal operation after
an over-current event.
Phase Fail Protection
The UCC28060 detects failure of one phase by monitoring the sequence of ZCD pulses. During normal
two-phase operation, if one ZCD input remains idle for longer than approximately 14 ms while the other ZCD
input switches normally, PWMCNTL goes high, indicating that the power stage is not operating correctly. During
normal single-phase operation, phase failure is not monitored.
Distortion Reduction
Because of the resonance between the capacitance present across the drain-source of the switching MOSFET
and the boost inductor, conventional transition mode power factor correction circuits may not be able to absorb
power from the input line when the input voltage is around 0 V. This limitation results in waveform distortion and
increased harmonic distortion. To reduce line current distortion to the lowest possible level, the UCC28060
increases switching MOSFET on-time when input voltage is around 0 V to increase the power absorption and
compensate for this effect.
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Improved Error Amplifier
The voltage error amplifier is a transconductance amplifier. Voltage loop compensation is connected from the
error amplifier output, COMP, to analog ground, AGND. The recommended compensation network is shown in
Figure 28.
REF
COMP
+
VSENSE
CZ
CP
4.95 V
RZ
Figure 28. Typical Error Amplifier Compensation
To improve the transient response, the error amplifier output current is increased by 100 µA when the error amp
input is below 5.815 V, as shown in Figure 29. This increase allows faster charging of the compensation
components following sudden load current increases (also refer to Figure 4 in the Typical Characteristics).
160mA
OV
PWM
Shutdown
+
6.45V
+
5.75V
VSENSE
+g
6V
m
COMP
Soft Start
+
Brownout
UV
EN
OV
(UCC28061)
0.5V
R
Q
S
Q
Figure 29. Error Amplifier Block Diagram Showing Speed-Up and Latched Soft-Start
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Open-Loop Protection
If the feedback loop is disconnected from the device, a current source internal to the UCC28060 pulls the
VSENSE pin voltage towards ground. When VSENSE falls below 1.20 V, the device is disabled. When disabled,
supply current decreases, and both gate drive outputs and COMP are actively pulled low. The device is
re-enabled when VSENSE rises above 1.25 V. At that time, the gate drive outputs begin switching under PWM
control.
The device can be externally disabled by grounding the VSENSE pin with an open-drain or open-collector driver.
When disabled, device supply current drops and COMP is actively pulled low. When VSENSE is released, the
device soft-starts. This disable method forces the device into standby mode and minimizes its power
consumption. This feature is particularly useful when standby power is a key design aspect.
If the feedback loop is disconnected from ground, the VSENSE voltage goes high. When VSENSE rises above
the over-voltage protection threshold, both gate drive outputs go low, and COMP is actively pulled low. The
device is re-enabled when VSENSE falls back into range. At that time, the gate drive outputs begin switching
under PWM control. The VSENSE pin is internally clamped to protect the device from damage under this
condition.
Soft-Start
The PWM gradually ramps from zero on-time to normal on-time as the compensation capacitor from COMP to
AGND charges from a low level to the final value. This process implements a soft-start, with a time constant set
by the output current of the error amplifier and the value of the compensation capacitors. In the event of a
brownout, logic disable, or VCC undervoltage fault, COMP is actively pulled low so the PWM soft-starts after this
event is cleared. Even if a fault event happens very briefly, soft-start fully discharges the compensation
components before resuming operation, ensuring soft-starting. See Figure 29 for details.
Light-Load Operation
As load current decreases, the error amplifier commands less input current by lowering the COMP voltage. If
PHB (normally connected to COMP) falls below 0.8 V at low input line (or 1.1 V at high input line), channel B
stops switching and channel A on-time doubles to compensate. If COMP falls below 150 mV, channel A also
stops switching and the loop enters a hysteretic control mode. The PWM skips cycles to maintain regulation.
Command for the Downstream Converter
In the UCC28060, the PWMCNTL pin is used to coordinate the PFC stage with a downstream converter.
Through the HVSEN pin, the output voltage is sensed. When the output voltage is within the desired range, the
PWMCNTL pin is pulled to ground internally and can be used to enable a downstream converter. The enable
threshold and hysteresis can be adjusted independently through the voltage divider ratio and resistor values. The
HVSEN pin is also used for the FailSafe over-voltage protection. When designing the voltage divider, make sure
this FailSafe over-voltage protection level is set above normal operating levels.
VCC Undervoltage Protection
VCC must rise above the undervoltage threshold for the PWM to begin functioning. If VCC drops below the
threshold during operation, both gate drive outputs and COMP are actively pulled low. VCC must rise above the
threshold for PWM function to restart.
VCC
VCC is connected to a bias supply of between 13 V and 21 V. When powered from a poorly-regulated supply, an
external zener diode is recommended to prevent excessive current into VCC.
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DESIGN EXAMPLE
An example of the UCC28060 PFC controller in a two-phase transition mode interleaved PFC pre-regulator is
shown in Figure 30.
F1
Bridge
-
D3
+
CIN
CF4
22 pF
12 V
L1
D1
CA
2.2 mF
R
1W
RZA
20 kW
VCC
RG1
5W
ZCDA
CS
CF1
1 nF
VOUT
Q1
GDA
CF5
22 pF
UCC28060
RZB
COMP
L2
ZCDB
RC
PWMCNTL
D2
PHB
RZ
RLOAD
20 kW
RP
TSET
12 V
PWMCNTL
50 kW
VREF
COUT
RA
RG2
5W
VINAC
GDB
Q2
VSENSE
HVSEN
RS
CZ
CP
RT
CB
2.2 mF
AGND
RF
PGND
CF2
1.2 nF
RB
CF3
1.2 nF
RD
CF4
1.2 nF
RE
Figure 30. Typical Transition Mode Interleaved PFC Pre-Regulator
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Design Goals
The specifications for this design were chosen based on the power requirements of a 300 W LCD TV. These
specifications are shown in Table 3.
Table 3. Design Specifications
PARAMETER
VIN
RMS input voltage
VOUT
Output voltage
fLINE
Line frequency
PF
Power factor at maximum load
MIN
Full load efficiency
fMIN
Minimum switching frequency
MAX
UNIT
265 (VIN_MAX)
VRMS
390
47
V
63
Hz
300
W
0.90
POUT
η
TYP
85 (VIN_MIN)
0.92
45
kHz
Recommended PCB Device Layout
Interleaved transition-mode PFC system architecture dramatically reduces input and output ripple current,
allowing the circuit to use smaller and less expensive filters. To maximize the benefits of interleaving, the input
and output filter capacitors should be located after the two phase currents are combined together. Similar to
other power management devices, when laying out the printed circuit board (PCB) it is important to use star
grounding techniques and keep filter capacitors as close to device ground as possible. To minimize the
interference caused by capacitive coupling from the boost inductor, the device should be located at least 1 in
(25.4 mm) away from the boost inductor. It is also recommended that the device not be placed underneath
magnetic elements. Because of the precise timing requirement, the timing setting resistor RT should be put as
close as possible to the TSET pin and returned to the analog ground. See Figure 31 for a recommended
component layout and placement.
24
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VOUT
+
-
RS
RG1
R
RP
CA
CF1
RG2
CB
CF2
RF
CF4
CP
RT
CF3
RD
RC
RZB
RB
U1
RA
RE
RZA
VCC
CZ
VOUT
RZ
VOUT
Figure 31. Recommended PCB Layout
Inductor Selection
The boost inductor is selected based on the inductor ripple current requirements at the peak of low line.
Selecting the inductor requires calculating the boost converter duty cycle at the peak of low line (DPEAK_LOW_LINE),
as shown in Equation 9.
VOUT - VIN_MIN Ö2
390 V - 85 V Ö2
DPEAK_LOW_LINE =
=
» 0.69
VOUT
390 V
(9)
The minimum switching frequency of the converter (fMIN) occurs at the peak of low line and is set between 25
kHz and 50 kHz to avoid audible noise. For this design example, fMIN was set to 45 kHz:
h ´ VIN_MIN2 x DPEAK_LOW_LINE
0.92(85 V)2 0.69
L1 = L2 =
=
» 340 mH
POUT ´ fMIN
300 W ´ 45 kHz
(10)
The inductor for this design would have a peak current (ILPEAK) of 5.4 A, as shown in Equation 11, and an RMS
current (ILRMS) of 2.2 A, as shown in Equation 12.
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ILPEAK =
ILRMS =
POUT Ö2
300 W Ö2
VIN_MIN ´ h
ILPEAK
=
Ö6
=
85 V ´ 0.92
» 5.4 A
(11)
5.4 A
» 2.2 A
Ö6
(12)
This converter uses constant on-time (TON) and zero-current switching (ZCS) to set up the converter timing.
Auxiliary windings off of L1 and L2 detect when the inductor currents are 0. Selecting the turns ratio in
Equation 13 ensures that there is at least 2 V at the peak of high line to reset the ZCD comparator after every
switching cycle.
The turns-ratio of each auxiliary winding is:
VOUT - VIN_MAX Ö2
NP
390 V - 265 V Ö2
=
=
»8
2V
2V
NS
(13)
ZCD Resistor Selection (RZA, RZB)
The minimum value of the ZCD resistors is selected based on the internal zener clamp maximum current rating
of 3 mA, as shown in Equation 14.
VOUT NS
390 V
RZA = RZB ³
=
» 16.3 kW
NP ´ 3 mA
8 ´ 3 mA
(14)
In this design the ZCD resistors were set to 20 kΩ, as shown in Equation 15.
RZA = RZB = 20 kW
(15)
HVSENSE
The HVSENSE pin programs the PWMCNTL output of the UCC28060. The PWMCNTL open-drain output can be
used to disable a downstream converter while the PFC output capacitor is charging. PWMCNTL starts in high
impedance and pulls to ground when the HVSENSE increases above 2.5 V. Setting the point where PWMCNTL
becomes active requires a voltage divider from the boost voltage to the HVSEN pin to ground. Equation 16 to
Equation 20 show how to set the PWMCNTL pin to activate when the output voltage is within 90% of its nominal
value.
VOUT_OK = VOUT ´ 0.90 » 351 V
(16)
Resistor RE sets up the high side of the voltage divider and programs the hysteresis of the PWMCNTL signal.
For this example, RE was selected to provide 108 V of hysteresis, as shown in Equation 17.
Hysteresis
108 V
RE =
=
= 3 MW
36 mA
36 mA
(17)
Resistor RF is used to program the PWMCNTL active threshold, as shown in Equation 18.
RF =
2.5 V
VOUT_OK - 2.5 V
RE
=
- 36 mA
2.5 V
= 31.185 kW » 31.6 kW
351 V - 2.5 V
- 36 mA
3 MW
(18)
This PWMCNTRL output remains active until a minimum output voltage (VOUT_MIN) is reached, as shown in
Equation 19.
2.5 V (RE + RF)
2.5 V (3 MW + 31.6 kW)
VOUT_MIN =
=
» 240 V
31.6 kW
RF
(19)
According to the resistor value, the FailSafe OVP threshold should be set according to Equation 20:
4.87 V (RE + RF) 4.87 V (3 MW + 31.6 kW)
VOV_FAILSAFE =
=
» 467 V
31.6 kW
RF
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Output Capacitor Selection
The output capacitor (COUT) is selected based on holdup requirements as shown in Equation 21.
POUT
1
300 W 1
2 h
2
fLINE
0.92 47 Hz
COUT ³
=
» 147 mF
2
2
2
2
VOUT - (VOUT_MIN)
(390 V) - (240 V)
(21)
Two 100-µF capacitors were used in parallel for the output capacitor:
COUT = 200 mF
(22)
For this size capacitor, the output voltage ripple (VRIPPLE) is approximately 11 V, as shown in Equation 23:
VRIPPLE =
2 ´ POUT
1
2 ´ 300W
=
» 14V
h
VOUT ´ 4p ´ fLINE ´ COUT 0.92 ´ 390V ´ 4p ´ 47Hz ´ 200 m F
(23)
In addition to hold-up requirements, a capacitor must be selected so that it can withstand the low-frequency RMS
current (ICOUT_100 Hz) and the high-frequency RMS current (ICOUT_HF); see Equation 24 to Equation 26.
High-voltage electrolytic capacitors generally have both a low- and a high-frequency RMS current rating on the
product data sheets.
POUT
300 W
ICOUT_100Hz =
=
= 0.591 A
390 V ´ 0.92 ´ Ö2
VOUT ´ h ´ Ö2
(24)
2
ICOUT_HF =
POUT 2 Ö2
4 Ö2 VIN_MIN
2 ´ h ´ VIN_MIN
9p VOUT
- (ICOUT_100 Hz)2
(25)
2
300 W ´ 2 Ö2
2 ´ 0.92 ´ 85 V
ICOUT_HF =
4 Ö2 ´ 85 V
9p ´ 390 V
- (0.591 A)2
» 0.966 A
(26)
Selecting an RS for Peak Current Limiting
The UCC28060 peak limit comparator senses the total input current and is used to protect the MOSFETs during
inrush and over-load conditions. For reliability, the peak current limit (IPEAK) threshold in this design is set for
120% of the nominal inrush current that is observed during power-up, as shown in Equation 27.
2POUT Ö2 (1.2)
2 ´ 300 W Ö2 ´ 1.2
=
IPEAK =
» 13 A
h ´ VIN_MIN
0.92 ´ 85 V
(27)
A standard 15-mΩ metal-film current-sense resistor is used for current sensing, as shown in Equation 28. The
estimated power loss of the current sense resistor (PRS) is less than 0.25 W during normal operation, as shown
in Equation 29.
200 mV
200 mV
RS =
=
» 15 mW
IPEAK
13 A
(28)
PRS =
POUT
VIN_MIN ´ h
2
2
RS =
300 W
85 V ´ 0.92
´ 15 mW » 0.22 W
(29)
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The most critical parameter in selecting a current-sense resistor is the surge rating. The resistor needs to
withstand a short-circuit current larger than the current required to open the fuse (F1). I2t (ampere squared
seconds) is a measure of thermal energy resulting from current flow required to melt the fuse, where I2t is equal
to RMS current squared times the duration of the current flow in seconds. A 4-A fuse with an I2t of 14 A2s was
chosen to protect the design from a short-circuit condition. To ensure the current-sense resistors have a high
enough surge protection, a 15-MΩ, 500-mW, metal-strip resistor was chosen for the design. The resistor has a
2.5-W surge rating for 5 seconds. This result translates into 833 A2s and has a high enough I2t rating to survive a
short-circuit before the fuse opens, as described in Equation 30.
2.5 W
I2t =
´ 5 s = 833 A2s
0.015 W
(30)
Power Semiconductor Selection (Q1, Q2, D1, D2):
The selection of Q1, Q2, D1, and D2 are based on the power requirements of the design. Application note
SLUU138, UCC38050 100-W Critical Conduction Power Factor Corrected (PFC) Pre-Regulator, explains how to
select power semiconductor components for transition-mode PFC pre-regulators.
The MOSFET maximum-pulsed drain current (Q1, Q2) is shown in Equation 31:
IDM ³ IPEAK = 13 A
(31)
The MOSFET RMS current calculation (Q1, Q2) is shown in Equation 32:
IDS =
IPEAK
2
4 Ö2 VIN_MIN
13 A
1
=
6
2
9p ´ VOUT
4 Ö2 ´ 85 V
1
6
9p ´ 390 V
» 2.3 A
(32)
To meet the power requirements of the design, IRFB11N50N 500-V MOSFETs from International Rectifier were
chosen for Q1 and Q2.
The boost diode RMS current (D1, D2) is shown in Equation 33:
ID =
IPEAK
4 Ö2 VIN_MIN
2
9p ´ VOUT
=
13 A
2
4 Ö2 ´ 85 V
9p ´ 390 V
» 1.4 A
(33)
To meet the power requirements of the design, MURS306T3 600-V diodes from On Semiconductor were chosen
for the design for D1 and D2.
Brownout Protection
Resistor RA and RB are selected to activate brownout protection at 75% of the specified minimum operated input
voltage. Resistor RA programs the brownout hysteresis comparator, which was selected to provide 21 V of
hysteresis. RA and RB are shown in Equation 34 and Equation 35.
In this design example, brownout becomes active when the input drops below 64 VRMS and deactivates when the
input reaches 79 VRMS.
Hysteresis
21 V
RA =
=
» 3 MW
7 mA
7 mA
(34)
1.4 V ´ RA
1.4 V ´ 3 MW
RB =
=
» 47 kW
85 V ´ 0.75 Ö2 - 1.4 V
VIN_MIN ´ 0.75 Ö2 - 1.4 V
(35)
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Converter Timing
Select the timing resistor, RTSET, for the correct on-time (TON) based on KTL, as shown in Equation 36. To ensure
proper operation, the timing must be set based on the highest boost inductance (L1MAX). In this design example,
the boost inductor could be as high as 390 µH, based on line and load conditions, as shown in Equation 37.
h ´ (VIN_MIN)2 1 fMIN =
VIN_MIN ´ Ö2
0.92 ´ (85 V)2 1 -
VOUT
=
POUT ´ L1MAX
133 kW 1 RTSET =
300 W ´ 390 mH
VIN_MIN ´ Ö2
133 kW 1 -
VOUT
4.85 V ´ 4 ms ´ fMIN
=
85 V ´ Ö2
390 V
85 V ´ Ö2
390 V
4.85 V ´ 4 ms ´ 39.2 kHz
= 39.2 kHz
(36)
» 121 kW
(37)
This result sets the maximum frequency clamp (fMAX), as shown in Equation 38, which improves efficiency at light
load.
133 kW
133 kW
fMAX =
» 550 kHz
=
2 ms ´ R T
2 ms ´ 121 kW
(38)
Programming VOUT
Resistor RC is selected to minimize error because of VSENSE input bias current and minimize loading on the
power line when the PFC is disabled. Construct resistor RC from two or more resistors in series to meet
high-voltage requirements. RC was also selected to be of a similar value of RA and RE to simplify the bill of
materials and reduce design costs.
Based on the resistor values shown in Equation 39 to Equation 41, the primary output over-voltage protection
threshold should be as shown in Equation 42:
RC = 3 MW
(39)
VREF = 6 V
RD =
(40)
VREF ´ RC
(VOUT - VREF)
VOVP = 6.45 V
=
RC + RD
RD
6 V ´ 3 MW
» 47 kW
(390 V - 6V)
(41)
3 MW + 47 kW
= 6.45 V
= 418 V
47 kW
(42)
Loop Compensation
Resistor RZ is sized to attenuate low-frequency ripple to less than 2% of the voltage amplifier output range. This
value ensures good power factor and low input current harmonic distortion.
The transconductance amplifier gain is shown in Equation 43:
gm = 96 mS
(43)
The voltage divider feedback gain is shown in Equation 44 and Equation 45:
VREF
6V
H=
=
» 0.015
390 V
VOUT
(44)
100 mV
100 mV
RZ =
=
= 6.313 kW » 6.34 kW
11 V ´ 0.015 ´ 96 mS
VRIPPLE ´ H ´ gm
(45)
CZ is then set to add 45° of phase margin at 1/5th of the switching frequency, as shown in Equation 46:
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1
CZ =
2p ´
fLINE
5
=
´ RZ
1
47 Hz
2p ´
´ 6.34 kW
5
= 2.67 mF
(46)
CP is sized to attenuate high-frequency noise, as shown in Equation 47:
1
1
CP =
=
= 1.12 nF
fMIN
45 kHz
2p
´
´
6.34
k
W
2p ´
´ RZ
2
2
(47)
The standard values of Equation 48 and Equation 49 should be chosen for CZ and CP.
CZ = 2.2 mF
(48)
CP = 1 nF
(49)
ADDITIONAL REFERENCES
Related Parts
Table 4 lists several TI parts that have characteristics similar to the UCC28060.
Table 4. Related Parts
DEVICE
DESCRIPTION
UCC28051
PFC controller for low to medium power applications
UCC28019
8-pin continuous conduction mode (CCM) PFC controller
References
These references, design tools, and links to additional references, including design software, may be found at
www.power.ti.com:
• Evaluation Module, UCC28060EVM 300W interleaved PFC Pre-regulator, SLUU280 from Texas Instruments
• Application Note, UCC38050 100-W Critical Conduction Power Factor Corrected (PFC) Pre-regulator,
SLUU138 from Texas Instruments
Package Outline and Recommended PCB Footprint
The mechanical packages at the end of this data sheet outline the mechanical dimensions of the 16-pin D
(SOIC) package and provide recommendations for PCB layout.
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PACKAGE OPTION ADDENDUM
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11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
UCC28060D
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
UCC28060
UCC28060DG4
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
UCC28060
UCC28060DR
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
UCC28060
UCC28060DRG4
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
UCC28060
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
UCC28060DR
Package Package Pins
Type Drawing
SOIC
D
16
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
16.4
Pack Materials-Page 1
6.5
B0
(mm)
K0
(mm)
P1
(mm)
10.3
2.1
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
UCC28060DR
SOIC
D
16
2500
333.2
345.9
28.6
Pack Materials-Page 2
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