S4008V1C WCFS4008V1C 512K x 8 Static RAM Features • High speed — tAA = 12 ns • 2.0V Data Retention • Automatic power-down when deselected • TTL-compatible inputs and outputs • Easy memory expansion with CE and OE features Functional Description The WCFS4008V1C is a high-performance CMOS Static RAM organized as 524K words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and three-state drivers. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW). The WCFS4008V1C is available in standard 400-mil-wide 36-pin SOJ package and 44-pin TSOP II package with center power and ground pinout. Logic Block Diagram Pin Configuration SOJ Top View I/O0 INPUT BUFFER I/O1 ROW DECODER I/O2 512K x 8 ARRAY SENSE AMPS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 I/O4 I/O5 COLUMN DECODER CE POWER DOWN I/O6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 NC A18 A17 A16 A15 OE I/O7 I/O6 GND VCC I/O5 I/O4 A14 A13 A12 A11 A10 NC I/O7 NC NC A0 A1 A2 A3 A4 CE I/O0 I/O1 VCC VSS I/O2 I/O3 WE A5 A6 A7 A8 A9 NC NC 1 44 2 3 43 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 A 11 A 12 A 13 A14 A15 A16 A17 A18 WE OE I/O3 A0 A1 A2 A3 A4 CE I/O0 I/O1 VCC GND I/O2 I/O3 WE A5 A6 A7 A8 A9 TSOP II Top View Selection Guide WCFS4008V1C 12ns Maximum Access Time (ns) 12 Maximum Operating Current (mA) Comm’l 85 Maximum CMOS Standby Current (mA) Comm’l 10 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 NC NC NC A18 A17 A16 A15 OE I/O7 I/O6 VSS VCC I/O5 I/O4 A14 A13 A12 A11 A10 NC NC NC WCFS4008V1C DC Input Voltage[1] ................................ –0.5V to VCC + 0.5V Maximum Ratings Current into Outputs (LOW) ........................................ 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Operating Range Storage Temperature ................................–65×C to +150×C Ambient Temperature with Power Applied............................................–55×C to +125×C Range Ambient Temperature VCC Supply Voltage on VCC to Relative GND[1] .... –0.5V to +4.6V Commercial 0°C to +70°C 3.3V ± 0.3V DC Voltage Applied to Outputs in High Z State[1] ....................................–0.5V to VCC + 0.5V Electrical Characteristics Over the Operating Range Parameter Description Test Conditions WCFS4008V1C 12ns Min. VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage VIL Input LOW Voltage[1] Max. Unit 2.4 V 0.4 V 2.0 VCC + 0.3 V –0.3 0.8 V IIX Input Load Current GND < VI < VCC –1 +1 µA IOZ Output Leakage Current GND < VOUT < VCC, Output Disabled –1 +1 µA ICC VCC Operating Supply Current VCC = Max., f = fMAX = 1/tRC 85 mA ISB1 Automatic CE Power-Down Current —TTL Inputs Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX 40 mA ISB2 Automatic CE Power-Down Current —CMOS Inputs Max. VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 10 mA Comm’l Comm’ll Capacitance[2] Parameter Description CIN Input Capacitance COUT I/O Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.3V Note: 1. VIL (min.) = –2.0V for pulse durations of less than 20 ns 2. Tested initially and after any design or process changes that may affect these parameters. 2 Max. Unit 8 pF 8 pF WCFS4008V1C AC Test Loads and Waveforms R1 317 Ω 3.3V 50Ω VTH = 1.5V OUTPUT OUTPUT 5 pF R2 351Ω INCLUDING JIG AND SCOPE (a) Z0 =50Ω * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 30pF* (b) ALL INPUT PULSES 3.3V 90% GND 90% 10% 10% Fall time: > 1 V/ns Rise time > 1 V/ns (c) 3 WCFS4008V1C AC Switching Characteristics[3] Over the Operating Range WCFS4008V1C 12ns Parameter Description Min. Max. Unit READ CYCLE tpower[4] VCC(typical) to the first access 1 ns tRC Read Cycle Time 12 ns tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 12 ns tDOE OE LOW to Data Valid 6 ns tLZOE OE LOW to Low Z tHZOE OE HIGH to High Z[5, 6] tLZCE CE LOW to Low Z 12 3 ns 0 3 [5, 6] tHZCE CE HIGH to High Z tPU CE LOW to Power-Up tPD CE HIGH to Power-Down ns 6 [6] ns ns ns 6 ns 12 ns 0 ns WRITE CYCLE[7, 8] tWC Write Cycle Time 12 ns tSCE CE LOW to Write End 8 ns tAW Address Set-Up to Write End 8 ns tHA Address Hold from Write End 0 ns tSA Address Set-Up to Write Start 0 ns tPWE WE Pulse Width 8 ns tSD Data Set-Up to Write End 6 ns tHD Data Hold from Write End 0 ns 3 ns tLZWE tHZWE [6] WE HIGH to Low Z WE LOW to High Z [5, 6] 6 ns Notes: 3. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. 4. tPOWER gives the minimum amount of time that the power supply should be at stable, typical Vcc values until the first memory access can be performed. 5. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 8. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 4 WCFS4008V1C Switching Waveforms Read Cycle No. 1[9, 10] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[10, 11] ADDRESS tRC CE tACE OE tHZOE tDOE DATA OUT tHZCE tLZOE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT HIGH IMPEDANCE tPD tPU ICC 50% 50% ISB Notes: 9. Device is continuously selected. OE, CE = VIL. 10. WE is HIGH for read cycle. 11. Address valid prior to or coincident with CE transition LOW. 5 WCFS4008V1C Switching Waveforms (continued) Write Cycle No. 1(WE Controlled, OE HIGH During Write)[12, 13] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE OE tSD DATA I/O tHD DATAIN VALID NOTE 14 tHZOE Write Cycle No. 2 (WE Controlled, OE LOW)[13] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD NOTE 14 DATA I/O tHD DATA VALID tLZWE tHZWE Truth Table CE OE WE I/O0 – I/O7 Mode Power H X X High Z Power-Down Standby (ISB) L L H Data Out Read Active (ICC) L X L Data In Write Active (ICC) L H H High Z Selected, Outputs Disabled Active (ICC) Notes: 12. Data I/O is high-impedance if OE = VIH. 13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 14. During this period the I/Os are in the output state and input signals should not be applied. 6 WCFS4008V1C Ordering Information Speed (ns) 12 Ordering Code Package Name Package Type WCFS4008V1C-JC12 J 36-Lead (400-Mil) Molded SOJ WCFS4008V1C-TC12 T 44-pin TSOP II Package Diagrams 36-Lead (400-Mil) Molded SOJ J 7 Operating Range Commercial WCFS4008V1C Package Diagrams (continued) 44-Pin TSOP II T 8 WCFS4008V1C 512K x 8 Static RAM Revision History Document Title: WCFS4008V1C 32K x 8 3.3V Static RAM REV. ISSUE DATE ORIG. OF CHANGE ** 4/12/2002 XFL DESCRIPTION OF CHANGE New Datasheet