SCAS252A − OCTOBER 1993 − REVISED JULY 1995
D EPIC (Enhanced-Performance Implanted
D
D
D
D
D
D
DGG OR DL PACKAGE
(TOP VIEW)
CMOS) Submicron Process
Member of the Texas Instruments
Widebus Family
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
Flow-Through Architecture Optimizes
PCB Layout
Bus Hold on Data Inputs Eliminates
the Need for External Pullup/Pulldown
Resistors
Package Options Include Plastic Shrink
Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
OEA
LE1B
2B3
GND
2B2
2B1
VCC
A1
A2
A3
GND
A4
A5
A6
A7
A8
A9
GND
A10
A11
A12
VCC
1B1
1B2
GND
1B3
LE2B
SEL
description
The SN74ALVC16260 is a 12-bit to 24-bit
multiplexed D-type latch used in applications
where two separate data paths must be
multiplexed onto, or demultiplexed from, a single
data path. Typical applications include
multiplexing and/or demultiplexing address and
data information in microprocessor or businterface applications. This device is also useful in
memory-interleaving applications.
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
OE2B
LEA2B
2B4
GND
2B5
2B6
VCC
2B7
2B8
2B9
GND
2B10
2B11
2B12
1B12
1B11
1B10
GND
1B9
1B8
1B7
VCC
1B6
1B5
GND
1B4
LEA1B
OE1B
Three 12-bit I/O ports (A1−A12, 1B1−1B12, and
2B1−2B12) are available for address and/or data
transfer. The output-enable (OE1B, OE2B, and
OEA) inputs control the bus transceiver functions.
The OE1B and OE2B control signals also allow
bank control in the A-to-B direction.
Address and/or data information can be stored using the internal storage latches. The latch-enable (LE1B,
LE2B, LEA1B, and LEA2B) inputs are used to control data storage. When the latch-enable input is high, the
latch is transparent. When the latch-enable input goes low, the data present at the inputs is latched and remains
latched until the latch-enable input is returned high.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVC16260 is available in TI’s shrink small-outline (DL) and thin shrink small-outline (DGG)
packages, which provide twice the I/O pin count and functionality of standard small-outline packages in the
same printed-circuit-board area.
The SN74ALVC16260 is characterized for operation from − 40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright 1995, Texas Instruments Incorporated
!"#$%! & '("")% $& ! *(+,'$%! -$%).
"!-('%& '!!"# %! &*)''$%!& *)" %/) %)"#& ! )0$& &%"(#)%&
&%$-$"- 1$""$%2. "!-('%! *"!')&&3 -!)& !% )')&&$",2 ',(-)
%)&%3 ! $,, *$"$#)%)"&.
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•
1
SCAS252A − OCTOBER 1993 − REVISED JULY 1995
Function Tables
B TO A (OEB = H)
INPUTS
1B
2B
SEL
LE1B
LE2B
OEA
OUTPUT
A
H
X
H
H
X
L
H
L
X
H
H
X
L
L
X
X
H
L
X
L
X
H
L
X
H
L
A0
H
X
L
L
X
H
L
L
X
X
L
X
L
L
X
X
X
X
X
H
A0
Z
A TO B (OEA = H)
INPUTS
2
OUTPUTS
A
LEA1B
LEA2B
OE1B
OE2B
1B
2B
H
H
H
L
H
H
L
L
H
H
L
L
L
H
H
L
L
L
L
H
2B0
2B0
L
H
L
L
L
L
H
L
H
L
L
1B0
1B0
H
2B0
Z
L
L
H
L
L
X
L
L
L
L
X
X
X
H
H
1B0
Z
X
X
X
L
H
Active
Z
X
X
X
H
L
Z
Active
X
X
X
L
L
Active
Active
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•
L
SCAS252A − OCTOBER 1993 − REVISED JULY 1995
logic diagram (positive logic)
2
LE1B
LE2B
LEA1B
27
30
55
LEA2B
OE2B
OE1B
OEA
56
29
1
28
SEL
A1
G1
C1
1
1D
8
23
1B1
1
C1
1D
6
2B1
C1
1D
C1
1D
To 11 Other Channels
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3
SCAS252A − OCTOBER 1993 − REVISED JULY 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Input voltage range, VI: (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
(I/O ports) (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 100 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 3): DGG package . . . . . . . . . . . . . . . . . . 1 W
DL package . . . . . . . . . . . . . . . . . . 1.4 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The input and output positive voltage ratings may be exceeded up to 4.6 V if the input and output clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology
Data Book, literature number SCBD002B.
recommended operating conditions (see Note 4)
MIN
MAX
2.3
3.6
VCC
Supply voltage
VIH
High-level input voltage
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VIL
Low-level input voltage
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VI
VO
Input voltage
0
Output voltage
0
IOH
High-level output current
IOL
Low-level output current
∆t /∆v
Input transition rise or fall rate
4
•
•
V
2
0.7
0.8
VCC
VCC
−12
VCC = 3 V
VCC = 2.3 V
−24
VCC = 2.7 V
VCC = 3 V
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V
1.7
VCC = 2.3 V
VCC = 2.7 V
TA
Operating free-air temperature
NOTE 4: Unused control inputs must be held high or low to prevent them from floating.
UNIT
−12
V
V
V
mA
12
mA
24
0
10
ns / V
−40
85
°C
SCAS252A − OCTOBER 1993 − REVISED JULY 1995
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
IOH = − 100 µA
IOH = − 6 mA,
VOH
II(hold)
2.3 V
VCC −0.2
2
2.3 V
1.7
VIH = 2 V
VIH = 2 V
2.7 V
2.2
3V
2.4
3V
2
VIH = 2 V
IOL = 6 mA,
IOL = 24 mA,
VI = VCC or GND
0.2
2.3 V
0.4
2.3 V
0.7
VIL = 0.8 V
VIL = 0.8 V
2.7 V
0.4
3V
0.55
±5
3.6 V
2.3 V
VI = 0.8 V
VI = 2 V
3V
UNIT
V
VIL = 0.7 V
VIL = 0.7 V
VI = 0.7 V
VI = 1.7 V
V
µA
45
−45
µA
75
VI = VCC or GND,
One input at VCC − 0.6 V,
Other inputs at VCC or GND
nICC
MAX
MIN to MAX
−75
3.6 V
± 500
3.6 V
± 10
µA
3.6 V
40
µA
3 V to 3.6 V
750
µA
VI = 0 to 3.6 V
VO = VCC or GND
IOZ§
ICC
TYP‡
VIH = 1.7 V
VIH = 1.7 V
IOH = − 24 mA,
IOL = 100 µA
IOL = 12 mA
II
MIN
MIN to MAX
IOH = − 12 mA
VOL
VCC†
TEST CONDITIONS
IO = 0
Ci
Control inputs VI = VCC or GND
3.3 V
Cio
A or B ports
VO = VCC or GND
3.3 V
† For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions.
‡ All typical values are at VCC = 3.3 V.
§ For I/O ports, the parameter IOZ includes the input-leakage current.
3.5
pF
9
pF
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
VCC = 2.5 V
± 0.2 V
MIN
MAX
0
150
VCC = 2.7 V
MIN
MAX
0
150
VCC = 3.3 V
± 0.3 V
MIN
MAX
0
150
UNIT
fclock
tw
Clock frequency
Pulse duration, LE1B, LE2B, LEA1B, or LEA2B high
3.3
3.3
3.3
ns
tsu
th
Setup time, data before LE1B, LE2B, LEA1B, or LEA2B low
1.4
1.1
1.1
ns
Hold time, data after LE1B, LE2B, LEA1B, or LEA2B low
1.6
1.9
1.5
ns
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MHz
5
SCAS252A − OCTOBER 1993 − REVISED JULY 1995
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figures 1 and 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
MIN
MAX
150
VCC = 2.7 V
MIN
MAX
150
VCC = 3.3 V
± 0.3 V
MIN
UNIT
MAX
150
ns
A or B
B or A
1.2
6
5.1
1.2
4.3
LE
A or B
1
6.2
5.2
1
4.4
SEL
A
1.2
7.5
6.6
1.1
5.6
ten
OE
A or B
1
7.2
6.4
1
5.4
ns
tdis
OE
A or B
1.7
5.9
5
1.3
4.6
ns
tpd
6
VCC = 2.5 V
± 0.2 V
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ns
SCAS252A − OCTOBER 1993 − REVISED JULY 1995
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V " 0.2 V
4.6 V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
4.6 V
GND
tw
LOAD CIRCUIT
2.3 V
Input
2.3 V
Timing
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
2.3 V
Data
Input
1.2 V
1.2 V
0V
tPHL
Output
Waveform 2
S1 at GND
(see Note B)
VOH
1.2 V
1.2 V
VOL
1.2 V
0V
tPLZ
2.3 V
Output
Waveform 1
S1 at 4.6 V
(see Note B)
1.2 V
tPLH
1.2 V
tPZL
2.3 V
1.2 V
2.3 V
Output
Control
(low-level
enabling)
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
1.2 V
0V
0V
tsu
Input
1.2 V
1.2 V
1.2 V
tPZH
VOL + 0.3 V
VOL
tPHZ
1.2 V
VOH − 0.3 V
VOH
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR v 10 MHz, ZO = 50 Ω, tr v 2.5 ns, tf v 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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7
SCAS252A − OCTOBER 1993 − REVISED JULY 1995
PARAMETER MEASUREMENT INFORMATION
VCC = 2.7 V AND 3.3 V " 0.3 V
6V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
tw
LOAD CIRCUIT
2.7 V
Input
2.7 V
Timing
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
2.7 V
Data
Input
1.5 V
1.5 V
0V
tPHL
Output
Waveform 2
S1 at GND
(see Note B)
VOH
1.5 V
1.5 V
VOL
1.5 V
0V
tPLZ
3V
Output
Waveform 1
S1 at 6 V
(see Note B)
1.5 V
tPLH
1.5 V
tPZL
2.7 V
1.5 V
2.7 V
Output
Control
(low-level
enabling)
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
1.5 V
0V
0V
tsu
Input
1.5 V
1.5 V
1.5 V
tPZH
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH − 0.3 V
VOH
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR v 10 MHz, ZO = 50 Ω, tr v 2.5 ns, tf v 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
8
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