RMPA1765 K-PCS, CDMA, CDMA2000-1X and WCDMA Power Edge™ Power Amplifier Module Features General Description ■ Single positive-supply operation and low power and The RMPA1765 power amplifier module (PAM) is designed for Korean CDMA, CDMA2000-1X, WCDMA, and HSDPA personal communications system (PCS) applications. The 2 stage PAM is internally matched to 50 Ohms to minimize the use of external components and features a low-power mode to reduce standby current and DC power consumption during peak phone usage. High power-added efficiency and excellent linearity are achieved using Fairchild RF’s InGaP Heterojunction Bipolar Transistor (HBT) process. ■ ■ ■ ■ ■ shutdown modes 38% CDMA/WCDMA efficiency at +28 dBm average output power Compact lead-free compliant LCC package3.0 x 3.0 x 1.0mm with industry standard pinout Internally matched to 50 Ohms and DC blocked RF input/output. Meets CDMA2000-1XRTT/WCDMA performance requirements Meets HSDPA performance requirements Device Functional Block Diagram (Top View) PA MODULE Vcc1 1 RF IN 2 Vmode 3 Vref 4 MMIC Output Match Input Match DC Bias Control 8 Vcc2 7 RF OUT 6 GND 5 GND (paddle ground on package bottom) ©2005 Fairchild Semiconductor Corporation RMPA1765 Rev. E 1 www.fairchildsemi.com RMPA1765 K-PCS, CDMA, CDMA2000-1X and WCDMA Power Edge™ Power Amplifier Module October 2006 Symbol Parameter Vcc1, Vcc2 Supply Voltages Vref Reference Voltage Vmode Power Control Voltage Pin RF Input Power Tstg Storage Temperature Value Units 5.0 V 2.6 to 3.5 V 3.5 V +10 dBm -55 to +150 °C Note: 1. No permanent damage with one parameter set at extreme limit. Other parameters set to typical values. Electrical Characteristics(1) Symbol f Parameter Operating Frequency Min. Typ. Max. Units 1720 1780 Comments MHz CDMA OPERATION SSg Small-Signal Gain 26 dB Po = 0dBm Gp Power Gain 28 dB Po = +28dBm; Vmode = 0V dB Po = +16dBm; Vmode = 2.0V Po Linear Output Power 26 28 16 PAEd Itot PAEd (digital) @ +28dBm dBm Vmode = 0V dBm Vmode ≥ 2.0V 38 % Vmode = 0V PAEd (digital) @ +16dBm 9 % Vmode ≥ 2.0V PAEd (digital) @ +16dBm 25 % Vmode ≥ 2.0V, Vcc = 1.4V High Power Total Current 490 mA Po = +28dBm, Vmode = 0V Low Power Total Current 130 mA Po = +16dBm, Vmode = 2.0V -50 dBc Po = +28dBm; Vmode = 0V -52 dBc Po = +16dBm; Vmode = 2V -60 dBc Po = +28dBm; Vmode = 0V, IS-95 -68 dBc Po = +16dBm; Vmode = 2V Adjacent Channel Power Ratio ACPR1 ±1.25MHz Offset ACPR2 ±2.25MHz Offset GENERAL CHARACTERISTICS VSWR NF Input Impedance 2.0:1 Noise Figure Rx No Receive Band Noise Power 2fo-5fo Harmonic Suppression S Tc 4 dB -139 dBm/ Hz -30 dBc Spurious Outputs -60 dBc Ruggedness w/ Load Mismatch(3) 10:1 (2)(3) Case Operating Temperature -30 85 Po ≤ +28dBm; 1840MHz to 1870MHz Po ≤ +28dBm Load VSWR ≤ 5.0:1 No permanent damage. °C DC CHARACTERISTICS Iccq Quiescent Current 45 Iref Reference Current 5 Shutdown Leakage Current 1 Icc(off) mA Vmode ≥ 2.0V 8 mA Po < +28dBm 5 µA No applied RF signal. Notes: 1. All parameters met at Tc = +25°C, Vcc = +3.4V, Vref = 2.85V, f = 1750 MHz and load VSWR ≤ 1.2:1, unless otherwise noted. 2. All phase angles. 3. Guaranteed by design. 2 RMPA1765 Rev. E www.fairchildsemi.com RMPA1765 K-PCS, CDMA, CDMA2000-1X and WCDMA Power Edge™ Power Amplifier Module Absolute Maximum Ratings(1) RMPA1765 K-PCS 3x3mm2 PAM Vcc=3.4V, Vref = 2.85V, Vmode=0V, Pout=28dBm 33.0 43.0 32.0 42.0 31.0 41.0 30.0 40.0 PAE (%) Gain (dB) RMPA1765 K-PCS 3x3mm2 PAM Vcc=3.4V, Vref = 2.85V, Vmode=0V, Pout=28dBm 29.0 28.0 27.0 39.0 38.0 37.0 26.0 36.0 25.0 35.0 24.0 34.0 23.0 1720 1740 1760 33.0 1720 1780 -40.0 -50.0 -42.0 -52.0 -44.0 -54.0 -46.0 -56.0 -48.0 -50.0 -52.0 -54.0 1780 -58.0 -60.0 -62.0 -64.0 -56.0 -66.0 -58.0 -68.0 -70.0 -60.0 1740 1760 1720 1780 1740 1760 1780 Frequency (MHz) Frequency (MHz) 3 RMPA1765 Rev. E 1760 RMPA1765 K-PCS 3x3mm2 PAM Vcc=3.4V, Vref = 2.85V, Vmode=0V, Pout=28dBm ACPR2 (dBc) ACPR1 (dBc) RMPA1765 K-PCS 3x3mm2 PAM Vcc=3.4V, Vref = 2.85V, Vmode=0V, Pout=28dBm 1720 1740 Frequency (MHz) Frequency (MHz) www.fairchildsemi.com RMPA1765 K-PCS, CDMA, CDMA2000-1X and WCDMA Power Edge™ Power Amplifier Module Performance Data In addition to high-power/low-power bias modes, the efficiency of the PA module can be significantly increased at backed-off RF power levels by dynamically varying the supply voltage (Vcc) applied to the amplifier. Since mobile handsets and power amplifiers frequently operate at 10-20 dB back-off, or more, from maximum rated linear power, battery life is highly dependent on the DC power consumed at antenna power levels in the range of 0 to +16dBm. The reduced demand on transmitted RF power allows the PA supply voltage to be reduced for improved efficiency, while still meeting linearity requirements for CDMA modulation with excellent margin. High-efficiency DC-DC converters are now available to implement switched-voltage operation. With the PA module in low-power mode (Vmode = +2.0V) at+16dBm output power and supply voltages reduced from 3.4V nominal down to 1.2V, power-added efficiency is more than doubled from 9.5 percent to nearly 25 percent (Vcc = 1.2V) while maintaining a typical ACPR1 of –52dBc and ACPR2 of less than –61dBc. Operation at even lower levels of Vcc supply voltage are possible with a further restriction on the maximum RF output power. Recommended Operating Conditions Symbol f Vcc1, Vcc2 Vref Parameter Min. Operating Frequency 1720 Supply Voltage Reference Voltage (operating) (shutdown) Vmode 1780 MHz 4.2 V 2.7 2.85 3.1 V 0.5 V 3.0 V 0.5 V +28 dBm +16 dBm +85 °C 1.8 0 Linear Output Power (high-power) Case Operating Temperature Units 3.4 (low-power) Tc Max. 3.0 0 Bias Control Voltage (low-power) (high-power) Pout Typ. -30 2.0 DC Turn-On Sequence 1) Vcc1 = Vcc2 = 3.4V (typical) 2) Vref = 2.85V (typical) 3) High-Power: Vmode = 0V (Pout > 16dBm) Low-Power: Vmode = 2V (Pout < 16dBm) 4 RMPA1765 Rev. E www.fairchildsemi.com RMPA1765 K-PCS, CDMA, CDMA2000-1X and WCDMA Power Edge™ Power Amplifier Module Efficiency Improvement Applications 5 1 3 6 6 5 2 Z XYTT 1765 4 7 5 Materials List Qty Item No. 1 1 G657691-1 V1 Part Number Description Vendor 2 2 #142-0701-841 SMA Connector Johnson 7 3 #2340-5211TN Terminals 3M Assembly, RMPA1765 Fairchild 1000pF Capacitor (0603) Murata PC Board Fairchild Ref 4 3 5 3 5 (Alt) ECJ-1VB1H102K 1000pF Capacitor (0603) Panasonic 2 6 C3216X5R1A335M 3.3µF Capacitor (1206) TDK 1 7 GRM39Y5V104Z16V 0.1µF Capacitor (0603) Murata 1 7 (Alt) ECJ-1VB1C104K 0.1µF Capacitor (0603) Panasonic A/R 8 SN63 Solder Paste Indium Corp. A/R 9 SN96 Solder Paste Indium Corp. GRM39X7R102K50V Evaluation Board Schematic 3.3 µF 1 Vcc1 SMA1 RF IN 2 50 Ohm TRL 3 Vmode 1000 pF 1000 pF 1000 pF Vref 8 Z XYTT 1765 4 7 Vcc2 50 Ohm TRL SMA2 RF OUT 5, 6 9 0.1 µF (package base) 5 RMPA1765 Rev. E 3.3 µF www.fairchildsemi.com RMPA1765 K-PCS, CDMA, CDMA2000-1X and WCDMA Power Edge™ Power Amplifier Module Evaluation Board Layout TOP VIEW 1 2 3.00 +.100 –.050 mm SQ. 3 4 8 Z XYTT 1765 7 6 X Z 17 YTT 65 5 I/O 1 INDICATOR FRONT VIEW 1.10mm MAX. 4X R.25mm 4 5 3 6 2 BACK SIDE SOLDER MASK 0.40mm 1 2.60mm 2 1 SEE DETAIL A 1.00mm 7 9 1.00mm 0.40mm 0.10mm 0.40mm 0.10mm 8 DETAIL A TYP. 0.20mm BOTTOM VIEW Signal Descriptions Pin # Signal Name Description 1 Vcc1 Supply Voltage to Input Stage Reference Voltage 2 RF In RF Input Signal 3 Vmode High-Power/Low-Power Mode Control 4 Vref Reference Voltage 5 GND Ground 6 GND Ground 7 RF Out 8 Vcc2 RF Output Signal Supply Voltage to Output Stage 6 RMPA1765 Rev. E www.fairchildsemi.com RMPA1765 K-PCS, CDMA, CDMA2000-1X and WCDMA Power Edge™ Power Amplifier Module Package Outline CAUTION: THIS IS AN ESD SENSITIVE DEVICE. Precautions to Avoid Permanent Device Damage: Solder Materials & Temperature Profile: Reflow soldering is the preferred method of SMT attachment. Hand soldering is not recommended. • Cleanliness: Observe proper handling procedures to ensure clean devices and PCBs. Devices should remain in their original packaging until component placement to ensure no contamination or damage to RF, DC and ground contact areas. Reflow Profile • Ramp-up: During this stage the solvents are evaporated from the solder paste. Care should be taken to prevent rapid oxidation (or paste slump) and solder bursts caused by violent solvent out-gassing. A maximum heating rate is 3°C/sec. • Device Cleaning: Standard board cleaning techniques should not present device problems provided that the boards are properly dried to remove solvents or water residues. • Pre-heat/soak: The soak temperature stage serves two purposes; the flux is activated and the board and devices achieve a uniform temperature. The recommended soak condition is: 60-180 seconds at 150-200°C. • Static Sensitivity: Follow ESD precautions to protect against ESD damage: – A properly grounded static-dissipative surface on which to place devices. • General Handling: Handle the package on the top with a vacuum collet or along the edges with a sharp pair of bent tweezers. Avoiding damaging the RF, DC, and ground contacts on the package bottom. Do not apply excessive pressure to the top of the lid. • Reflow Zone: If the temperature is too high, then devices may be damaged by mechanical stress due to thermal mismatch or there may be problems due to excessive solder oxidation. Excessive time at temperature can enhance the formation of inter-metallic compounds at the lead/board interface and may lead to early mechanical failure of the joint. Reflow must occur prior to the flux being completely driven off. The duration of peak reflow temperature should not exceed 20 seconds. Soldering temperatures should be in the range 255–260°C, with a maximum limit of 260°C. • Device Storage: Devices are supplied in heat-sealed, moisture-barrier bags. In this condition, devices are protected and require no special storage conditions. Once the sealed bag has been opened, devices should be stored in a dry nitrogen environment. • Cooling Zone: Steep thermal gradients may give rise to excessive thermal shock. However, rapid cooling promotes a finer grain structure and a more crack-resistant solder joint. The illustration below indicates the recommended soldering profile. Device Usage: Fairchild recommends the following procedures prior to assembly. Solder Joint Characteristics: Proper operation of this device depends on a reliable void-free attachment of the heat sink to the PWB. The solder joint should be 95% void-free and be a consistent thickness. – Static-dissipative floor or mat. – A properly grounded conductive wrist strap for each person to wear while handling devices. • Assemble the devices within 7 days of removal from the dry pack. Rework Considerations: Rework of a device attached to a board is limited to reflow of the solder with a heat gun. The device should be subjected to no more than 15°C above the solder melting temperature for no more than 5 seconds. No more than 2 rework operations should be performed. • During the 7-day period, the devices must be stored in an environment of less than 60% relative humidity and a maximum temperature of 30°C • If the 7-day period or the environmental conditions have been exceeded, then the dry-bake procedure, at 125°C for 24 hours minimum, must be performed. Recommended Solder Reflow Profile Peak tem p 260 +0/-5 °C 10 - 20 sec 260 Temperature (°C) Ramp-Up R ate 3 °C/sec max 217 200 Time above li quidus temp 60 - 150 sec 150 Preheat, 150 to 200 °C 60 - 180 sec 100 Ramp-Up R ate 3 °C/sec max Ramp-Do wn Rate 6 °C/sec max 50 25 Time 25 °C/sec t o peak tem p 6 mi nutes max Time (Sec) 7 RMPA1765 Rev. E www.fairchildsemi.com RMPA1765 K-PCS, CDMA, CDMA2000-1X and WCDMA Power Edge™ Power Amplifier Module Applications Information FAIRCHILD SEMICONDUCTOR TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. FACT Quiet Series™ GlobalOptoisolator™ GTO™ HiSeC™ I2C™ i-Lo™ ImpliedDisconnect™ IntelliMAX™ ISOPLANAR™ LittleFET™ MICROCOUPLER™ MicroFET™ MicroPak™ MICROWIRE™ MSX™ MSXPro™ Across the board. Around the world.™ The Power Franchise® Programmable Active Droop™ ACEx™ ActiveArray™ Bottomless™ Build it Now™ CoolFET™ CROSSVOLT™ DOME™ EcoSPARK™ E2CMOS™ EnSigna™ FACT® FAST® FASTr™ FPS™ FRFET™ OCX™ OCXPro™ OPTOLOGIC® OPTOPLANAR™ PACMAN™ POP™ Power247™ PowerEdge™ PowerSaver™ PowerTrench® QFET® QS™ QT Optoelectronics™ Quiet Series™ RapidConfigure™ RapidConnect™ µSerDes™ ScalarPump™ SILENT SWITCHER® SMART START™ SPM™ Stealth™ SuperFET™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TCM™ TinyBoost™ TinyBuck™ TinyPWM™ TinyPower™ TinyLogic® TINYOPTO™ TruTranslation™ UHC® UniFET™ UltraFET® VCX™ Wire™ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. I21