TPS742xx TP S7 42x x TP S7 42 xx www.ti.com SBVS064L – DECEMBER 2005 – REVISED NOVEMBER 2010 1.5A Ultra-LDO with Programmable Soft-Start Check for Samples: TPS742xx FEATURES 1 • 2 • • • • • • • • • • Soft-Start (SS) Pin Provides a Linear Startup with Ramp Time Set by External Capacitor 1% Accuracy Over Line, Load, and Temperature Supports Input Voltages as Low as 0.9V with External Bias Supply Adjustable Output (0.8V to 3.6V) Fixed Output (0.9V to 3.6V) Ultra-Low Dropout: 55mV at 1.5A (typ) Stable with Any or No Output Capacitor Excellent Transient Response Available in 5mm × 5mm × 1mm QFN and DDPAK-7 Packages Open-Drain Power-Good (5 × 5 QFN) Active High Enable APPLICATIONS • • • • • FPGA Applications DSP Core and I/O Voltages Post-Regulation Applications Applications with Special Start-Up Time or Sequencing Requirements Hot-Swap and Inrush Controls DESCRIPTION The TPS742xx low-dropout (LDO) linear regulators provide an easy-to-use robust power management solution for a wide variety of applications. User-programmable soft-start minimizes stress on the input power source by reducing capacitive inrush current on start-up. The soft-start is monotonic and well suited for powering many different types of processors and ASICs. The enable input and power-good output allow easy sequencing with external regulators. This complete flexibility permits the user to configure a solution that will meet the sequencing requirements of FPGAs, DSPs, and other applications with special start-up requirements. A precision reference and error amplifier deliver 1% accuracy over load, line, temperature, and process. Each LDO is stable with low-cost ceramic output capacitors and the family is fully specified from –40°C to +125°C. The TPS742xx is offered in a small (5mm × 5mm) QFN package, yielding a highly compact total solution size. For applications that require additional power dissipation, the DDPAK (KTW) package is also available. ADJUSTABLE VOLTAGE VERSION VIN IN CIN 1mF PG R3 BIAS EN VBIAS TPS74201 R1 SS CBIAS 1mF GND FB CSS CSS = 0mF CSS = 0.001mF VOUT OUT COUT R2 VOUT Optional CSS = 0.0047mF 1V/div FIXED VOLTAGE VERSION VIN IN CIN 1 mF 1.2V 1V/div VEN 0V PG R3 BIAS EN VBIAS TPS742xx OUT GND SNS SS CBIAS 1 mF VOUT COUT CSS Time (1ms/div) Figure 1. Turn-On Response Optional Figure 2. Typical Application Circuits 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005–2010, Texas Instruments Incorporated TPS742xx SBVS064L – DECEMBER 2005 – REVISED NOVEMBER 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PRODUCT TPS742xx yyy z (1) (2) (3) VOUT (2) XX is nominal output voltage (for example, 12 = 1.2V, 15 = 1.5V, 01 = Adjustable). (3) YYY is package designator. Z is package quantity. For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Output voltages from 0.9V to 1.5V in 50mV increments and 1.5V to 3.3V in 100mV increments are available through the use of innovative factory EEPROM programming; minimum order quantities may apply. Contact factory for details and availability. For fixed 0.8V operation, tie FB to OUT. ABSOLUTE MAXIMUM RATINGS (1) At TJ = –40°C to +125°C, unless otherwise noted. All voltages are with respect to GND. TPS742xx UNIT –0.3 to +6 V VEN Enable voltage range –0.3 to +6 V VPG Power-good voltage range –0.3 to +6 V 0 to +1.5 mA VSS SS pin voltage range –0.3 to +6 V VFB Feedback pin voltage range –0.3 to +6 V –0.3 to VIN + 0.3 V VIN, VBIAS Input voltage range IPG PG sink current VOUT Output voltage range IOUT Maximum output current Indefinite PDISS Continuous total power dissipation See Thermal Information Table TJ Operating junction temperature range TSTG Storage junction temperature range (1) 2 Internally limited Output short circuit duration –40 to +125 °C –55 to +150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Submit Documentation Feedback Copyright © 2005–2010, Texas Instruments Incorporated TPS742xx www.ti.com SBVS064L – DECEMBER 2005 – REVISED NOVEMBER 2010 THERMAL INFORMATION TPS742xx (3) THERMAL METRIC (1) (2) RGW (20 PINS) KTW (7 PINS) qJA Junction-to-ambient thermal resistance (4) 30.5 20.1 qJCtop Junction-to-case (top) thermal resistance (5) 27.6 2.1 (6) qJB Junction-to-board thermal resistance yJT Junction-to-top characterization parameter (7) yJB Junction-to-board characterization parameter (8) qJCbot (1) (2) (3) (4) (5) (6) (7) (8) (9) Junction-to-case (bottom) thermal resistance (9) N/A N/A 0.37 4.2 10.6 6.1 4.1 1.4 UNITS °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953A. For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator. Thermal data for the RGW and KTW packages are derived by thermal simulations based on JEDEC-standard methodology as specified in the JESD51 series. The following assumptions are used in the simulations: (a) i. RGW: The exposed pad is connected to the PCB ground layer through a 4x4 thermal via array. - ii. KTW: The exposed pad is connected to the PCB ground layer through a 6x6 thermal via array. (b) Each of top and bottom copper layers has a dedicated pattern for 20% copper coverage. (c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in × 3in copper area. To understand the effects of the copper area on thermal performance, refer to the Power Dissipation and Estimating Junction Temperature sections. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data to obtain qJA using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, yJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data to obtain qJA using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Copyright © 2005–2010, Texas Instruments Incorporated Submit Documentation Feedback 3 TPS742xx SBVS064L – DECEMBER 2005 – REVISED NOVEMBER 2010 www.ti.com ELECTRICAL CHARACTERISTICS At VEN = 1.1V, VIN = VOUT + 0.3V, CIN = CBIAS = 0.1mF, COUT = 10mF, IOUT = 50mA, VBIAS = 5.0V, and TJ = –40°C to +125°C, unless otherwise noted. Typical values are at TJ = +25°C. TPS742xx PARAMETER TEST CONDITIONS VIN Input voltage range MIN VBIAS Bias pin voltage range VREF Internal reference (Adj.) VOUT 0.796 Output voltage range VIN = 5V, IOUT = 1.5A, VBIAS = 5V VREF Accuracy (1) 2.375V ≤ VBIAS ≤ 5.25V, VOUT + 1.62V ≤ VBIAS 50mA ≤ IOUT ≤ 1.5A VOUT/IOUT Load regulation VDO VIN dropout voltage (2) VBIAS dropout voltage (2) ICL Current limit IBIAS Bias pin current ISHDN IFB, ISNS –1 + 0.3 ≤ VIN ≤ 5.5V, QFN VOUT (NOM) VOUT (NOM) + 0.3 ≤ VIN ≤ 5.5V, DDPAK V ±0.2 1 % 0.0005 0.05 0.0005 0.06 0.04 %/V %/mA %/A IOUT = 1.5A, VBIAS – VOUT (NOM) ≥ 1.62V, QFN 55 100 mV IOUT = 1.5A, VBIAS – VOUT (NOM) ≥ 1.62V, DDPAK 60 120 mV 1.4 V IOUT = 1.5A, VIN = VBIAS VOUT = 80% × VOUT (NOM) 1.8 4 A mA Shutdown supply current (VIN) VEN ≤ 0.4V 1 100 mA Feedback, Sense pin current (3) IOUT = 50mA to 1.5A 68 250 nA –250 Power-supply rejection (VIN to VOUT) 1kHz, IOUT = 1.5A, VIN = 1.8V, VOUT = 1.5V 73 300kHz, IOUT = 1.5A, VIN = 1.8V, VOUT = 1.5V 42 Power-supply rejection (VBIAS to VOUT) 1kHz, IOUT = 1.5A, VIN = 1.8V, VOUT = 1.5V 62 300kHz, IOUT = 1.5A, VIN = 1.8V, VOUT = 1.5V 50 100Hz to 100kHz, IOUT = 1.5A, CSS = 0.001mF 16 × VOUT mVRMS 3.5 %VOUT %VOUT droop during load transient IOUT = 50mA to 1.5A at 1A/ms, COUT = none IOUT = 1.5A, CSS = open 0 VEN, DG Enable pin deglitch time IEN Enable pin current VEN = 5V VOUT decreasing 86.5 VHYS PG trip hysteresis IPG = 1mA (sinking), VOUT < VIT PG leakage current VPG = 5.25V, VOUT > VIT Operating junction temperature TSD Thermal shutdown temperature dB ms 1 mA 5.5 V 0.4 V 50 mV 20 ms 0.1 1 mA 90 93.5 %VOUT 3 PG output low voltage TJ 0.73 1.1 VIT PG trip threshold dB 100 0.5 VEN, LO Enable input low level 4 V 3.6 0.013 VEN, HYS Enable pin hysteresis (1) (2) (3) V 50mA ≤ IOUT ≤ 1.5A VEN, HI Enable input high level LO 5.25 0.804 0.8 0mA ≤ IOUT ≤ 50mA ISS Soft-start charging current VSS = 0.4V LKG V 4 tSTR Minimum startup time VPG, UNIT 5.5 2 Noise Output noise voltage IPG, MAX IOUT = 0mA to 1.5A PSRR VTRAN 2.375 TJ = +25°C VOUT/VIN Line regulation TYP VOUT + VDO 0.03 –40 Shutdown, temperature increasing +155 Reset, temperature decreasing +140 %VOUT 0.3 V 1 mA +125 °C °C Adjustable devices tested at 0.8V; resistor tolerance is not taken into account. Dropout is defined as the voltage from the input to VOUT when VOUT is 2% below nominal. IFB, ISNS current flow is out of the device. Submit Documentation Feedback Copyright © 2005–2010, Texas Instruments Incorporated TPS742xx www.ti.com SBVS064L – DECEMBER 2005 – REVISED NOVEMBER 2010 BLOCK DIAGRAMS IN Current Limit BIAS UVLO OUT Thermal Limit 0.73mA VOUT R1 SS CSS Soft-Start Discharge VOUT = 0.8 x (1 + 0.8V Reference R1 ) R2 FB PG Hysteresis and De-Glitch EN R2 0.9 ´ VREF GND Figure 3. Adjustable Voltage Version IN Current Limit BIAS UVLO OUT VOUT RSMALL SNS Thermal Limit 0.73mA R1 SS CSS Soft-Start Discharge R2 0.8V Reference PG EN Hysteresis and De-Glitch 0.9 ´ VREF GND Figure 4. Fixed Voltage Versions Copyright © 2005–2010, Texas Instruments Incorporated Submit Documentation Feedback 5 TPS742xx SBVS064L – DECEMBER 2005 – REVISED NOVEMBER 2010 www.ti.com Table 1. Standard 1% Resistor Values for Programming the Output Voltage (1) (1) R1 (kΩ) R2 (kΩ) VOUT (V) Short Open 0.8 0.619 4.99 0.9 1.13 4.53 1.0 1.37 4.42 1.05 1.87 4.99 1.1 2.49 4.99 1.2 4.12 4.75 1.5 3.57 2.87 1.8 3.57 1.69 2.5 3.57 1.15 3.3 VOUT = 0.8 × (1 + R1/R2) Table 2. Standard Capacitor Values for Programming the Soft-Start Time (1) tSS(s) = (1) 6 CSS SOFT-START TIME Open 0.1ms 470pF 0.5ms 1000pF 1ms 4700pF 5ms 0.01mF 10ms 0.015mF 16ms VREF × CSS 0.8V × CSS(F) = 0.73mA ISS where tSS(s) = soft-start time in seconds. Submit Documentation Feedback Copyright © 2005–2010, Texas Instruments Incorporated TPS742xx www.ti.com SBVS064L – DECEMBER 2005 – REVISED NOVEMBER 2010 PIN CONFIGURATIONS IN NC NC NC OUT 5 4 3 2 1 RGW PACKAGE 5 × 5 QFN-20 (TOP VIEW) KTW PACKAGE DDPAK-7 SURFACE-MOUNT IN 6 20 OUT IN 7 19 OUT IN 8 18 OUT PG 9 17 NC BIAS 10 16 FB/SNS 11 12 13 14 15 EN GND NC NC SS TPS742xx GND 1 2 3 4 5 6 7 SS OUT IN EN FB/ GND BIAS SNS PIN DESCRIPTIONS NAME KTW (DDPAK) RGW (QFN) IN 5 5–8 Unregulated input to the device. EN 7 11 Enable pin. Driving this pin high enables the regulator. Driving this pin low puts the regulator into shutdown mode. This pin must not be left floating. SS 1 15 Soft-Start pin. A capacitor connected on this pin to ground sets the start-up time. If this pin is left floating, the regulator output soft-start ramp time is typically 100ms. BIAS 6 10 Bias input voltage for error amplifier, reference, and internal control circuits. 9 Power-Good (PG) is an open-drain, active-high output that indicates the status of VOUT. When VOUT exceeds the PG trip threshold, the PG pin goes into a high-impedance state. When VOUT is below this threshold the pin is driven to a low-impedance state. A pull-up resistor from 10kΩ to 1MΩ should be connected from this pin to a supply up to 5.5V. The supply can be higher than the input voltage. Alternatively, the PG pin can be left floating if output monitoring is not necessary. PG N/A FB 2 16 DESCRIPTION This pin is the feedback connection to the center tap of an external resistor divider network that sets the output voltage. This pin must not be left floating. (Adjustable version only.) This pin is the sense connection to the load device. This pin must be connected to VOUT and must not be left floating. (Fixed versions only.) SNS OUT 3 1, 18–20 NC N/A 2–4, 13, 14, 17 GND 4 12 PAD/TAB Copyright © 2005–2010, Texas Instruments Incorporated Regulated output voltage. No capacitor is required on this pin for stability. No connection. This pin can be left floating or connected to GND to allow better thermal contact to the top-side plane. Ground Should be soldered to the ground plane for increased thermal performance. Submit Documentation Feedback 7 TPS742xx SBVS064L – DECEMBER 2005 – REVISED NOVEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS At TJ = +25°C, VOUT = 1.5V, VIN = VOUT(TYP) + 0.3V, VBIAS = 3.3V, IOUT = 50mA, EN = VIN, CIN = 1mF, CBIAS = 4.7mF, CSS = 0.01mF, and COUT = 10mF, unless otherwise noted. LOAD REGULATION LOAD REGULATION 1.0 0.050 Referred to IOUT = 50mA 0.9 Referred to IOUT = 50mA 0.025 0.7 0.6 -40°C 0.5 0.4 +25°C 0.3 0 Change in VOUT (%) Change in VOUT (%) 0.8 0.2 +25°C -0.025 -0.050 -40°C -0.075 +125°C -0.100 0.1 +125°C 0 -0.125 -0.150 -0.1 0 10 20 30 40 50 50 500 IOUT (mA) 1000 1500 IOUT (mA) Figure 5. Figure 6. LINE REGULATION VIN DROPOUT VOLTAGE vs IOUT AND TEMPERATURE (TJ) 0.05 100 0.04 0.02 Dropout Voltage (mV) Change in VOUT (%) 0.03 TJ = -40°C 0.01 0 -0.01 TJ = +25°C TJ = +125°C -0.02 75 +125°C 50 +25°C 25 -40°C -0.03 -0.04 0 -0.05 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 0.5 VIN - VOUT (V) Figure 8. VIN DROPOUT VOLTAGE vs VBIAS – VOUT AND TEMPERATURE (TJ) VIN DROPOUT VOLTAGE vs VBIAS – VOUT AND TEMPERATURE (TJ) 60 IOUT = 1.5A 180 IOUT = 500mA 50 Dropout Voltage (mV) 160 Dropout Voltage (mV) 1.5 Figure 7. 200 140 120 +125°C 100 +25°C 80 60 40 40 +125°C 30 +25°C 20 10 -40°C 20 -40°C 0 0 0.9 8 1.0 IOUT (A) 1.4 1.9 2.4 2.9 3.4 3.9 0.9 1.4 1.9 2.4 2.9 VBIAS - VOUT (V) VBIAS - VOUT (V) Figure 9. Figure 10. Submit Documentation Feedback 3.4 3.9 Copyright © 2005–2010, Texas Instruments Incorporated TPS742xx www.ti.com SBVS064L – DECEMBER 2005 – REVISED NOVEMBER 2010 TYPICAL CHARACTERISTICS (continued) At TJ = +25°C, VOUT = 1.5V, VIN = VOUT(TYP) + 0.3V, VBIAS = 3.3V, IOUT = 50mA, EN = VIN, CIN = 1mF, CBIAS = 4.7mF, CSS = 0.01mF, and COUT = 10mF, unless otherwise noted. VBIAS DROPOUT VOLTAGE vs IOUT AND TEMPERATURE VBIAS PSRR vs FREQUENCY 1400 Power-Supply Rejection Ratio (dB) 80 Dropout Voltage (mV) 1300 1200 +25°C +125°C 1100 1000 -40°C 900 800 700 600 70 60 50 40 30 20 VIN = 1.8, VOUT = 1.5V VBIAS = 3.3V, IOUT = 1.5A 10 0 500 0 0.5 1.0 1.5 10 100 1k IOUT (A) 10k Figure 11. VIN PSRR vs FREQUENCY Power-Supply Rejection Ratio (dB) Power-Supply Rejection Ratio (dB) COUT = 10mF 60 50 40 30 20 COUT = 0mF 10 VIN = 1.8, VOUT = 1.5V, IOUT = 100mA 0 10 100 1k 10k VIN = 1.8, VOUT = 1.5V, IOUT = 1.5A 90 80 70 COUT = 100mF 60 COUT = 10mF 50 40 30 20 10 COUT = 0mF 0 100k 1M 10 10M 100 Figure 13. Figure 14. 700kHz 60 50 300kHz 100kHz 20 10 IOUT = 1.5A 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 VIN - VOUT (V) Figure 15. Copyright © 2005–2010, Texas Instruments Incorporated Output Spectral Noise Density (mV/ÖHz) Power-Supply Rejection Ratio (dB) 1kHz 40 100k 1M 10M NOISE SPECTRAL DENSITY 80 0 10k Frequency (Hz) VIN PSRR vs VIN – VOUT 30 1k Frequency (Hz) 90 70 10M VIN PSRR vs FREQUENCY 100 COUT = 100mF 90 70 1M Figure 12. 100 80 100k Frequency (Hz) 1 IOUT = 100mA VOUT = 1.1V CSS = 1nF CSS = 0nF 0.1 CSS = 10nF 0.01 100 1k 10k 100k Frequency (Hz) Figure 16. Submit Documentation Feedback 9 TPS742xx SBVS064L – DECEMBER 2005 – REVISED NOVEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) At TJ = +25°C, VOUT = 1.5V, VIN = VOUT(TYP) + 0.3V, VBIAS = 3.3V, IOUT = 50mA, EN = VIN, CIN = 1mF, CBIAS = 4.7mF, CSS = 0.01mF, and COUT = 10mF, unless otherwise noted. IBIAS vs IOUT AND TEMPERATURE IBIAS vs VBIAS AND VOUT 2.85 3.0 2.8 2.65 2.25 2.05 +25°C 1.85 1.65 +125°C 2.6 2.45 Bias Current (mA) Bias Current (mA) +125°C -40°C 2.4 2.2 +25°C 2.0 1.8 1.6 -40°C 1.4 1.45 1.2 1.25 1.0 0 0.5 1.0 2.0 1.5 2.5 3.0 3.5 4.0 4.5 IOUT (A) VBIAS (V) Figure 17. Figure 18. IBIAS SHUTDOWN vs TEMPERATURE SOFT-START CHARGING CURRENT (ISS) vs TEMPERATURE 0.45 5.0 765 0.40 VBIAS = 2.375V 750 735 0.30 VBIAS = 5.5V 0.25 ISS (nA) Bias Current (mA) 0.35 0.20 720 705 0.15 0.10 690 0.05 675 0 -40 -20 0 20 40 60 80 100 120 -40 -20 0 Junction Temperature (°C) 20 40 60 80 100 120 Junction Temperature (°C) Figure 19. Figure 20. LOW-LEVEL PG VOLTAGE vs PG CURRENT VOL Low-Level PG Voltage (V) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 12 PG Current (mA) Figure 21. 10 Submit Documentation Feedback Copyright © 2005–2010, Texas Instruments Incorporated TPS742xx www.ti.com SBVS064L – DECEMBER 2005 – REVISED NOVEMBER 2010 TYPICAL CHARACTERISTICS (continued) At TJ = +25°C, VOUT = 1.5V, VIN = VOUT(TYP) + 0.3V, VBIAS = 3.3V, IOUT = 50mA, EN = VIN, CIN = 1mF, CBIAS = 4.7mF, CSS = 0.01mF, and COUT = 10mF, unless otherwise noted. VBIAS LINE TRANSIENT (1.5A) VIN LINE TRANSIENT COUT = 1000mF 10mV/div 10mV/div COUT = 2 x 470mF (OSCON) 10mV/div COUT = 100mF COUT = 100mF (Cer.) 10mV/div COUT = 10mF COUT = 10mF (Cer.) 10mV/div 10mV/div COUT = 0mF COUT = 0mF 10mV/div 10mV/div 1V/ms 1V/div 500mV/div 1V/ms Time (50ms/div) Time (50ms/div) Figure 22. Figure 23. OUTPUT LOAD TRANSIENT RESPONSE TURN-ON RESPONSE COUT = 2 x 470mF (OSCON) CSS = 0mF 50mV/div 50mV/div CSS = 0.0047mF 1V/div 50mV/div VOUT CSS = 0.001mF COUT = 100mF (Cer.) COUT = 10mF (Cer.) 50mV/div COUT = 0mF 1.5A 1A/div 1.2V 1V/div VEN 0V 1A/ms 50mA Time (1ms/div) Time (50ms/div) Figure 24. Figure 25. POWER-UP/POWER-DOWN OUTPUT SHORT-CIRCUIT RECOVERY 1V/div VIN = VBIAS = VEN VPG (500mV/div) IOUT 500mA/div VOUT 50mV/div Output Shorted VOUT Output Open Time (20ms/div) Figure 26. Copyright © 2005–2010, Texas Instruments Incorporated Time (20ms/div) Figure 27. Submit Documentation Feedback 11 TPS742xx SBVS064L – DECEMBER 2005 – REVISED NOVEMBER 2010 www.ti.com APPLICATION INFORMATION The TPS742xx belongs to a family of new generation ultra-low dropout regulators that feature soft-start and tracking capabilities. These regulators use a low current bias input to power all internal control circuitry, allowing the NMOS pass transistor to regulate very low input and output voltages. The use of an NMOS-pass FET offers several critical advantages for many applications. Unlike a PMOS topology device, the output capacitor has little effect on loop stability. This architecture allows the TPS742xx to be stable with any or even no output capacitor. Transient response is also superior to PMOS topologies, particularly for low VIN applications. The TPS742xx features a programmable voltage-controlled soft-start circuit that provides a smooth, monotonic start-up and limits startup inrush currents that may be caused by large capacitive loads. A power-good (PG) output is available to allow supply monitoring and sequencing of other supplies. An enable (EN) pin with hysteresis and deglitch allows slow-ramping signals to be used for sequencing the device. The low VIN and VOUT capability allows for inexpensive, easy-to-design, and efficient linear regulation between the multiple supply voltages often present in processor intensive systems. Figure 28 is a typical application circuit for the TPS74201 adjustable output device. R1 and R2 can be calculated for any output voltage using the formula shown in Figure 28. Refer to Table 1 for sample resistor values of common output voltages. In order to achieve the maximum accuracy specifications, R2 should be ≤ 4.99kΩ. IN CIN 1mF PG R3 BIAS EN VBIAS TPS74201 R1 SS CBIAS 1mF VOUT OUT FB GND CSS COUT Optional R2 VOUT = 0.8 ´ ( 1+ R1 R2 Figure 29 illustrates a typical application circuit for the TPS742xx fixed output device. VIN IN CIN 1 mF PG R3 BIAS EN VBIAS TPS742xx OUT GND SNS SS CBIAS 1 mF VOUT COUT CSS Optional Figure 29. Typical Application Circuit for the TPS742xx (Fixed Voltage) A fixed voltage version of the TPS742xx has a sense pin (SNS) so that the device can monitor its output voltage at the load device pin(s) as closely as possible. Unlike other TI fixed-voltage LDOs, however, this pin must not be left floating; it must be connected to an output node. See the TI application report, Ultimate Regulation of with Fixed Output Versions of the TPS742xx, TPS743xx, and TPS744xx (literature number SBVA024), available for download from the TI web site. INPUT, OUTPUT, AND BIAS CAPACITOR REQUIREMENTS ADJUSTABLE VOLTAGE PART AND SETTING VIN FIXED VOLTAGE AND SENSE PIN ) The device does not require any output capacitor for stability. If an output capacitor is needed, the device is designed to be stable for all available types and values of output capacitance. The device is also stable with multiple capacitors in parallel, which can be of any type or value. The capacitance required on the IN and BIAS pins is strongly dependent on the input supply source impedance. To counteract any inductance in the input, the minimum recommended capacitor for VIN and VBIAS is 1mF. If VIN and VBIAS are connected to the same supply, the recommended minimum capacitor for VBIAS is 4.7mF. Good quality, low ESR capacitors should be used on the input; ceramic X5R and X7R capacitors are preferred. These capacitors should be placed as close the pins as possible for optimum performance. Figure 28. Typical Application Circuit for the TPS74201 (Adjustable Version) space space 12 Submit Documentation Feedback Copyright © 2005–2010, Texas Instruments Incorporated TPS742xx www.ti.com SBVS064L – DECEMBER 2005 – REVISED NOVEMBER 2010 TRANSIENT RESPONSE The TPS742xx was designed to have transient response within 5% for most applications without any output capacitor. In some cases, the transient response may be limited by the transient response of the input supply. This limitation is especially true in applications where the difference between the input and output is less than 300mV. In this case, adding additional input capacitance improves the transient response much more than just adding additional output capacitance would do. With a solid input supply, adding additional output capacitance reduces undershoot and overshoot during a transient at the expense of a slightly longer VOUT recovery time. Refer to Figure 24 in the Typical Characteristics section. Since the TPS742xx is stable without an output capacitor, many applications may allow for little or no capacitance at the LDO output. For these applications, local bypass capacitance for the device under power may be sufficient to meet the transient requirements of the application. This design reduces the total solution cost by avoiding the need to use expensive high-value capacitors at the LDO output. DROPOUT VOLTAGE The TPS742xx offers industry-leading dropout performance, making it well-suited for high-current low VIN/low VOUT applications. The extremely low dropout of the TPS742xx allows the device to be used in place of a DC/DC converter and still achieve good efficiencies. This efficiency allows the user to rethink the power architecture for their applications to achieve the smallest, simplest, and lowest cost solution. There are two different specifications for dropout voltage with the TPS742xx. The first specification (illustrated in Figure 30) is referred to as VIN Dropout and is for users who wish to apply an external bias voltage to achieve low dropout. This specification assumes that VBIAS is at least 1.62V above VOUT, which is the case for VBIAS when powered by a 3.3V rail with 5% tolerance and with VOUT = 1.5V. If VBIAS is higher than 3.3V × 0.95 or VOUT is less than 1.5V, VIN dropout is less than specified. Copyright © 2005–2010, Texas Instruments Incorporated BIAS IN Reference VBIAS = 5V ± 5% VIN = 1.8V VOUT = 1.5V IOUT = 1.5A Efficiency = 83% OUT VOUT FB Simplified Block Diagram Figure 30. Typical Application of the TPS742xx Using an Auxiliary Bias Rail The second specification (shown in Figure 31) is referred to as VBIAS Dropout and is for users who wish to tie IN and BIAS together. This option allows the device to be used in applications where an auxiliary bias voltage is not available or low dropout is not required. Dropout is limited by BIAS in these applications because VBIAS provides the gate drive to the pass FET and therefore must be 1.4V above VOUT. Because of this usage, IN and BIAS tied together easily consume huge power. Pay attention not to exceed the power rating of the IC package. VIN BIAS Reference IN VBIAS = 3.3V ± 5% VIN = 3.3V ± 5V VOUT = 1.5V IOUT = 1.5A Efficiency = 45% OUT VOUT FB Simplified Block Diagram Figure 31. Typical Application of the TPS742xx Without an Auxiliary Bias Submit Documentation Feedback 13 TPS742xx SBVS064L – DECEMBER 2005 – REVISED NOVEMBER 2010 www.ti.com PROGRAMMABLE SOFT-START SEQUENCING REQUIREMENTS The TPS742xx features a programmable, monotonic, voltage-controlled soft-start that is set with an external capacitor (CSS). This feature is important for many applications because it eliminates power-up initialization problems when powering FPGAs, DSPs, or other processors. The controlled voltage ramp of the output also reduces peak inrush current during start-up, minimizing start-up transients to the input power bus. The device can have VIN, VBIAS, and VEN sequenced in any order without causing damage to the device. However, for the soft-start function to work as intended, certain sequencing rules must be applied. Enabling the device after VIN and VBIAS are present is preferred, and can be accomplished using a digital output from a processor or supply supervisor. An analog signal from an external RC circuit, as shown in Figure 32, can also be used as long as the delay time is long enough for VIN and VBIAS to be present. To achieve a linear and monotonic soft-start, the TPS742xx error amplifier tracks the voltage ramp of the external soft-start capacitor until the voltage exceeds the internal reference. The soft-start ramp time depends on the soft-start charging current (ISS), soft-start capacitance (CSS), and the internal reference voltage (VREF), and can be calculated using Equation 1: ǒVREF CSSǓ t SS + I SS (1) If large output capacitors are used, the device current limit (ICL) and the output capacitor may set the start-up time. In this case, the start-up time is given by Equation 2: t SSCL + ǒVOUT(NOM) COUTǓ I CL(MIN) (2) VOUT(NOM) is the nominal set output voltage as set by the user, COUT is the output capacitance, and ICL(MIN) is the minimum current limit for the device. In applications where monotonic startup is required, the soft-start time given by Equation 1 should be set to be greater than Equation 2. The maximum recommended soft-start capacitor is 0.015mF. Larger soft-start capacitors can be used and will not damage the device; however, the soft-start capacitor discharge circuit may not be able to fully discharge the soft-start capacitor when enabled. Soft-start capacitors larger than 0.015mF could be a problem in applications where the user needs to rapidly pulse the enable pin and still requires the device to soft-start from ground. CSS must be low-leakage; X7R, X5R, or C0G dielectric materials are preferred. Refer to Table 2 for suggested soft-start capacitor values. 14 Submit Documentation Feedback VIN IN VOUT OUT CIN 1mF R1 BIAS TPS74201 FB R2 R VBIAS CBIAS 1mF EN C GND SS CSS Figure 32. Soft-Start Delay Using an RC Circuit on Enable If a signal is not available to enable the device after IN and BIAS, simply connecting EN to IN is acceptable for most applications as long as VIN is greater than 1.1V and the ramp rate of VIN and VBIAS is faster the set soft-start ramp rate. If the ramp rate of the input sources is slower than the set soft-start time, the output will track the slower supply minus the dropout voltage until it reaches the set output voltage. If EN is connected to BIAS, the device will soft-start as programmed provided that VIN is present before VBIAS. If VBIAS and VEN are present before VIN is applied and the set soft-start time has expired then VOUT will track VIN. NOTE: When VBIAS and VEN are present and VIN is not supplied, this device outputs approximately 50mA of current from OUT. Although this condition will not cause any damage to the device, the output current may charge up the OUT node if total resistance between OUT and GND (including external feedback resistors) is greater than 10kΩ. Copyright © 2005–2010, Texas Instruments Incorporated TPS742xx www.ti.com SBVS064L – DECEMBER 2005 – REVISED NOVEMBER 2010 OUTPUT NOISE The TPS742xx provides low output noise when a soft-start capacitor is used. When the device reaches the end of the soft-start cycle, the soft-start capacitor serves as a filter for the internal reference. By using a 0.001mF soft-start capacitor, the output noise is reduced by half and is typically 30mVRMS for a 1.2V output (10Hz to 100kHz). Because most of the output noise is generated by the internal reference, the noise is a function of the set output voltage. The RMS noise with a 0.001mF soft-start capacitor is given in Equation 3. ǒmVV Ǔ V NǒmVRMSǓ + 25 RMS V OUT(V) (3) The low output noise of the TPS742xx makes it a good choice for powering transceivers, PLLs, or other noise-sensitive circuitry. ENABLE/SHUTDOWN The enable (EN) pin is active high and is compatible with standard digital signaling levels. VEN below 0.4V turns the regulator off, while VEN above 1.1V turns the regulator on. Unlike many regulators, the enable circuitry has hysteresis and deglitching for use with relatively slow-ramping analog signals. This configuration allows the TPS742xx to be enabled by connecting the output of another supply to the EN pin. The enable circuitry typically has 50mV of hysteresis and a deglitch circuit to help avoid on-off cycling because of small glitches in the VEN signal. The enable threshold is typically 0.8V and varies with temperature and process variations. Temperature variation is approximately –1mV/°C; therefore, process variation accounts for most of the variation in the enable threshold. If precise turn-on timing is required, a fast rise-time signal should be used to enable the TPS742xx. Copyright © 2005–2010, Texas Instruments Incorporated If not used, EN can be connected to either IN or BIAS. If EN is connected to IN, it should be connected as close as possible to the largest capacitance on the input to prevent voltage droops on that line from triggering the enable circuit. POWER-GOOD (QFN Package Only) The power-good (PG) pin is an open-drain output and can be connected to any 5.5V or lower rail through an external pull-up resistor. This pin requires at least 1.1V on VBIAS in order to have a valid output. The PG output is high-impedance when VOUT is greater than VIT + VHYS. If VOUT drops below VIT or if VBIAS drops below 1.9V, the open-drain output turns on and pulls the PG output low. The PG pin also asserts when the device is disabled. The recommended operating condition of PG pin sink current is up to 1mA, so the pull-up resistor for PG should be in the range of 10kΩ to 1MΩ. PG is only provided on the QFN package. If output voltage monitoring is not needed, the PG pin can be left floating. INTERNAL CURRENT LIMIT The TPS742xx features a factory-trimmed, accurate current limit that is flat over temperature and supply voltage. The current limit allows the device to supply surges of up to 1.8A and maintain regulation. The current limit responds in about 10ms to reduce the current during a short-circuit fault. Recovery from a short-circuit condition is well-controlled and results in very little output overshoot when the load is removed. See Figure 27 in the Typical Characteristics section for a graph of IOUT versus VOUT performance. The internal current limit protection circuitry of the TPS742xx is designed to protect against overload conditions. It is not intended to allow operation above the rated current of the device. Continuously running the TPS742xx above the rated current degrades device reliability. Submit Documentation Feedback 15 TPS742xx SBVS064L – DECEMBER 2005 – REVISED NOVEMBER 2010 THERMAL PROTECTION Thermal protection disables the output when the junction temperature rises to approximately +160°C, allowing the device to cool. When the junction temperature cools to approximately +140°C, the output circuitry is enabled. Depending on power dissipation, thermal resistance, and ambient temperature the thermal protection circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a result of overheating. Activation of the thermal protection circuit indicates excessive power dissipation or inadequate heatsinking. For reliable operation, junction temperature should be limited to +125°C maximum. To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until thermal protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should trigger at least +40°C above the maximum expected ambient condition of the application. This condition produces a worst-case junction temperature of +125°C at the highest expected ambient temperature and worst-case load. The internal protection circuitry of the TPS742xx is designed to protect against overload conditions. It is not intended to replace proper heatsinking. Continuously running the TPS742xx into thermal shutdown degrades device reliability. www.ti.com Power dissipation of the device depends on input voltage and load conditions and can be calculated using Equation 4: P D + ǒVIN * VOUTǓ Knowing the device power dissipation and proper sizing of the thermal plane that is connected to the tab or pad is critical to avoiding thermal shutdown and ensuring reliable operation. white space 16 Submit Documentation Feedback (4) Power dissipation can be minimized and greater efficiency can be achieved by using the lowest possible input voltage necessary to achieve the required output voltage regulation. On the QFN (RGW) package, the primary conduction path for heat is through the exposed pad to the printed circuit board (PCB). The pad can be connected to ground or be left floating; however, it should be attached to an appropriate amount of copper PCB area to ensure the device will not overheat. On the DDPAK (KTW) package, the primary conduction path for heat is through the tab to the PCB. That tab should be connected to ground. The maximum junction-to-ambient thermal resistance depends on the maximum ambient temperature, maximum device junction temperature, and power dissipation of the device and can be calculated using Equation 5: ()125OC * T A) R qJA + PD (5) Knowing the maximum RqJA, the minimum amount of PCB copper area needed for appropriate heatsinking can be estimated using Figure 33. 120 LAYOUT RECOMMENDATIONS AND POWER DISSIPATION 100 80 qJA (°C/W) An optimal layout can greatly improve transient performance, PSRR, and noise. To minimize the voltage droop on the input of the device during load transients, the capacitance on IN and BIAS should be connected as close as possible to the device. This capacitance also minimizes the effects of parasitic inductance and resistance of the input source and can therefore improve stability. To achieve optimal transient performance and accuracy, the top side of R1 in Figure 28 should be connected as close as possible to the load. If BIAS is connected to IN it is recommended to connect BIAS as close to the sense point of the input supply as possible. This connection minimizes the voltage droop on BIAS during transient conditions and can improve the turn-on response. I OUT 60 qJA (RGW) 40 20 qJA (KTW) 0 0 1 2 3 4 5 7 6 8 9 10 2 Board Copper Area (in ) Note: qJA value at board size of 9in2 (that is, 3in × 3in) is a JEDEC standard. Figure 33. qJA vs Board Size Figure 33 shows the variation of qJA as a function of ground plane copper area in the board. It is intended only as a guideline to demonstrate the effects of heat spreading in the ground plane and should not be used to estimate actual thermal performance in real application environments. Copyright © 2005–2010, Texas Instruments Incorporated TPS742xx www.ti.com SBVS064L – DECEMBER 2005 – REVISED NOVEMBER 2010 NOTE: When the device is mounted on an application PCB, it is strongly recommended to use ΨJT and ΨJB, as explained in the Estimating Junction Temperature section. ESTIMATING JUNCTION TEMPERATURE Using the thermal metrics ΨJT and ΨJB, shown in the Thermal Information table, the junction temperature can be estimated with corresponding formulas (given in Equation 6). For backwards compatibility, an older qJC,Top parameter is listed as well. YJT: TJ = TT + YJT · PD YJB: TJ = TB + YJB · PD (6) Where PD is the power dissipation shown by Equation 4, TT is the temperature at the center-top of the IC package, and TB is the PCB temperature measured 1mm away from the IC package on the PCB surface (as Figure 34 shows). NOTE: Both TT and TB can be measured on actual application boards using a thermo-gun (an infrared thermometer). For more information about measuring TT and TB, see the application note Using New Thermal Metrics (SBVA025), available for download at www.ti.com. (1) TT on top of IC TB on PCB TT on top of IC 1mm TB on PCB surface (2) 1mm (a) Example RGW (QFN) Package Measurement (1) TT is measured at the center of both the X- and Y-dimensional axes. (2) TB is measured below the package lead on the PCB surface. (b) Example KTW (DDPAK) Package Measurement Figure 34. Measuring Points for TT and TB Copyright © 2005–2010, Texas Instruments Incorporated Submit Documentation Feedback 17 TPS742xx SBVS064L – DECEMBER 2005 – REVISED NOVEMBER 2010 Looking at Figure 35, the RGW package thermal performance has negligible dependency on board size. The KTW package, however, does have a measurable dependency on board size. This dependency exists because the package shape is not point-symmetric to an IC center. In the KTW package, for example (see Figure 34), silicon is not beneath the measuring point of TT which is the center of the X and Y dimension, so that ΨJT has a dependency. Also, because of that non-point-symmetry, device heat distribution on the PCB is not point-symmetric, either, so that ΨJB has a dependency. space 18 12 10 YJT and YJB (°C/W) Compared with qJA, the new thermal metrics ΨJT and ΨJB are less independent of board size, but they do have a small dependency. Figure 35 shows characteristic performance of ΨJT and ΨJB versus board size. www.ti.com YJB (RGW) 8 YJB (KTW) 6 4 YJT (KTW) 2 YJT (RGW) 0 0 2 4 6 8 10 2 Board Copper Area (in ) Figure 35. ΨJT and ΨJB vs Board Size For a more detailed discussion of why TI does not recommend using qJC,Top to determine thermal characteristics, refer to the application note Using New Thermal Metrics (SBVA025), available for download at www.ti.com. Also, refer to the application note IC Package Thermal Metrics (SPRA953) (also available on the TI web site) for further information. Submit Documentation Feedback Copyright © 2005–2010, Texas Instruments Incorporated TPS742xx www.ti.com SBVS064L – DECEMBER 2005 – REVISED NOVEMBER 2010 REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision K (August, 2010) to Revision L • Page Corrected equation for Table 2 ............................................................................................................................................. 6 Changes from Revision J (December, 2009) to Revision K Page • Replaced the Dissipation Ratings table with the Thermal Information table ........................................................................ 3 • Revised Layout Recommendations and Power Dissipation section ................................................................................... 16 • Changed final paragraph of Power Dissipation section ...................................................................................................... 16 • Revised Estimating Junction Temperature section ............................................................................................................. 17 Copyright © 2005–2010, Texas Instruments Incorporated Submit Documentation Feedback 19 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) TPS74201KTWR ACTIVE DDPAK/ TO-263 KTW 7 500 Green (RoHS & no Sb/Br) CU SN Level-3-245C-168 HR -40 to 85 TPS74201 TPS74201KTWRG3 ACTIVE DDPAK/ TO-263 KTW 7 500 Green (RoHS & no Sb/Br) CU SN Level-3-245C-168 HR -40 to 85 TPS74201 TPS74201KTWT ACTIVE DDPAK/ TO-263 KTW 7 50 Green (RoHS & no Sb/Br) CU SN Level-3-245C-168 HR -40 to 85 TPS74201 TPS74201KTWTG3 ACTIVE DDPAK/ TO-263 KTW 7 50 Green (RoHS & no Sb/Br) CU SN Level-3-245C-168 HR -40 to 85 TPS74201 TPS74201RGWR ACTIVE VQFN RGW 20 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS 74201 TPS74201RGWRG4 ACTIVE VQFN RGW 20 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS 74201 TPS74201RGWT ACTIVE VQFN RGW 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS 74201 TPS74201RGWTG4 ACTIVE VQFN RGW 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS 74201 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 (4) Multiple Top-Side Markings will be inside parentheses. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 9-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS74201KTWR DDPAK/ TO-263 KTW 7 500 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2 TPS74201KTWT DDPAK/ TO-263 KTW 7 50 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2 TPS74201RGWR VQFN RGW 20 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 TPS74201RGWT VQFN RGW 20 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 9-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS74201KTWR DDPAK/TO-263 KTW 7 500 367.0 367.0 45.0 TPS74201KTWT DDPAK/TO-263 KTW 7 50 367.0 367.0 45.0 TPS74201RGWR VQFN RGW 20 3000 367.0 367.0 35.0 TPS74201RGWT VQFN RGW 20 250 210.0 185.0 35.0 Pack Materials-Page 2 MECHANICAL DATA MPSF015 – AUGUST 2001 KTW (R-PSFM-G7) PLASTIC FLANGE-MOUNT 0.410 (10,41) 0.385 (9,78) 0.304 (7,72) –A– 0.006 –B– 0.303 (7,70) 0.297 (7,54) 0.0625 (1,587) H 0.055 (1,40) 0.0585 (1,485) 0.300 (7,62) 0.064 (1,63) 0.045 (1,14) 0.252 (6,40) 0.056 (1,42) 0.187 (4,75) 0.370 (9,40) 0.179 (4,55) 0.330 (8,38) H 0.296 (7,52) A 0.605 (15,37) 0.595 (15,11) 0.012 (0,305) C 0.000 (0,00) 0.019 (0,48) 0.104 (2,64) 0.096 (2,44) H 0.017 (0,43) 0.050 (1,27) C C F 0.034 (0,86) 0.022 (0,57) 0.010 (0,25) M B 0.026 (0,66) 0.014 (0,36) 0°~3° AM C M 0.183 (4,65) 0.170 (4,32) 4201284/A 08/01 NOTES: A. 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