EPA120D High Efficiency Heterojunction Power FET UPDATED 01/13/2006 FEATURES • • • • • • +29.5dBm TYPICAL OUTPUT POWER 19.5dB TYPICAL POWER GAIN AT 2GHz 0.5 X 1200 MICRON RECESSED “MUSHROOM” GATE Si3N4 PASSIVATION AND PLATED HEAT SINK ADVANCED EPITAXIAL DOPING PROFILE PROVIDES HIGH POWER EFFICIENCY, LINEARITY AND RELIABILITY Idss SORTED IN 30mA PER BIN RANGE Chip Thickness: 75 ± 20 microns All Dimensions In Microns ELECTRICAL CHARACTERISTICS (Ta = 25 OC) Caution! ESD sensitive device. SYMBOLS MIN TYP 28.0 29.5 29.5 19.5 14.5 PARAMETERS/TEST CONDITIONS Output Power at 1dB Compression f= 2GHz Vds=8V, Ids=50% Idss f= 4GHz Gain at 1dB Compression f= 2GHz Vds=8V, Ids=50% Idss f= 4GHz Power Added Efficiency at 1dB Compression Vds=8V, Ids=50% Idss f=2GHz P1dB G1dB PAE 18.0 MAX UNIT dBm dB 50 % Idss Saturated Drain Current Vds=3V, Vgs=0V 210 360 510 mA Gm Transconductance Vds=3V, Vgs=0V 240 380 Vp Pinch-off Voltage Vds=3V,Ids=3.6mA BVgd Drain Breakdown Voltage Igd=1.2mA -13 -15 V BVgs Source Breakdown Voltage Igs=1.2mA -7 -14 V Rth Thermal Resistance (Au-Sn Eutectic Attach) mS -1.0 -2.5 40 45 V o C/W MAXIMUM RATINGS AT 25OC SYMBOLS Vds Vgs Igsf Igsr Pin Tch Tstg Pt Note: PARAMETERS Drain-Source Voltage Gate-Source Voltage Forward Gate Current Reserve Gate Current Input Power Channel Temperature Storage Temperature Total Power Dissipation ABSOLUTE1 CONTINUOUS2 12V -5V 5.4 mA 0.9 mA 26 dBm 175oC -65/175oC 3.3 W 8V -3V 1.8 mA 0.3 mA @ 3dB Compression 175oC -65/175oC 3.3 W 1. Exceeding any of the above ratings may result in permanent damage. 2. Exceeding any of the above ratings may reduce MTTF below design goals. Specifications are subject to change without notice. Excelics Semiconductor, Inc. 310 De Guigne Drive, Sunnyvale, CA 94085 Phone: 408-737-1711 Fax: 408-737-1868 Web: www.excelics.com page 1 of 2 Revised January 2006 EPA120D High Efficiency Heterojunction Power FET UPDATED 01/13/2006 S-PARAMETERS 8V, 1/2 Idss FREQ (GHz) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Note: --- S11 ----- S21 --MAG ANG MAG ANG 0.891 -106.9 15.439 119.2 0.858 -143.2 9.009 97.3 0.854 -159.9 6.233 84.9 0.850 -170.6 4.775 75.1 0.856 -178.8 3.800 66.3 0.856 174.1 3.195 58.6 0.858 168.5 2.766 51.0 0.863 162.7 2.424 43.9 0.870 157.6 2.140 36.7 0.872 153.1 1.926 30.2 0.880 148.6 1.738 23.4 0.889 145.4 1.565 17.0 0.890 142.4 1.412 10.7 0.898 140.3 1.289 5.2 0.910 138.5 1.176 0.0 0.905 136.4 1.080 -5.4 0.909 135.0 0.991 -9.9 0.903 133.4 0.922 -14.9 0.901 130.8 0.874 -19.6 0.909 127.3 0.821 -24.3 --- S12 --MAG ANG 0.029 40.8 0.034 27.9 0.036 26.8 0.037 25.2 0.039 29.6 0.041 31.4 0.044 34.1 0.046 35.9 0.048 36.0 0.054 37.5 0.056 38.3 0.059 40.9 0.065 37.4 0.070 36.2 0.075 38.6 0.080 36.8 0.083 36.9 0.092 35.4 0.100 33.4 0.109 32.7 --- S22 --MAG ANG 0.290 -64.3 0.219 -86.7 0.207 -97.0 0.212 -103.1 0.228 -112.6 0.245 -117.0 0.258 -121.6 0.279 -127.2 0.298 -133.0 0.324 -139.4 0.352 -146.3 0.383 -152.7 0.413 -160.3 0.459 -165.7 0.487 -170.9 0.529 -175.5 0.557 -179.2 0.581 177.8 0.607 173.1 0.614 168.7 The data included 0.7 mils diameter Au bonding wires: 1 gate wires, 20 mils each; 1 drain wires, 12 mils each; 4 source wires, 7 mils each. Specifications are subject to change without notice. Excelics Semiconductor, Inc. 310 De Guigne Drive, Sunnyvale, CA 94085 Phone: 408-737-1711 Fax: 408-737-1868 Web: www.excelics.com page 2 of 2 Revised January 2006