TI TPS61310YFF

TPS61310
www.ti.com
SLVS978 – MARCH 2010
2 TM
1.5A Multiple LED Camera Flash and Video Light Driver With I C Compatible Interface
Check for Samples: TPS61310
FEATURES
1
• Operational Modes:
– Video Light and Flash Strobe
– Voltage Regulated Converter: 3.8V...5.7V
with Down Mode
– Standby: 2mA (typ.)
• LED VF Measurement
• Power-Save Mode for Improved Efficiency at
Low Output Power, Up to 95% Efficiency
• I2C Compatible Interface up to 3.4Mbits/s
• Dual Wire Camera Module Interface
• Zero Latency Tx-Masking Input
• Hardware Reset Input
• Privacy Indicator LED Output
• GPIO/Power Good Output
• Various Safe Operation and Robust Handling
Features:
– LED Temperature Monitoring
– Open/Short LED Detection/Protection
– Integrated LED Safety Timer
– Automatic Battery Voltage Droop
Monitoring and Protection
– Smooth LED Current Ramp-Up/Down
– Undervoltage Lockout
• Total Solution Size of Less Than 25mm2
• Available in a 20-Pin NanoFree™ (CSP)
234
DESCRIPTION
The TPS6131x family is an integrated solution with a
wide feature set for driving up to three LEDs for
still-camera flash strobe and video-camera lighting
applications. It is based on a high efficiency
synchronous boost topology with combinable current
sinks to drive up to three white LEDs in parallel. The
2MHz switching frequency allows the use of small
and low-profile 2.2mH inductors. To optimize overall
efficiency, the device operates with a low
LED-feedback voltage and regulated output-voltage
adaptation.
The device integrates a control scheme that
automatically optimizes the LED current flash budget
as a function of the battery voltage condition.
The TPS6131x not only operates as a regulated
current source, but also as a standard voltage boost
regulator. The device enters power-save mode
operation at light load currents to maintain high
efficiency over the entire load current range. These
operating modes can be useful to supply other high
power devices in the system (e.g. hands-free audio
PA).
To simplify video light and flash synchronization with
the camera module, the device offers a dedicated
control interface (STRB0, STRB1) for zero latency
LED turn-on time.
TPS61310
L
SW
SW
VOUT
2.2 mH
AVIN
APPLICATIONS
•
•
•
•
Single/Dual/Triple White LED Flash Supply for
Cell Phones and Smart-Phones
Video Lighting for Digital Video Applications
General Lighting Applications
Audio Amplifier Power Supply
2.5 V..5.5 V
CO
CI
4.7 mF
10mF
D1
D2
NRESET
LED1
I2C I/F
STRB0
LED2
STRB1
LED3
SCL
SDA
INDLED
Privacy
Indicator
Tx-MASK
TS
GPIO/PG
NTC
AGND
AGND
PGND
PGND
Figure 1. Typical Application
1
2
3
4
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
I2C is a trademark of Koninklijke Philips Electronics N.V..
I2C is a trademark of NXP Semiconductors.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
TPS61310
SLVS978 – MARCH 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Table 1. AVAILABLE OPTIONS
PART NUMBER
(1)
PACKAGE MARKING
PACKAGE
61310
CSP-20
TPS61310YFF
(1)
DEVICE SPECIFIC FEATURES (2)
The YFF package is available in tape and reel. Add R suffix (TPS6131xYFFR) to order quantities of 3000 parts per reel, T suffix for 250
parts per reel.
For more details, refer to the section Application Diagrams.
(2)
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
Voltage range on AVIN, VOUT, SW, LED1, LED2, LED3
(1)
(2)
Voltage range on SCL, SDA, STRB0, STRB1, NRESET, GPIO/PG (2)
VI
Voltage range on Tx-MASK, TS
(2)
Current on GPIO/PG
Power dissipation
TA
TJ
Operating ambient temperature range
(MAX)
Maximum operating junction temperature
Storage temperature range
(1)
(2)
(3)
(4)
(4)
–0.3 to 7
V
–0.3 to 7
V
–0.3 to 7
V
±25
mA
–40 to 85
°C
150
°C
–65 to 150
°C
2
kV
Charge device model
500
V
Machine model
100
V
Human body model
ESD rating
UNIT
Internally limited
(3)
Tstg
VALUE
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature [TA(max)] is dependent on the maximum operating junction temperature [TJ(max)], the
maximum power dissipation of the device in the application [PD(max)], and the junction-to-ambient thermal resistance of the part/package
in the application (qJA), as given by the following equation: TA(max) = TJ(max) – (qJA × PD(max))
The human body model is a 100-pF capacitor discharged through a 1.5kΩ resistor into each pin. The machine model is a 200-pF
capacitor discharged directly into each pin.
DISSIPATION RATINGS
(1)
(2)
2
PACKAGE
THERMAL RESISTANCE (1)
qJA
THERMAL RESISTANCE (1)
qJB
POWER RATING
TA = 25°C
DERATING FACTOR
ABOVE (2) TA = 25°C
YFF
71°C/W
21°C/W
1.4 W
14mW/°C
Simulated with high-K board
Maximum power dissipation is a function of TJ(max), qJA and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TA)/ qJA.
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TPS61310
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SLVS978 – MARCH 2010
ELECTRICAL CHARACTERISTICS
Unless otherwise noted the specification applies for VIN = 3.6V over an operating junction temp. –40°C ≤ TJ ≤ 125°C; Circuit
of Parameter Measurement Information section (unless otherwise noted). Typical values are for TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
2.5
5.5
UNIT
SUPPLY CURRENT
VIN
Input voltage range
IQ
Operating quiescent current into AVIN
IOUT = 0 mA, device not switching (Power Safe
Mode)
–40°C ≤ TJ ≤ +85°C
590
IOUT(DC) = 0mA, PWM operation
VOUT = 4.95V, voltage regulation mode
11.3
ISD
Shutdown current
–40°C ≤ TJ ≤ +85°C
VUVLO
Undervoltage lockout threshold
(analog circuitry)
VIN falling
V
mA
700
mA
1
5
2.3
2.35
mA
V
OUTPUT
Output voltage range
VOUT
OVP
Current regulation mode
VIN
5.5
V
Voltage regulation mode
3.825
5.7
V
–2%
2%
Internal feedback voltage accuracy
2.5V ≤ VIN ≤ 4.8V, –20°C ≤ TJ ≤ +125°C
Boost mode, PWM voltage regulation
Power-save mode ripple voltage
IOUT = 10 mA
Output overvoltage protection
Output overvoltage protection hysteresis
0.015 VOUT
VP-P
VOUT rising, 0000 ≤ OV[3:0] ≤ 0100
4.5
4.65
4.8
V
VOUT rising, 0101 ≤ OV[3:0] ≤ 1111
5.8
6.0
6.2
V
VOUT falling
0.15
V
POWER SWITCH
rDS(on)
Ilkg(SW)
Ilim
Switch MOSFET on-resistance
VOUT = VGS = 3.6 V
90
Rectifier MOSFET on-resistance
VOUT = VGS = 3.6 V
135
Leakage into SW
VOUT = 0V, SW = 3.6V, –40°C ≤ TJ ≤ +85°C
0.3
Rectifier valley current limit (open-loop)
VOUT = 4.95V
–20°C ≤ TJ ≤ +85°C
PWM operation, relative to selected ILIM
–15
mΩ
mΩ
4
mA
+15
%
OSCILLATOR
fOSC
Oscillator frequency
fACC
Oscillator frequency
1.92
–10
MHz
+7
%
THERMAL SHUTDOWN, HOT DIE DETECTOR
Thermal shutdown (1)
Thermal shutdown hysteresis
140
(1)
°C
20
Hot die detector accuracy (1)
(1)
160
–8
°C
8
°C
Verified by characterization. Not tested in production.
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ELECTRICAL CHARACTERISTICS (Continued)
Unless otherwise noted the specification applies for VIN = 3.6V over an operating junction temp. –40°C ≤ TJ ≤ 125°C; Circuit
of Parameter Measurement Information section (unless otherwise noted). Typical values are for TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
0.4V ≤ VLED1/3 ≤ 2.0V,
0mA ≤ ILED1/3 ≤ 100mA, TJ = +85°C
–10
+10
%
0.4V ≤ VLED1/3 ≤ 2.0V,
100mA < ILED1/3 ≤ 400mA, TJ = +85°C
–7.5
+7.5
%
0.4V ≤ VLED2 ≤ 2.0V,
0mA ≤ ILED2 ≤ 250mA, TJ = +85°C
–10
+10
%
0.4V ≤ VLED2 ≤ 2.0V,
250mA ≤ ILED2 ≤ 800mA, TJ = +85°C
–7.5
+7.5
%
–10
+10
%
LED CURRENT REGULATOR
LED1/3 current accuracy
LED2 current accuracy
(1)
(1)
LED1/3 current matching
(1)
LED1/2/3 current temperature
coefficient
INDLED current accuracy
0.05
1.5V ≤ (VIN-VINDLED) ≤ 2.5V
2.6mA ≤ IINDLED ≤ 15.8mA, TJ = +25°C
–20
INDLED current temperature
coefficient
VDO
%/°C
+20
0.05
LED1/2/3 sense voltage
ILED1-3 = full-scale current
VOUT dropout voltage
IOUT = -15.8mA, device not switching
LED1/2/3 input leakage current
VLED1/2/3 = VOUT = 5V, –40°C ≤ TJ ≤ +85°C
INDLED input leakage current
VINDLED = 0V, –40°C ≤ TJ ≤ +85°C
%
%/°C
400
mV
200
mV
0.1
4
mA
0.1
1
mA
LED TEMPERATURE MONITORING
IO(TS) Temperature Sense Current Source
Thermistor bias current
TS Resistance (Warning
Temperature)
LEDWARN bit = 1
TS Resistance (Hot Temperature)
LEDHOT bit = 1
23.8
mA
39
44.5
50
kΩ
12.5
14.5
16.5
kΩ
SDA, SCL, GPIO/PG, Tx-MASK, STRB0, STRB1, NRESET
V(IH)
High-level input voltage
V(IL)
Low-level input voltage
V(OL)
1.2
V
0.4
V
Low-level output voltage (SDA)
IOL = 8mA
0.3
V
Low-level output voltage (GPIO)
DIR = 1, IOL = 5mA
0.3
V
0.1
mA
V(OH) High-level output voltage (GPIO)
DIR = 1, GPIOTYPE = 0, IOH = 8mA
I(LKG) Logic input leakage current
Input connected to VIN or GND, –40°C ≤ TJ ≤ +85°C
0.01
STRB0, STRB1 pull-down resistance
STRB0, STRB1≤ 0.4 V
400
kΩ
NRESET pull-down resistance
NRESET ≤ 0.4 V
400
kΩ
Tx-MASK pull-down resistance
Tx-MASK ≤ 0.4 V
400
kΩ
SDA Input Capacitance
SDA = VIN or GND
9
pF
SCL Input Capacitance
SCL = VIN or GND
4
pF
GPIO/PG Input Capacitance
DIR = 0, GPIO/PG = VIN or GND
9
pF
STRB0 Input Capacitance
STRB0 = VIN or GND
3
pF
STRB1 Input Capacitance
STRB1 = VIN or GND
3
pF
NRESET Input Capacitance
NRESET = VIN or GND
3.5
pF
Tx-MASK Input Capacitance
Tx-MASK = VIN or GND
4
pF
RPD
C(IN)
(1)
4
VIN–0.4
V
Verified by characterization. Not tested in production.
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TPS61310
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SLVS978 – MARCH 2010
ELECTRICAL CHARACTERISTICS (Continued)
Unless otherwise noted the specification applies for VIN = 3.6V over an operating junction temp. –40°C ≤ TJ ≤ 125°C; Circuit
of Parameter Measurement Information section (unless otherwise noted). Typical values are for TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TIMING
tNRESET
Reset pulse width
ms
Start-up time [ref to verified by char]
1.2
ms
LED current settling time (1) triggered
by a rising edge on STRB0
MODE_CTRL[1:0] = 10
ILED2 = from 0mA to 950mA
500
ms
20
ms
LED current settling time
by Tx-MASK
(1)
10
From shutdown into video light mode
ILED = 150mA
(1)
triggered
MODE_CTRL[1:0] = 10
ILED2 = from 950mA to 150mA
Settling time to ±15% of the target value.
I2C INTERFACE TIMING CHARACTERISTICS (1)
PARAMETER
f(SCL)
SCL Clock Frequency
TEST CONDITIONS
MAX
UNIT
Standard mode
MIN
100
kHz
Fast mode
400
kHz
High-speed mode (write operation), CB – 100pF max
3.4
MHz
High-speed mode (read operation), CB – 100pF max
3.4
MHz
High-speed mode (write operation), CB – 400pF max
1.7
MHz
1.7
MHz
High-speed mode (read operation), CB – 400pF max
Bus Free Time Between a STOP and
START Condition
tBUF
Standard mode
4.7
ms
Fast mode
1.3
ms
4
ms
ns
Standard mode
tHD, tSTA
tLOW
Hold Time (Repeated) START
Condition
LOW Period of the SCL Clock
Fast mode
600
High-speed mode
160
ns
Standard mode
4.7
ms
Fast mode
1.3
ms
High-speed mode, CB – 100pF max
160
ns
High-speed mode, CB – 400pF max
320
ns
Standard mode
tHIGH
tSU, tSTA
HIGH Period of the SCL Clock
Setup Time for a Repeated START
Condition
tSU, tDAT Data Setup Time
tHD, tDAT Data Hold Time
tRCL
(1)
Rise Time of SCL Signal
4
ms
Fast mode
600
ns
High-speed mode, CB – 100pF max
60
ns
High-speed mode, CB – 400pF max
120
ns
Standard mode
4.7
ms
Fast mode
600
ns
High-speed mode
160
ns
Standard mode
250
ns
Fast mode
100
ns
High-speed mode
10
ns
Standard mode
0
3.45
ms
Fast mode
0
0.9
ms
High-speed mode, CB – 100pF max
0
70
ns
High-speed mode, CB – 400pF max
0
150
ns
Standard mode
20 + 0.1 CB
1000
ns
Fast mode
20 + 0.1 CB
300
ns
High-speed mode, CB – 100pF max
10
40
ns
High-speed mode, CB – 400pF max
20
80
ns
Specified by design. Not tested in production.
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I2C INTERFACE TIMING CHARACTERISTICS (1) (continued)
PARAMETER
tRCL1
TEST CONDITIONS
Rise Time of SCL Signal After a
Repeated START Condition and After
an Acknowledge BIT
MIN
MAX
UNIT
Standard mode
20 + 0.1 CB
1000
ns
Fast mode
20 + 0.1 CB
300
ns
10
80
ns
High-speed mode, CB – 100pF max
High-speed mode, CB – 400pF max
tFCL
tRDA
tFDA
Fall Time of SCL Signal
Rise Time of SDA Signal
Fall Time of SDA Signal
20
160
ns
Standard mode
20 + 0.1 CB
300
ns
Fast mode
20 + 0.1 CB
300
ns
High-speed mode, CB – 100pF max
10
40
ns
High-speed mode, CB – 400pF max
20
80
ns
Standard mode
20 + 0.1 CB
1000
ns
Fast mode
20 + 0.1 CB
300
ns
High-speed mode, CB – 100pF max
10
80
ns
High-speed mode, CB – 400pF max
20
160
ns
Standard mode
20 + 0.1 CB
300
ns
Fast mode
20 + 0.1 CB
300
ns
High-speed mode, CB – 100pF max
10
80
ns
High-speed mode, CB – 400pF max
20
160
ns
Standard mode
4
ms
Fast mode
600
ns
High-speed mode
160
ns
tSU, tSTO Setup Time for STOP Condition
CB
Capacitive Load for SDA and SCL
400
pF
I2C TIMING DIAGRAMS
SDA
tf
tLOW
tsu;DAT
tr
tf
tBUF
tr
thd;STA
SCL
thd;STA
thd;DAT
S
tsu;STA
tsu;STO
HIGH
Sr
P
S
Figure 2. Serial Interface Timing for F/S-Mode
Sr
Sr P
tfDA
trDA
SDAH
thd;DAT
thd;STA
tsu;STA
tsu;STO
tsu;DAT
SCLH
tfCL
trCL1
See Note A
trCL1
trCL
tHIGH
tLOW
tLOW
tHIGH
See Note A
= MCS Current Source Pull-Up
= R(P) Resistor Pull-Up
Note A: First rising edge of the SCLH signal after Sr and after each acknowledge bit.
Figure 3. Serial Interface Timing for H/S-Mode
6
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DEVICE INFORMATION
Table 2. PIN FUNCTIONS
PIN
I/O
DESCRIPTION
NAME
NO.
AVIN
E4
I
This is the input voltage pin of the device. Connect directly to the input bypass capacitor.
VOUT
A2
O
This is the output voltage pin of the converter.
LED1
E2
I
LED2
E1
I
LED3
E3
I
STRB0
B4
I
LED1/2/3 enable logic input. This pin can be used to enable/disable the high-power LEDs connected to the
device.
STRB0 = LOW: LED1, LED2 and LED3 current regulators are turned off.
STRB0 = HIGH: LED2, LED2 and LED3 current regulators are active. The LED current level (video light or
flash current) is defined according to the STRB1 logic level.
NRESET
B3
I
Master hardware reset input.
NRESET = LOW: The device is forced in shutdown mode and the I2C™ control I/F and all internal control
registers are reset.
NRESET = HIGH: The device is operating normally under the control of the I2C interface.
SCL
B2
I
Serial interface clock line. This pin must not be left floating and must be terminated.
SDA
B1
I/O
Serial interface address/data line. This pin must not be left floating and must be terminated.
GPIO/PG
D4
I/O
This pin can either be configured as a general purpose input/output pin (GPIO) or either as an open-drain or
a push-pull output to signal when the converters output voltage is within the regulation limits (PG). Per
default, the pin is configured as an open-drain power-good output.
TS
C4
I
NTC resistor connection. This pin can be used to monitor the LED temperature. Connect a 220kΩ NTC
resistor from the TS input to ground. In case this functionality is not desired, the TS input should be tied to
AVIN or left floating.
INDLED
A1
O
This pin provides a constant current source to drive low VF LEDs. Connect to LED anode.
STRB1
D3
I
LED current level selection input. Pulling this input high disables the video light watchdog timer.
STRB1 = LOW: flash mode is enabled.
STRB1 = HIGH: video light mode is enabled.
Tx-MASK
C3
I
RF PA synchronization control input. Pulling this pin high turns the LED from flash to video light operation,
thereby reducing almost instantaneously the peak current loading from the battery.
SW
C1
C2
I/O
PGND
D1
D2
Power ground. Connect to AGND underneath IC.
AGND
A3
A4
Analog ground.
LED return input (current sinks). This feedback pin regulates the LED current through the internal sense
resistor by regulating the voltage across it. Connect to the cathode of the white LEDs.
Inductor connection. Drain of the internal power MOSFET. Connect to the switched side of the inductor. SW
is high impedance during shutdown.
PIN ASSIGNMENTS
CSP-20
(TOP VIEW)
CSP-20
(BOTTOM VIEW)
A4
B4
C4
D4
E4
E4
D4
C4
B4
A4
A3
B3
C3
D3
E3
E3
D3
C3
B3
A3
A2
B2
C2
D2
E2
E2
D2
C2
B2
A2
A1
B1
C1
D1
E1
E1
D1
C1
B1
A1
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FUNCTIONAL BLOCK DIAGRAM
SW
AVIN
Undervoltage
Lockout
Bias Supply
Bandgap
OVP
COMPARATOR
VREF = 1.238V
REF
Backgate
Control
VOUT
Hot Die
Indicator
VBAT DROOP
COMPARATOR
TON
Control
ERROR
AMPLIFIER
VREF
Digital
Filter
S
Q
R
Q
CONTROL LOGIC
P
COMPARATOR
BATTERY DROOP
THRESHOLD
VOLTAGE
REGULATION
CURRENT
REGULATION
VLED Sense
SENSE FB
SCL
I2C I/F
LED2
ON/OFF
Max tON Timer
CURRENT
CONTROL
DAC
P
SDA
SENSE FB
LED Current Ramp
(STOP)
Slew-Rate
Controller
Oscillator
LED1
ON/OFF
CURRENT
CONTROL
DAC
P
STRB1
SENSE FB
LED3
STRB0
Tx-MASK
P
NRESET
Low-Side LED Current Regulator
Control
Logic
350 kΩ
AVIN
INDLED
INDC[1:0]
AVIN
High-Side LED Current Regulator
23µA
TS
WARNING
VREF = 1.05V
HOT
VREF = 0.345V
AGND
8
PGND
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TIMER BLOCK DIAGRAM
(GPIO Bit)
Tx-MASK
350 kW
Port Direction
(DIR)
CURRENT REGULATOR MODE – DC LIGHT / FLASH ACTIVE
MODE 0 = LOW
MODE 0 MODE 1 = HIGH
Port Type
(PG)
MODE 1
STRB1
GPIO/PG
0
STRB0
1
1
(GPIO Bit)
350 kW
Safety Timer Trigger
(STT)
Edge Detect
PWROK
Start
Flash/Timer
(SFT)
DC Light
Safety Timer
(11.2s)
MODE 0
MODE 1
0: NORMAL OPERATION
1: DISABLE CURRENT SINK
Start
LED1-3 CURRENT CONTROL
CLOCK
16-bit Prescaler
Safety Timer
0: DC LIGHT CURRENT LEVEL
1: FLASH CURRENT LEVEL
tPULSE
Time-Out (TO)
Dimming
(DIM)
Timer
Value
(STIM)
LED1-3 ON/OFF CONTROL
Duty-Cycle Generator (5% ... 67%)
0: LED1-3 OFF
1: DC LIGHT CURRENT LEVEL
PARAMETER MEASUREMENT INFORMATION
TPS61310
L
SW
SW
VOUT
2.2 mH
AVIN
2.5 V..5.5 V
CO
CI
4.7 mF
10mF
D1
D2
NRESET
LED1
I2C I/F
STRB0
LED2
STRB1
LED3
SCL
SDA
INDLED
Privacy
Indicator
Tx-MASK
TS
GPIO/PG
NTC
AGND
AGND
PGND
PGND
List of Components:
L = 2.2mH, Wuerth Elektronik WE-TPC Series
CI, CO = 10mF 6.3V X5R 0603 – TDK C1605X5R0J106MT
Storage Capacitor = TDK EDLC262020-500mF
NTC = 220kΩ, muRata NCP18WM224J03RB
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TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
LED Power Efficiency
vs. Input Voltage
Figure 4, Figure 5
DC Input Current
vs. Input Voltage
Figure 6
LED Current
vs. LED Pin Headroom Voltage
Figure 7, Figure 8
Figure 9, Figure 10,
Figure 11, Figure 12
LED Current
vs. LED Current Digital Code
INDLED Current
vs. LED Pin Headroom Voltage
Voltage Mode Efficiency
vs. Output Current
Figure 14, Figure 15
DC Output Voltage
vs. Output Current
Figure 16, Figure 17
Maximum Output Current
vs. Input Voltage
DC Pre-Charge Current
vs. Differential Input-Output Voltage
Supply Current
vs. Input Voltage
Figure 13
Figure 18
Figure 19, Figure 20
Figure 21
Temperature Detection Threshold
Figure 22, Figure 23
Junction Temperature
vs. Port Voltage
Figure 24
Flash Sequence
Figure 25
Figure 26, Figure 27,
Figure 28
Tx-Masking Operation
Figure 29
PWM Operation
Figure 30
PFM Operation
Figure 31
Down-Mode Operation (Voltage Mode)
Figure 32
Voltage Mode Load Transient Response
Figure 33
Start-up Into video Light Operation
Figure 34
Start-up Into Voltage Mode Operation
Figure 35
100
100
90
90
80
70
60
ILED2 = 75 mA
ILED2 = 100 mA
ILED2 = 150 mA
50
ILED2 = 225 mA
40
30
20
ILIM = 1750 mA,
Tx-MASK = Low
LED2 Channel
10
0
2.5
2.9
3.3
3.7
4.1
4.5
VI - Input Voltage - V
4.9
5.3
LED Power Efficiency (PLED/PIN) - %
LED Power Efficiency (PLED/PIN) - %
Low-Light Dimming Mode Operation
ILED1 = ILED3 = 350 mA
ILED2 = 600 mA
80
70
ILED1 = ILED3 = 50 mA
ILED2 = 100 mA
60
ILED1 = ILED3 = 75 mA
ILED2 = 150 mA
40
30
20
ILIM = 1750 mA,
Tx-MASK = Low
10
0
2.5
Figure 4. LED Power Efficiency
vs.
Input Voltage
10
ILED1 = ILED3 = 100 mA
ILED2 = 200 mA
ILED1 = ILED3 = 250 mA
ILED2 = 450 mA
ILED1 = ILED3 = 250 mA
ILED2 = 550 mA
50
2.9
3.3
3.7
4.1
4.5
VI - Input Voltage - V
4.9
5.3
Figure 5. LED Power Efficiency
vs.
Input Voltage
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TYPICAL CHARACTERISTICS (continued)
2000
900
ILED2 = 800 mA
ILED1 = ILED3 = 350 mA
ILED2 = 600 mA
1750
800
ILED2 = 700 mA
700
LED2 Current - mA
DC Input Current - mA
1500
1250
1000
750
ILED1 = ILED3 = 250 mA
ILED2 = 550 mA
ILED1 = ILED3 = 250 mA
ILED2 = 450 mA
500
250
0
2.5
500
400
300
ILED2 = 550 mA
ILED2 = 450 mA
ILED2 = 350 mA
ILED2 = 300 mA
200
ILED1 = ILED3 = 250 mA
ILED2 = 275 mA
100
ILIM = 1750 mA,
Tx-MASK = Low
2.9
600
3.3
3.7
4.1
4.5
VI - Input Voltage - V
4.9
ILIM = 1750 mA
0
400 500 600 700 800 900 1000 1100 1200 1300 1400
LED2 Pin Headroom Voltage - mV
5.3
Figure 6. DC Input Current
vs.
Input Voltage
900
Figure 7. LED2 Current
vs.
LED2 Pin Headroom Voltage
300
ILED1 = ILED3 = 400 mA
275
ILED1 = ILED3 = 350 mA
250
ILED1 = ILED3 = 300 mA
225
700
600
LED2 Current - mA
LED1 + LED3 Current - mA
800
ILED1 = ILED3 = 250 mA
500
400
300
ILIM = 1750 mA
VIN = 2.5 V
200
VIN = 4.5 V
175
150
125
VIN = 3.6 V
100
75
200
ILIM = 1750 mA
100
0
400 500 600 700 800 900 1000 1100 1200 1300 1400
LED1, LED3 Pin Headroom Voltage - mV
50
25
0
0 25 50 75 100 125 150 175 200 225 250 275 300
LED2 Current Digital Code - mA
Figure 8. LED1+LED3 Current
vs.
LED1+LED3 Pin Headroom Voltage
Figure 9. LED2 Current
vs.
LED2 Current Digital Code
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TYPICAL CHARACTERISTICS (continued)
900
125
850
ILIM = 1750 mA
ILIM = 1750 mA
VIN = 2.5 V
750
VIN = 3.6 V
100
700
VIN = 4.5 V
75
LED2 Current - mA
LED1, LED3 Current - mA
800
VIN = 2.5 V
50
650
VIN = 4.5 V
VIN = 3.6 V
600
550
500
450
400
350
300
250
25
25
50
75
100
LED1, LED3 Current Digital Code - mA
125
200
200
300
Figure 10. LED1, LED3 Current
vs.
LED1, LED3 Current Digital Code
900
Figure 11. LED2 Current
vs.
LED2 Current Digital Code
450
425
400
500
600
700
800
LED2 Current Digital Code - mA
9
ILIM = 1750 mA
8
VIN = 2.5 V
INDLED = 0011
TA = 85°C
TA = 25°C
TA = -40°C
7
375
350
VIN = 3.6 V
VIN = 4.5 V
325
300
275
INDLED Current - mA
LED1, LED3 Current - mA
400
6
TA = 85°C
INDLED = 0010
5
4
3
INDLED = 0001
TA = 85°C
TA = 25°C
TA = -40°C
2
250
1
225
200
200 225 250 275 300 325 350 375 400 425 450
LED1, LED3 Current Digital Code - mA
0
0.5
VIN = 3.6 V
0.7
Figure 12. LED1, LED3 Current
vs.
LED1, LED3 Current Digital Code
12
TA = 25°C
TA = -40°C
0.9
1.1
1.3
1.5
1.7
INDLED Pin Headroom Voltage - V
1.9
Figure 13. INDLED Current
vs.
INDLED Pin Headroom Voltage
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TYPICAL CHARACTERISTICS (continued)
100
100
VIN = 4.2 V
80
VIN = 2.5 V
70
Efficiency - %
Efficiency - %
Forced PWM Operation
VIN = 3 V
PFM/PWM Operation
60
50
40
Forced PWM Operation
VIN = 4.2 V
60
50
PFM/PWM Operation
40
30
30
20
VOUT = 3.825 V
ILIM = 1750 mA
Voltage Mode Regulation
20
VOUT = 4.95 V
ILIM = 1750 mA
Voltage Mode Regulation
10
10
0
1
10
100
1000
IO - Output Current - mA
1
10000
10
100
1000
IO - Output Current - mA
Figure 14. Efficiency
vs.
Output Current
4.016
Voltage Mode Regulation
5.15
VOUT = 4.95 V,
ILIM = 1750 mA
Voltage Mode Regulation
PFM/PWM Operation
5.05
5
4.95
VIN = 4.2 V
Forced PWM Operation
4.9
VIN = 3.6 V
4.85
10
3.94
3.902
IOUT = 100 mA
3.863
3.825
IOUT = 1000 mA
3.787
VOUT = 3.825 V
ILIM = 1750 mA
3.749
VIN = 2.5 V
4.8
1
IOUT = 0 mA
3.978
VO - Output Voltage (DC) - V
5.1
10000
Figure 15. Efficiency
vs.
Output Current
5.2
VO - Output Voltage (DC) - V
VIN = 3 V
VIN = 2.5 V
80
VIN = 3.6 V
70
0
VIN = 3.6 V
90
90
100
1000
IO - Output Current - mA
10000
3.71
2.5
Figure 16. DC Output Voltage
vs.
Load Current
2.9
3.3
3.7
4.1
4.5
4.9
IO - Output Current - mA
5.3
Figure 17. DC Output Voltage
vs.
Load Current
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TYPICAL CHARACTERISTICS (continued)
1500
1400
400
Voltage Mode Regulation
350
1200
1100
VOUT = 4.95 V,
ILIM = 1250 mA
VOUT = 5.7 V,
ILIM = 1250 mA
1000
900
800
700
600
500
400
DC Pre-Charge Current - mA
IO - Output Current (max) - mA
1300
VIN = 3.6 V, TA = 25°C
300
VIN = 4.2 V, TA = 25°C
250
200
VIN = 2.5 V, TA = 25°C
150
100
300
200
50
100
0
2.5
2.9
3.3
3.7
4.1
4.5
VI - Input Voltage - V
4.9
0
5.3
0
0.6
1.2
1.8
2.4
3
3.6
Differential Input - Output Voltage - V
Figure 18. Maximum Output Current
vs.
Input Voltage
Figure 19. DC Pre-Charge Current
vs.
Differential Input-Output Voltage
400
1500
1400
VIN = 3.6 V, TA = -40°C
IOUT = 0 mA
ENPSM bit = ENVM bit = 1
1300
300
250
200
VIN = 3.6 V, TA = 85°C
150
VIN = 3.6 V, TA = 25°C
100
ICC - Supply Current - mA
DC Pre-Charge Current - mA
350
1200
50
0
0.6
1.2
1.8
2.4
3
3.6
Differential Input - Output Voltage - V
4.2
VOUT = 5.7 V, TA = 25°C
1000
900
800
600
0
VOUT = 4.95 V, TA = 85°C
1100
700
VOUT = 4.95 V,
TA = -40°C V
OUT = 4.95 V,
TA = 25°C
500
2.5
Figure 20. DC Pre-Charge Current
vs.
Differential Input-Output Voltage
14
4.2
2.9
3.3
VOUT = 3.825 V,
TA = 25°C
3.7
4.1
4.5
VI - Input Voltage - V
4.9
5.3
Figure 21. Supply Current
vs.
Input Voltage
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TYPICAL CHARACTERISTICS (continued)
26
28
VIN = 3.6 V
26
22
24
20
22
18
16
14
12
10
Sample Size = 76
8
Sample Percentage - %
Sample Percentage - %
24
6
20
18
16
14
12
Sample Size = 76
10
8
6
4
4
2
0
VIN = 3.6 V
2
50
51 52 53 54 55 56 57 58 59
Temperature Detection (55°C Threshold)
0
60
Figure 22. Temperature Detection Threshold
64 65 66 67 68 69 70 71 72 73 74 75
Temperature Detection (70°C Threshold)
Figure 23. Temperature Detection Threshold
200
150
Tx-MASK Input
IPORT = -100 mA
STRB1 Input
125
100
75
50
25
Port
Input Buffer
0
-25
VPORT
TJ - Junction Temperature - °C
175
100 mA
-50
-0.6 -0.55 -0.5 -0.45 -0.4 -0.35 -0.3 -0.25 -0.2 -0.15 -0.1
Port Voltage - V
Figure 24. Junction Temperature
vs.
Port Voltage
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TYPICAL CHARACTERISTICS (continued)
STRB0
(2V/div)
STRB0
(2V/div)
ILED2
(500mA/div)
Tx-MASK
(2V/div)
LED2 Channel Only
DCLC2[2:0] = 000
FC2[5:0] = 100000
DCLC13[2:0] = 000
FC13[4:0] = 01100
ILED1 + ILED3
(200mA/div)
VOUT
(1V/div - 3.6V Offset)
LED2 Pin Headroom Voltage
(1V/div)
ILED2
(200mA/div)
VIN = 3.6V, VOUT = 4.95V, ILIM = 1750mA
VIN = 3.6V, VOUT = 4.95V, ILIM = 1750mA
t - Time = 500 µs/div
t - Time = 1 ms/div
Figure 25. FLASH SEQUENCE (STRB1=0)
Tx-MASK
(2V/div)
Figure 26. Tx-MASKING OPERATION (STRB1=0)
Tx-MASK
(2V/div)
ILED2
(200mA/div)
ILED2
(200mA/div)
IL
(200mA/div)
IL
(500mA/div)
VIN = 3.6V, VOUT = 4.95V
ILIM = 1750mA
LED2 Channel Only
DCLC2[2:0] = 111
FC2[5:0] = 100000
VIN = 3.6V, VOUT = 4.95V
ILIM = 1750mA
t - Time = 5 µs/div
LED2 Channel Only
DCLC2[2:0] = 010
FC2[5:0] = 100000
t - Time = 100 µs/div
Figure 27. Tx-MASKING OPERATION (STRB1=0)
16
DCLC2[2:0] = 000
FC2[5:0] = 011000
Figure 28. Tx-MASKING OPERATION (STRB1=0)
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TYPICAL CHARACTERISTICS (continued)
VOUT
(20mV/div - 4.95V Offset)
ILED2
(20 mA/div)
IL
(200mA/div)
SW
(2V/div)
Frequency = 30 kHz
Duty Cycle = 23 %
VIN = 3.6V, VOUT = 4.95V
IOUT = 300mA, ILIM = 1750mA
Forced PWM Operation
ENPSM bit = 0
t - Time = 125 ns/div
t - Time = 10 µs/div
Figure 29. LOW-LIGHT DIMMING MODE OPERATION
Figure 30. PWM OPERATION
VOUT
(100mV/div - 4.95V Offset)
VOUT
(100mV/div - 3.825V Offset)
IL
(200mA/div)
IL
(200mA/div)
SW
(5V/div)
SW
(5V/div)
VIN = 3.6V, VOUT = 4.95V
IOUT = 50mA, ILIM = 1750mA
PFM/PWM Operation
ENPSM bit = 1
VIN = 4.2V, VOUT = 3.825V
IOUT = 50mA, ILIM = 1750mA
t - Time = 2 ms/div
t - Time = 2 ms/div
Figure 31. PFM OPERATION
PFM/PWM Operation
ENPSM bit = 1
Figure 32. DOWN-MODE OPERATION (VOLTAGE MODE)
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TYPICAL CHARACTERISTICS (continued)
VIN = 3.6V, VOUT = 4.95V
ILIM = 1750mA
MODE_CTRL[1:0] = 01
DC Light Turn-On
ILED2
(50mA/div)
VOUT
(500mV/div - 4.95V Offset)
VOUT
(2V/div)
IL
(500mA/div)
IL
(200mA/div)
50mA to 500mA Load Step
IOUT
(500mA/div)
VIN = 3.6V, VOUT = 4.95V
ILIM = 1750mA
PFM/PWM Operation
ENPSM bit = 1
LED2 Channel Only
DCLC2[2:0] = 100
t - Time = 200 µs/div
t - Time = 50 ms/div
Figure 33. VOLTAGE MODE LOAD TRANSIENT RESPONSE
Figure 34. START-UP INTO video LIGHT OPERATION
ENVM bit
Voltage Mode Regulation Start
VOUT
(2V/div)
IL
(200mA/div)
VIN = 3.6V, VOUT = 4.95V
IOUT = 0mA, ILIM = 1750mA
t - Time = 100 µs/div
Figure 35. START-UP INTO VOLTAGE MODE OPERATION
18
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DETAILED DESCRIPTION
•
•
•
•
•
•
•
•
•
•
OPERATION
VIDEO LIGHT AND FLASH OPERATION
VOLTAGE MODE
PRIVACY INDICATOR
SAFE OPERATION AND PROTECTION FEATURES
POWER-SAVE MODE OPERATION, EFFICIENCY
START-UP SEQUENCE
NRESET INPUT: HARDWARE ENABLE / DISABLE
SHUTDOWN
SERIAL INTERFACE DESCRIPTION
OPERATION
The TPS6131x family is an integrated solution with a wide feature set for driving up to three LEDs for still-camera
flash and video-camera lighting applications. It employs a 2MHz fixed on-time, PWM current-mode converter to
generate the output voltage required to drive up to three high-power LEDs in parallel. The device integrates an
NMOS-switch power stage and a synchronous PMOS rectifier. The device also implements a set of linear
low-side current regulators to control the LED current when the battery voltage is higher than the diode forward
voltage.
The high efficient boost converter stage and LED forward voltage adoption ensure lowest device input current for
a given LED output current.
A special circuit disconnects the load from the battery during shutdown of the converter. In conventional
synchronous-rectifier circuits, the back-gate diode of the high-side PMOS is forward biased in shutdown, allowing
current to flow from the battery to the output. The TPS6131x prevents this by disconnecting the cathode of the
back-gate diode of the high-side PMOS from the source when the regulator is in shutdown.
The TPS6131x device not only operates as a regulated current source, but also as a standard voltage-boost
regulator featuring a power-save mode for improved efficiency at light loads. If the input voltage is higher than
the programmed output voltage, a down mode is implemented that acts similarly to an LDO.
The power stage is capable of supplying a maximum total current of roughly 1500mA. The TPS6131x provides
three constant-current sinks, capable of sinking up to 2x 400mA (LED1 and LED3) and 800mA (LED2) in flash
mode.
Figure 36. TPS6131x States
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Special effort is taken for safe operation and robust system integration. The battery voltage can be monitored so
that the flash current is not increased if the battery voltage drops by a programmable threshold. Internal timers
limit the flash on-time to prevent potential camera-engine software errors, and a video light watchdog acts in a
similar fashion. Multiple monitoring features (LED and die temperature, input voltage droop etc.) keep the device
and LEDs operating properly.
The TPS6131x integrates an I2C compatible interface allowing transfers up to 3.4Mbits/s for controlling the
device, featuring low-speed mode, standard mode and high-speed mode compatible operation. Additionally,
basic functions can be triggered by dedicated hardware input signals, such as STRB0 and STRB1 for triggering
the flash or video lighting with zero latency.
VIDEO LIGHT AND FLASH STROBE OPERATION
The TPS6131x devices drive one, two or three LEDs for video light and flash application. The video light and
flash operation can either be triggered by an I2C software command or by means of dedicated, zero latency
hardware signals.
LED Hardware Setup
The TPS6131x device utilizes LED forward-voltage sensing circuitry on LED1-3 pins to optimize the power-stage
boost ratio for maximum efficiency. Due to the nature of the sensing circuitry, it is not recommended to leave any
of the LED1-3 pins unused if the operation has been selected via ENLED[3:1] bits. Leaving LED1-3 pins
unconnected, while the respective ENLEDx bits have been set, forces the control loop into high gain, and
eventually trips the output overvoltage protection. Figure 37 shows the recommend LED setup for a single, dual
or triple-LED application.
VOUT
TPS6131x
VOUT
COUT
TPS6131x
LED1
LED2
LED3
VOUT
COUT
LED1
LED2
LED3
Dual LED
Single LED
COUT
TPS6131x
LED1
LED2
LED3
Tripple LED
Figure 37. White LED Hardware Setup Options
The LED1-3 inputs may be connected together to drive one or two LEDs at higher currents. Connecting the
current sink inputs in parallel does not affect the internal operation of the TPS6131x. For best operation, it is
recommended to disable the LED inputs that are not connected. (see the ENLED[3:1] bits description in
REGISTER5 DESCRIPTION).
The video light currents are individually programmed via the video light control bits DCL13[2:0] and DCL2[2:0] ,
the flash currents via FC2[5:0] and FC13[4:0] bits accordingly. If, for single or dual LED application as shown in
Figure 37, current sinks are connected to each other and enabled, the resulting video / flash current will be the
sum of the programmed currents.
Triggering Video Light and Flash
For most flexible system integration, the TPS6131x offers several options for activating the video light and flash.
Depending on the settings of the MODE_CTRL[1:0] bits, the device can enter different modes of operation. It
offers the option of triggering the video light and flash via hardware signals (STRB0, STRB1) or software I2C
command. The flash-signal hardware trigger can be on the leading-edge, turning on for the programmed flash on
time, or level sensitive, turning on for as long as the signal is logic high.
The TPS6131x flash timer is programmed via the STIM[2:0] and SELSTIM bits. If the flash is fired by a
rising-edge trigger or by an I2C command, the timer defines the flash duration. If the flash is fired by a
level-sensitive trigger, the timer defines the maximum flash-on duration, and overrides the hardware signal if the
programmed on-time is exceeded.
20
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For video lighting, a watchdog timer is implemented; this must be refreshed within 13.0 seconds. This function
can be disabled, as described below.
MODE_CTRL[1:0] The STRB0, STRB1 inputs are disabled. The device regulates the LED current in video
= 01:
light mode (DCLC bits) regardless of the STRB0, STRB1 inputs and the
START_FLASH/TIMER (SFT) bit. To avoid device shutdown because of the video light
safety timeout, MODE_CTRL[1:0] must be refreshed within less than 13.0 seconds (STRB1
= 0). The video light watchdog timer can be disabled by pulling the STRB1 signal high.
MODE_CTRL[1:0] The STRB0, STRB1 inputs are enabled. The flash pulse can be triggered by these
= 10:
synchronization signals, or by a software command (START_FLASH/TIMER (SFT) bit).
The LEDs are enabled/disabled according to the STRB0, STRB1 input. The flash safety
timer is activated, and the video light watchdog timer is disabled.
The dual-wire camera-module interface STRB0 and STRB1 inputs are used for selecting the video light (STRB1
= 1) or flash (STRB1 = 0) mode. The STRB0 signal then triggers the video light or flash, depending on the state
of STRB1. The STT bit defines if the flash trigger is level sensitive (STT = 0), or fired on the rising edge (STT =
0).
Level-Sensitive Flash Trigger (STT = 0)
In this mode, the high-power LEDs are driven at the flash-current level and the safety timer (STIM) is running.
The maximum duration of the flash pulse is defined in the STIM[2:0] register.
The safety timer is triggered on rising edge and stopped by a negative logic on the synchronization source
(STRB0, STRB1 = 0) or by a timeout event (TO bit).
AF ASSIST LIGHT
STROBE
STRB0
STRB1
DURATION < STIM
TIMER
LED CONTROL
LED OFF
LED OFF
DC LIGHT
LED OFF
FLASH
Figure 38. Hardware Synchronized Video Light and flash Strobe
Flash is Rising-Edge Sensitive (STT = 1)
In this mode, the high-power LEDs are driven at the flash current level and the safety timer (STIM) is running.
The duration of the flash pulse is defined in the STIM[2:0] register.
The flash strobe is started either by a rising edge on the synchronization source (STRB0, STRB1 = 0) or by a
positive transition on the START-FLASH/TIMER (SFT) bit. Once running, the timer ignores all kind of triggering
signals and only stops after a timeout (TO). START-FLASH/TIMER (SFT) bit is being reset by the timeout (TO)
signal.
AF ASSIST LIGHT
STROBE
STRB0
STRB1
DURATION = STIM
TIMER
LED CONTROL
LED OFF
LED OFF
DC LIGHT
LED OFF
FLASH
Figure 39. Edge Sensitive Timer (Single Trigger Event)
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VOLTAGE MODE
In this mode, the TPS6131x operates as a standard voltage-boost regulator, featuring power-save mode for
improved efficiency under light loads. The voltage-mode operation is enabled by software control by setting the
mode-control bit MODE_CTRL[1:0] = 11. The device regulates a constant output voltage according to the
OV[3:0] bit settings (between 3.825V and 5.7V in 125mV steps). In voltage mode, the LED current sinks LED1-3
are turned off.
The TPS6131x integrates a software control bit (ENVM bit) that can be used to force the converter to run in
voltage mode. This enables the converter to operate at a fixed programmed output voltage (according to the
OV[3:0] settings) while operating the LEDs.
Table 3 provides an overview of the different voltage mode variations.
Table 3. Voltage Mode Description
INTERNAL REGISTER
SETTINGS MODE_CTRL[1:0]
ENVM
BIT
11
0
00
1
01
1
The converter operates in voltage-regulation mode (VM); the output voltage is set via the
register OV[3:0]. The LEDs are turned-on for video light operation and the energy is being
directly transferred from the battery to the output. The LED currents are regulated by the means
of the low-side current sinks.
10
1
The converter operates in the voltage-regulation mode (VM); the output voltage is set via the
register OV[3:0]. The LED currents are regulated by the low-side current sinks. The LEDs are
ready for flash operation.
11
1
LEDs are turned off and the converter operates in the voltage regulation mode (VM); the output
voltage is set via the register OV[3:0].
OPERATING MODES
LEDs are turned off and the converter operate in voltage-regulation mode (VM); the output
voltage is set via register OV[3:0].
Down mode in voltage mode operation
In general, a boost converter only regulates output voltages which are higher than the input voltage. The
TPS6131x can regulate 4.2V at the output with an input voltage as high as 5.5V. To control these applications
properly, a down-conversion mode is implemented.
In voltage-regulation mode, if the input voltage reaches or exceeds the output voltage, the converter changes to
down-conversion mode. In this mode, the control circuit changes the behavior of the rectifying PMOS. It sets the
voltage drop across the PMOS as high as needed to regulate the output voltage. This increases the power
losses in the converter, and must be taken into account for thermal design. The down-conversion mode is
automatically turned off as soon as the input voltage falls to approximately 200mV below the output voltage.
For proper operation in down-conversion mode the output voltage should not be programmed higher than
approximately 5.3V. Care should be taken not to violate the absolute maximum ratings at the SW pins.
Power Good Indication
The TPS6131x integrates a power-good circuit that is activated when the device operates in voltage-regulation
mode (MODE_CTRL[1:0] = 11 or ENVM = 1). In shutdown mode (MODE_CTRL[1:0] = 00, ENVM = 0), the
GPIO/PG pin state is defined below, according to the GPIOTYPE bit:
GPIOTYPE
GPIO/PG SHUTDOWN STATE
0
Reset/pulled to ground
1
Open-drain
Depending on the GPIO/PG output stage type selection (i.e., push-pull or open-drain), the polarity of the
power-good output signal (PG) can be inverted or not. The power-good software bit and hardware signal polarity
is defined below:
GPIOTYPE
PG BIT
GPIO/PG OUTPUT PORT
0
0
1
1
0: push-pull output
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GPIOTYPE
1: open-drain output
PG BIT
GPIO/PG OUTPUT PORT
0
Open-drain
1
Low
COMMENTS
Output is active-low
The power-good signal is true when the output voltage is within –1.5% and +2.5% of its nominal value.
Conversely, it is false when the voltage-mode operation is suspended (MODE_CTRL[1:0] ≠ 11 and ENVM = 0).
Forced PWM mode operation
Output Voltage
Down Regulation
Voltage Mode Request
1.025 VOUT (NOM )
Nom. Voltage
Output Voltage, VOUT
VOUT (NOM )
Start-up phase
0.985 VOUT (NOM )
Output Voltage
Up Regulation
Power Good Bit, (PG)
Power Good Output,
GPIO/PG
Hi-Z
Hi-Z
Forced PWM mode operation
(PG) Bit
Figure 40. Power Good Operation (DIR = 1, GPIOTYPE = 1)
The TPS6131x device uses a control architecture that “recycles” excess energy that might be stored in the output
capacitor. By reversing the operation of the boost power stage, the converter is capable of transferring energy
from its output back into the input source. In this case, the power-good signal is de-asserted while the output
voltage is decreasing towards its target value (i.e., the closest fit voltage the converter can support.
PRIVACY INDICATOR
The privacy indicator functionality can be used to indicate when a person is being photographed or filmed. The
TPS6131x device offers two options of privacy indication: A dedicated pin driving an additional privacy indicator
LED or using the white LEDs with pulse width modulation.
Dedicated LED Privacy Indicator
The TPS6131x device provides a high-side linear constant current source to drive low VF LEDs. The LED current
is directly regulated off the battery and can be controlled via the INDC[3:0] bits, ranging 2.6mA to 15.8mA in 7
programable current steps.
The device can drive two possible hardware configurations shown in Figure 41 and Figure 42. In Figure 41 the
TPS6131x device drives a privacy indicator LED towards ground.
VOUT
VOUT
COUT
TPS6131x
COUT
LED1
LED2
LED3
TPS6131x
INDLED
LED1
LED2
LED3
INDLED
Figure 41. Configuration 1
Figure 42. Configuration 2
The TPS6131x device also allows a path for driving a privacy indicator LED that is reverse biased to the white
flash LED, see Figure 42. To do so, the output of the converter (VOUT) is pulled to ground thus allowing a
reverse current to flow. This mode of operation is only possible when the converter’s power stage is in shutdown
(MODE_CTRL[1:0] = 00, ENVM = 0).
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White LED Privacy Indicator
The TPS6131x device features white LED drive capability at very low light intensity. To generate a reduced LED
average current, the device employs a 30kHz fixed-frequency PWM modulation scheme. The PWM timer uses
the internal oscillator as reference clock, therefore the PWM modulating frequency shows the same accuracy as
the internal reference clock. Operation is shown in the timer block diagram in.
The video light current is modulated with a duty cycle defined by the INDC[3:0] bits. The low light dimming mode
can only be activated in the software-,controlled video-light-only mode (MODE_CTRL[1:0] = 01, ENVM = 1), and
applies to the LEDs selected via ENLED[3:1] bits. In this mode, the video light safety-timeout feature is disabled.
PWM Dimming Steps
5%, 11%, 17%, 23%, 30%, 36%, 48%, 67%
I DCLIGHT
t1
I LED (DC ) = I DCLIGHT x PWM Dimming Step
0
T PWM
Figure 43. PWM Dimming Principle
SAFE OPERATION AND PROTECTION FEATURES
LED Temperature Monitoring (Finger-Burn Protection)
The TPS6131x device optionally monitors the LED temperature. Critical temperatures are handled in two stages
reflected by two bits: LEDWARN provides an early warning to the camera engine, LEDHOT immediately
suspends the flash operation.
The LED temperature is sensed by measuring the voltage drop of a negative-temperature-coefficient resistor
connected between the TS and AGND pins. An internal current source provides the bias (c.a. 24 mA) for the
NTC, and the TS pin voltage is compared to internal thresholds (1.05V and 0.345V) to protect the LEDs against
overheating. See the Application Information section for choosing the NTC.
The temperature-monitoring blocks are explicitly active in video light or flash modes. In voltage-mode operation
[MODE_CTRL[1:0] = 11], the device only activates the TS input when the ENTS bit is set high.
The LEDWARN and LEDHOT bits reflect the LED temperature. The LEDWARN bit is set when the voltage at the
TS pin is lower than 1.05V. This threshold corresponds to an LED warning temperature value; device operation is
still permitted. While regulating LED current (i.e. video light or flash modes), the LEDHOT bit is latched when the
voltage at the TS pin is lower than 0.345V. This threshold corresponds to an excessive LED temperature value;
device operation is immediately suspended, (MODE_CTRL[1:0] bits are reset, and the HOTDIE[1:0] bits are set).
LED Failure Modes (Open / Short Detection) and Overvoltage Protection
The TPS6131x devices incorporate protection features to indicate if the connected LED(s) are failing. These
protections cover overvoltage conditions, which are caused by a failing LED showing open circuit behavior, as
well as short circuit conditions caused by a failing LED or further reasons causing a short circuit condition. If such
failure conditions occur, these are indicated by setting a failure detection flag. Furthermore, the maximum current
drawn from the output is limited and can be programmed by the current-limit setting.
LED open circuit detection / Over Voltage Protection
If the connected LED(s) fail showing an open circuit behavior or are disconnected, the VOUT output voltage must
be limited to prevent the step-up converter from exceeding critical values. An overvoltage protection is
implemented to avoid the output voltage exceeding critical values for the device and possibly for the system it is
supplying. For this protection the TPS6131x output voltage is monitored internally. The TPS6131x device limits
VOUT according to the overvoltage protection settings (refer to OVP specification). In this failure mode, VOUT is
either limited to 4.65V (typ.) or 6.0V (typ.) and the HIGH-POWER LED FAILURE [HPLF] flag is set. The OVP
threshold depends on the programmed output voltage [OV].
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OVP THRESHOLD
OPERATING CONDITIONS
4.65 V typ.
0000 ≤ OV[3:0] ≤ 0100
6.0 V typ.
0101 ≤ OV[3:0] ≤ 1111
Short Circuit Protection
The TPS6131x devices incorporate double protection to protect the device and application circuit from short
circuit conditions occurring between VOUT and the current sinks LED1..3.
If a short circuit condition occurs while the LED(s) are operated, the low side current sinks LED1, LED2, LED3
limit the maximum output current as programmed for the video-light mode or flash mode respectively. If a short
circuit condition occurs, the current sinks increase their input resistance to prevent excessive current to be
drawn. Furthermore, the HIGH-POWER LED FAILURE flag (HPLF) is set to indicate the short circuit condition.
(HPLF) is triggered if the LED forward voltage drops below 1.23V typically. The second protection is the current
limit, which generally limits the current drawn from VOUT. See the Current Limit section.
LED Current Ramp-Up/Down
To achieve smooth LED current waveforms and avoid excessive battery voltage drop, the TPS6131x device
actively controls the LED current ramp-up / down sequence.
Table 4. LED Current Ramp-Up/Down Control vs Operating Mode
ISTEP = 25mA
LED CURRENT RAMP-UP
tRISE = 12ms
Slew-rate × 2.1mA/ms
ISTEP = 25mA
LED CURRENT RAMP-DOWN
tFALL = 0.5ms
Slew-rate × 50mA/ms
LED
CURRENT
ISTEP
Time
t RISE
t FALL
Figure 44. LED Current Slew-Rate Control
Battery Voltage Droop Monitoring and Protection
During a high-power flash strobe, the battery voltage usually drops by a few hundred millivolts. To prevent the
battery voltage from collapsing too much, the TPS6131x devices integrates a battery voltage droop monitoring
feature to automatically limit the flash current if the battery voltage drops more than a programmable threshold.
The battery voltage droop monitoring feature can be enabled/disabled via the ENBATMON bit.
At the very beginning of the flash strobe, the device measures the battery voltage and sets a minimum battery
voltage threshold based on the tolerable droop (refer to BATDROOP[2:0] bits). While the LED current is
increasing to the target flash current (see FC13[4:0] and FC2[5:0] bits), a comparator monitors the actual battery
voltage and stops the ramp-up sequence when the droop exceeds the limit. Operation is understood best by
referring to the functional block diagram and to Figure 45.
The battery voltage droop monitor feature is automatically disabled during a Tx-MASK event.
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ILED
Target Flash
Current (950mA)
Actual Flash
Current (700mA)
LED current is
stopped from
ramping further
DC light
VBAT
maximum allowed
Battery Droop
(BATDROOP[2:0])
Battery droop
threshold
exceeded
STRB0
Figure 45. Battery Voltage Droop Monitoring / LED Current Control Principle (STRB1 = 0, Tx-BASE = 1)
Undervoltage Lockout
The undervoltage lockout circuit prevents the device from error conditions at low input voltages. It prevents the
converter from turning on the switch–MOSFET, or rectifier–MOSFET for battery voltages below 2.3V. The I2C
compatible interface is fully functional down to 2.1V input voltage.
Hot Die Detection and Thermal Shutdown
The TPS6131x device offers two levels of die temperature monitoring and protection, which are hot die detection
and thermal shutdown functionality. The hot die detector (HOTDIE[1:0] bits) reflects the instantaneous junction
temperature. This functionality is always enabled except when the device is in shutdown mode.
The hot die detector monitors the junction temperature but does not shut down the device. It provides an early
warning to the camera engine to avoid excessive power dissipation thus preventing from thermal shutdown
during the next high-power flash strobe.
As soon as the junction temperature TJ exceeds 160°C typical, the device goes into thermal shutdown. In this
mode, the power stage and the low-side current regulators are turned off, the HOTDIE[1:0] bits are set and can
only be reset by a read access. In the voltage mode operation (MODE_CTRL[1:0] = 11 or ENVM = 1), the device
continues its operation when the junction temperature falls below 140°C typ. again. In the current regulation
mode (i.e., video light or flash modes), device operation is suspended.
Table 5. Die Temperature Bits
HOTDIE[1:0]
TJ
00
<55°C
01
55°C <= TJ <= 70°C
10
>70°C
11
Thermal shutdown tripped. The bit is reset after read access
Current Limit
The TPS6131x devices employ a programmable inductor-current limit. This allows choosing inductors with
different saturation-current ratings. Furthermore, this provides protection against a shorted inductor, or if the
inductance value has dramatically dropped. This protects the battery from excessively-high current drain.
The current limit circuit employs a valley current sensing scheme. The detection threshold is user selectable via
the ILIM bit. The ILIM bit can only be set prior to entering operation, i.e. initial shutdown state.
Figure 46 illustrates the inductor and rectifier current waveforms during current limit operation. The output
current, IOUT, is the average of the rectifier ripple current waveform. When the load current is increased such
that the lower peak is above the current limit threshold, the off time is lengthened to allow the current to decrease
to this threshold before the next on-time begins (so called frequency fold-back mechanism).
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Both the output voltage and the switching frequency are reduced as the power stage of the device operates in a
constant current mode. The maximum continuous output current (IOUT(CL)), before entering current limit operation,
can be defined as:
V
V
- VIN
1
D
IOUT(CL) = (1 - D) ´ (IVALLEY + DIL ) with DIL = IN ´
and D » OUT
2
L
f
VOUT
(1)
The TPS6131x device also provides a negative current limit (≈ 300mA) to prevent an excessive reverse inductor
current when the power stage sinks current from the output in the forced continuous-conduction mode.
IPEAK
DIL
Current Limit
Threshold
Rectifier
Current
IVALLEY = ILIM
IOUT (CL)
DIL
IOUT(DC) (= ILED)
Increased
Load Current
IIN (DC)
f
Inductor
Current
IIN (DC)
DIL
ΔI L =
V IN D
×
L f
Figure 46. Inductor/Rectifier Currents in Current Limit Operation
Table 6. Inductor Current Limit Operation
CURRENT LIMIT SETTING
ILIM BIT
1250 mA
Low
1750 mA
High
Flash Blanking (Tx-Mask) for Instantaneous Flash-Current Reduction
The TPS6131x devices offer a dedicated hardware signal input (Tx-Mask) that can be used to reduce the flash
current to the programmed video light level instantaneously.
This feature can be used to reduce the overall current drawn from the battery if other system components require
high energy simultaneously, e.g. during a RF PA transmission pulse.
The Tx-MASK function has no influence on the safety timer duration.
FLASH
LED CURRENT
DC LIGHT
Tx- MASK
STRB0
Figure 47. Synchronized Flash With Blanking Periods (STRB1 = 0)
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POWER-SAVE MODE OPERATION, EFFICIENCY
The TPS6131x integrates a power-save mode to improve efficiency under light loads. In power-save mode the
converter only operates when the output voltage trips below a set threshold voltage. It ramps up the output
voltage with one-to-several pulses and returns to power-save mode once the output voltage exceeds the set
threshold voltage.
Output
Voltage
PFM mode at light load
PFM ripple about 0.015 x VOUT
1.013 x VOUT NOM.
VOUT NOM.
PWM mode at heavy load
Figure 48. Operation inpFM Mode and Transfer to PWM Mode
The power-save mode can be enabled and disabled via the ENPSM bit. In down conversion mode, power-save
mode is always active and the device cannot be forced into fixed frequency operation at light loads.
The LED sense voltage has a direct effect on converter efficiency. Because the voltage across the low-side
current regulator does not contribute to the output power (LED brightness), the lower the sense voltage the
higher the efficiency will be.
The integrated current control loop automatically selects the minimum boost ratio to maintain regulation based on
the LED forward voltage and current requirements. The low-side current regulators drop the voltage difference
between the input voltage and the LEDs forward voltage (VF(LED) < VIN). When running in boost mode (VF(LED) >
VIN), the voltage present at the LED1-3 pins of the low-side current regulators is typically 400mV, leading to high
power conversion efficiency. Depending on the input voltage and the LEDs forward voltage characteristic the
converter efficiency is approximately 75% to 90%.
START-UP SEQUENCE
To avoid high inrush current during start-up, special care is taken to control the inrush current. When the device
enables, the internal startup cycle starts with the first step, the pre-charge phase.
During pre-charge, the rectifying switch is turned on until the output capacitor is either charged to a value close
to the input voltage or ≈ 3.3V, whichever occurs first. The rectifying switch is current-limited during that phase.
The current limit increases with decreasing input-to-output voltage difference. This circuit also limits the output
current under output short-circuit conditions.
After having pre-charged the output capacitor, the device starts switching, and increases its current limit in three
steps of typically 25mA, 250mA and full current limit (ILIM setting). The current-limit transition from the first to the
second step occurs after 1ms of operation. Full current limit operation is set once the output voltage has reached
its regulation limits. In this mode, the active balancing circuit is disabled.
NRESET INPUT: HARDWARE ENABLE / DISABLE
The TPS6131x family features a hardware reset pin (NRESET). This reset pin allows the device to be disabled
by an external controller without requiring an I2C write command. Under normal operation, the NRESET pin
should be held high to prevent an unwanted reset. When the NRESET is driven low, the I2C control interface and
all internal control registers are reset to the default states and the part enters shutdown mode.
SHUTDOWN
Writing 00 to MODE_CTRL[1:0] bits forces the device into shutdown. The shutdown state can only be entered
when the voltage regulation (ENVM = 0) and light modes are both turned off.
In the shutdown state:
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•
•
•
•
The
The
The
The
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regulator stops switching.
high-side PMOS disconnects the load from the input.
LEDx pins are high impedance thus eliminating any DC conduction path.
TPS6131x device actively discharges the output capacitor when it turns off.
SERIAL INTERFACE DESCRIPTION
I2C™ is a 2-wire serial interface developed by Philips Semiconductor, now NXP Semiconductors (see I2C-Bus
Specification, Version 2.1, January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with
pull-up structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I2C compatible devices
connect to the I2C bus through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or
a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device
addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A
slave device receives and/or transmits data on the bus under control of the master device.
The TPS6131x device works as a slave and supports the following data transfer modes, as defined in the
I2C-Bus Specification: standard mode (100 kbps) and fast mode (400 kbps), and high-speed mode (3.4 Mbps).
The interface adds flexibility to the power supply solution, enabling most functions to be programmed to new
values depending on the instantaneous application requirements. Register contents remain intact as long as
supply voltage remains above 2.1V.
The data transfer protocol for standard and fast modes is exactly the same, therefore they are referred to as
F/S-mode in this document. The protocol for high-speed mode is different from F/S-mode, and it is referred to as
HS-mode. The TPS6131x device supports 7-bit addressing; 10-bit addressing and general call address are not
supported. The device 7bit address is defined as ‘011 0011’.
F/S-Mode Protocol
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 49. All I2C-compatible devices should
recognize a start condition.
DATA
CLK
S
P
START Condition
STOP Condition
Figure 49. START and STOP Conditions
The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit R/W
on the SDA line. During all transmissions, the master checks for valid data. A valid data condition requires the
SDA line to be stable during the entire high period of the clock pulse (see Figure 50). All devices recognize the
address sent by the master and compare it to their internal fixed addresses. Only the slave device with a
matching address generates an acknowledge (see Figure 51) by pulling the SDA line low during the entire high
period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a
slave has been established.
DATA
CLK
Data line
stable;
data valid
Change
of data
allowed
Figure 50. Bit Transfer on the Serial Interface
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The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the
slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an
acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary.
To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to
high while the SCL line is high (see Figure 49). This releases the bus and stops the communication link with the
addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a stop
condition, all devices know that the bus is released, and they wait for a start condition followed by a matching
address.
Attempting to read data from register addresses not listed in this section will result in 00h being read out.
Figure 51. Acknowledge on the I2C Bus
Figure 52. Bus Protocol
H/S-Mode Protokoll
The master generates a start condition followed by a valid serial byte containing HS master code 00001XXX.
This transmission is made in F/S-mode at no more than 400 Kbps. No device is allowed to acknowledge the HS
master code, but all devices must recognize it and switch their internal setting to support 3.4 Mbps operation.
The master then generates a repeated start condition (a repeated start condition has the same timing as the start
condition). After this repeated start condition, the protocol is the same as F/S-mode, except that transmission
speeds up to 3.4 Mbps are allowed. A stop condition ends the HS-mode and switches all the internal settings of
the slave devices to support the F/S-mode. Instead of using a stop condition, repeated start conditions should be
used to secure the bus in HS-mode.
Attempting to read data from register addresses not listed in this section will result in 00h being read out.
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TPS6131x I2C Update Sequence
The TPS6131x requires a start condition, a valid I2C address, a register address byte, and a data byte for a
single update. After the receipt of each byte, TPS6131x device acknowledges by pulling the SDA line low during
the high period of a single clock pulse. A valid I2C address selects the TPS6131x. TPS6131x performs an update
on the falling edge of the acknowledge signal that follows the LSB byte.
1
7
1
1
8
1
8
1
1
S
Slave Address
R/W
A
Register Address
A
Data
A
P
“0” Write
A
S
Sr
P
From Master to TPS6131x
From TPS6131x to Master
= Acknowledge
= START condition
= REPEATED START condition
= STOP condition
Figure 53. : “Write” Data Transfer Format in F/S-Mode
1
7
1
1
8
1
1
7
1
1
8
1
1
S
Slave Address
R/W
A
Register Address
A
Sr
Slave Address
R/W
A
Data
A
P
“0” Write
“1” Read
From Master to TPS6131x
A
S
Sr
P
From TPS6131x to Master
= Acknowledge
= START condition
= REPEATED START condition
= STOP condition
Figure 54. “Read” Data Transfer Format in F/S-Mode
F/S Mode
HS Mode
F/S Mode
1
8
1
1
7
1
1
8
1
8
1
1
S
HS-Master Code
A
Sr
Slave Address
R/W
A
Register Address
A
Data
A/A
P
Data Transferred
(n x Bytes + Acknowledge)
HS Mode Continues
Sr
A
A
S
Sr
P
From Master to TPS6131x
From TPS6131x to Master
Slave Address
= Acknowledge
= Acknowledge
= START condition
= REPEATED START condition
= STOP condition
Figure 55. Data Transfer Format in H/S-Mode
Slave Address Byte
MSB
X
LSB
X
X
X
X
X
A1
A0
The slave address byte is the first byte received following the START condition from the master device.
Register Address Byte
MSB
0
LSB
0
0
0
00
D2
D1
D0
Following the successful acknowledgment of the slave address, the bus master will send a byte to the
TPS6131x, which will contain the address of the register to be accessed.
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REGISTER DESCRIPTIONS
REGISTER0 DESCRIPTION
Memory location: 0x00
Description
Bits
Memory type
Default value
RESET
D7
R/W
0
Bit
Description
RESET
Register Reset bit.
0: Normal operation.
1: Default values are set to all internal registers.
DCLC13[2:0]
Video Light Current Control bits (LED1/3).
000: 0mA. (1) (2)
001: 25mA
010: 50mA
011: 75mA
100: 100mA
101: 125mA
110: 150mA
111: 175mA
DCLC2[2:0]
Video Light Current Control bits (LED2).
000: 0mA. (1) (2)
001: 25mA
010: 50mA
011: 75mA
100: 100mA
101: 125mA
110: 150mA, 225mA current level can be activated simultaneously with Tx-MASK = 1
111: 175mA, 325mA current level can be activated simultaneously with Tx-MASK = 1
(1)
(2)
32
FREE
D6
R/W
0
D5
R/W
0
DCLC13[2:0]
D4
R/W
0
D3
R/W
1
D2
R/W
0
DCLC2[2:0]
D1
R/W
1
D0
R/W
0
LEDs are off, VOUT set according to OV[3:0].
When DCLC2[2:0] and DCLC13[2:0] are both reset, the device operates in voltage regulation mode. The output voltage is set according
to OV[3:0].
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REGISTER1 DESCRIPTION
Memory location: 0x01
Description
Bits
Memory type
Default value
MODE_CTRL[1:0]
D7
D6
R/W
R/W
0
0
FC2[5:0]
D5
R/W
0
D4
R/W
1
D3
R/W
0
D2
R/W
0
D1
R/W
0
D0
R/W
0
Bit
Description
MODE_CTRL[1:0]
Mode Control bits.
00: Device in shutdown mode.
01: Device operates in video light mode.
10: Device operates in flash mode.
11: Device operates as constant voltage source.
To avoid device shutdown by video light safety timeout, MODE_CTRL[1:0] bits need to be refreshed within less
than 13.0s.
Writing to REGISTER1[7:6] automatically updates REGISTER2[7:6].
FC2[5:0]
Flash Current Control bits (LED2).
000000: 0mA. (1) (2)
000001: 25mA
000010: 50mA
000011: 75mA
000100: 100mA
000101: 125mA
000110: 150mA
000111: 175mA
001000: 200mA
001001: 225mA
001010: 250mA
001011: 275mA
001100: 300mA
001101: 325mA
001110: 350mA
001111: 375mA
010000: 400mA
010001: 425mA
010010: 450mA
010011: 475mA
010100: 500mA
010101: 525mA
010110: 550mA
010111: 575mA
011000: 600mA
011001: 625mA
011010: 650mA
011011: 675mA
011100: 700mA
011101: 725mA
011110: 750mA
011111: 775mA
100000 ... 111111: 800mA
(1)
(2)
LEDs are off, VOUT set according to OV[3:0].
When FC13[4:0] and FC2[5:0] are both reset, the device operates in voltage regulation mode. The output voltage is set according to
OV[3:0].
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REGISTER2 DESCRIPTION
Memory location: 0x02
Description
Bits
Memory type
Default value
MODE_CTRL[1:0]
D7
D6
R/W
R/W
0
0
ENVM
D5
R/W
0
D4
R/W
0
D3
R/W
1
FC13[4:0]
D2
R/W
0
D1
R/W
0
D0
R/W
0
Bit
Description
MODE_CTRL[1:0]
Mode Control bits.
00: Device in shutdown mode.
01: Device operates in video light mode.
10: Device operates in flash mode.
11: Device operates as constant voltage source.
To avoid device shutdown by video light safety timeout, MODE_CTRL[1:0] bits need to be refreshed within less
than 13.0s.
Writing to REGISTER2[6:5] automatically updates REGISTER1[6:5].
ENVM
Enable Voltage Mode bit.
0: Normal operation.
1: Forces the device into a constant voltage source.
In read mode, the ENVM bit is automatically updated to reflect the logic state of the ENVM input pin.
FC13[4:0]
Flash Current Control bits (LED1/3).
00000: 0mA. (1) (2)
00001: 25mA
00010: 50mA
00011: 75mA
00100: 100mA
00101: 125mA
00110: 150mA
00111: 175mA
01000: 200mA
01001: 225mA
01010: 250mA
01011: 275mA
01100: 300mA
01101: 325mA
01110: 350mA
01111: 375mA
10000 ... 11111: 400mA
(1)
(2)
34
LEDs are off, VOUT set according to OV[3:0].
When FC13[4:0] and FC2[5:0] are both reset, the device operates in voltage regulation mode. The output voltage is set according to
OV[3:0].
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REGISTER3 DESCRIPTION
Memory location: 0x03
Description
Bits
Memory type
Default value
STIM[2:0]
D7
R/W
1
D6
R/W
1
Bit
Description
STIM[2:0]
Safety Timer bits.
STIM[2:0]
RANGE 0
HPLF
D5
R/W
0
D4
R
0
SELSTIM (W)
TO ®)
D3
R
0
RANGE 1
STIM[2:0]
RANGE 0
RANGE 1
000
68.2ms
5.3ms
100
204.5ms
26.6ms
001
102.2ms
10.7ms
101
340.8ms
32.0ms
010
136.3ms
16.0ms
110
579.3ms
37.3ms
011
170.4ms
21.3ms
111
852ms
71.5ms
STT
SFT
Tx-MASK
D2
R/W
0
D1
R/W
0
D0
R/W
1
HPFL
High-Power LED Failure flag.
0: Proper LED operation.
1: LED failed (open or shorted).
High-power LED failure flag is reset after readout
SELSTIM
Safety Timer Selection Range (Write Only).
0: Safety timer range 0.
1: Safety timer range 1.
TO
Time-Out Flag (Read Only).
0: No time-out event occurred.
1: Time-out event occurred. Time-out flag is reset at re-start of the safety timer.
STT
Safety Timer Trigger bit.
0: LED safety timer is level sensitive.
1: LED safety timer is rising edge sensitive.
This bit is only valid for MODE_CTRL[1:0] = 10.
SFT
Start/Flash Timer bit.
In write mode, this bit initiates a flash strobe sequence.
0: No change in the high-power LED current.
1: High-power LED current ramps to the flash current level.
In read mode, this bit indicates the high-power LED status.
0: High-power LEDs are idle.
1: Ongoing high-power LED flash strobe.
Tx-MASK
Flash Blanking Control bit.
In write mode, this bit enables/disables the flash blanking/LED current reduction function.
0: Flash blanking disabled.
1: LED current is reduced to video light level when Tx-MASK input is high.
In read mode, this flag indicates whether or not the flash masking input has been activated. Tx-MASK flag is reset after
readout of the flag.
0: No flash blanking event occurred.
1: Tx-MASK input triggered.
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REGISTER4 DESCRIPTION
Memory location: 0x04
Description
Bits
Memory type
Default value
PG
D7
R/W
0
HOTDIE[1:0]
D6
D5
R
R
0
0
ILIM
D4
R/W
0
INC[3:0]
D3
R/W
0
D2
R/W
0
Bit
Description
PG
Power Good bit.
In write mode, this bit selects the functionality of the GPIO/PG output.
0: PG signal is routed to the GPIO port.
1: GPIO PORT VALUE bit is routed to the GPIO port.
In read mode, this bit indicates the output voltage conditions.
0: The converter is not operating within the voltage regulation limits.
1: The output voltage is within its nominal value.
HOTDIE[1:0]
Instantaneous Die Temperature bits.
00: TJ < +55°C
01: +55°C < TJ < +70°C
10: TJ > +70°C
11: Thermal shutdown tripped. Indicator flag is reset after readout.
ILIM
Inductor Valley Current Limit bit.
The ILIM bit can only be set before the device enters operation (i.e. initial shutdown state).
INDC[3:0]
36
ILIM BIT
SETTING
1250mA
Low
1750mA
High
D0
R/W
0
Indicator Light Control bits.
INDC[3:0]
(1)
(2)
VALLEY CURRENT
LIMIT SETTING
D1
R/W
0
PRIVACY INDICATOR
INDLED CHANNEL
PRIVACY INDICATOR
LED1-3 CHANNELS (1)
INDC[3:0]
0000
Privacy indicator turned off
1000
5% PWM dimming ratio
0001
INDLED current = 2.6mA (2)
1001
11% PWM dimming ratio
0010
INDLED current = 5.2mA (2)
1010
17% PWM dimming ratio
0011
INDLED current = 7.9mA
(2)
1011
23% PWM dimming ratio
0100
Privacy indicator turned off
1100
30% PWM dimming ratio
0101
INDLED current = 5.2mA (2)
1101
36% PWM dimming ratio
1110
48% PWM dimming ratio
1111
67% PWM dimming ratio
0110
INDLED current = 10.4mA
0111
INDLED current = 15.8mA
(2)
(2)
This mode of operation can only be activated for MODE_CTRL[1:0] = 01 & ENVM = 1.
The output node (VOUT) is internally pulled to ground.
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REGISTER5 DESCRIPTION
Memory location: 0x05
Description
Bits
Memory type
Default value
SELFCAL
ENPSM
D7
R/W
0
D6
R/W
1
DIR (W)
STSTRB1 ®)
D5
R/W
1
GPIO
GPIOTYPE
ENLED3
ENLED2
ENLED1
D4
R/W
0
D3
R/W
1
D2
R/W
0
D1
R/W
1
D0
R/W
0
Bit
Description
SELFCAL
High-Current LED Forward Voltage Self-Calibration Start bit.
In write mode, this bit enables/disables the output voltage vs. LED forward voltage/current self-calibration procedure.
0: Self-calibration disabled.
1: Self-calibration enabled.
In read mode, this bit returns the status of the self-calibration procedure.
0: Self-calibration ongoing
1: Self-calibration done Notice that this bit is only being reset at the (re-)start of a calibration cycle.
ENPSM
Enable / Disable Power-Save Mode bit.
0: Power-save mode disabled.
1: Power-save mode enabled.
STSTRB1
STRB1 Input Status bit (Read Only).
This bit indicates the logic state on the STRB1 state.
DIR
GPIO Direction bit.
0: GPIO configured as input.
1: GPIO configured as output.
GPIO
GPIO Port Value.
This bit contains the GPIO port value.
GPIOTYPE
GPIO Port Type.
0: GPIO is configured as push-pull output.
1: GPIO is configured as open-drain output.
ENLED3
Enable / Disable High-Current LED3 bit.
0: LED3 input is disabled.
1: LED3 input is enabled.
ENLED2
Enable / Disable High-Current LED2 bit.
0: LED2 input is disabled.
1: LED2 input is enabled.
ENLED1
Enable / Disable High-Current LED1 bit.
0: LED1 input is disabled.
1: LED1 input is enabled.
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REGISTER6 DESCRIPTION
Memory location: 0x06
Description
Bits
Memory type
Default value
ENTS
D7
R/W
0
LEDHOT
D6
R/W
0
LEDWARN
D5
R
0
LEDHDR
D4
R
0
OV[3:0]
D3
R/W
1
D2
R/W
0
D1
R/W
0
D0
R/W
1
Bit
Description
ENTS
Enable / Disable LED Temperature Monitoring.
0: LED temperature monitoring disabled.
1: LED temperature monitoring enabled.
LEDHOT
LED Excessive Temperature Flag.
This bit can be reset by writing a logic level zero.
0: TS input voltage > 0.345V.
1: TS input voltage < 0.345V.
LEDWARN
LED Temperature Warning Flag (Read Only).
This flag is reset after readout.
0: TS input voltage > 1.05V.
1: TS input voltage < 1.05V.
LEDHDR
LED High-Current Regulator Headroom Voltage Monitoring bit.
This bit returns the headroom voltage status of the LED high-current regulators. This value is being updated at the end of a
flash strobe, prior to the LED current ramp-down phase.
0: Low headroom voltage.
1: Sufficient headroom voltage.
0V[3:0]
Output Voltage Selection bits.
In read mode, these bits return the result of the high-current LED forward voltage self-calibration procedure.
In write mode, these bits are used to set the target output voltage (refer to voltage regulation mode). In applications
requiring dynamic voltage control, care should be take to set the new target code after voltage mode operation has been
enabled (MODE_CTRL[1:0] = 11 and/or ENVM bit = 1).
38
OV[3:0]
Target Output Voltage
0000
3.825V
0001
3.950V
0010
4.075V
0011
4.200V
0100
4.325V
0101
4.450V
0110
4.575V
0111
4.700V
1000
4.825V
1001
4.950V
1010
5.075V
1011
5.200V
1100
5.325V
1101
5.450V
1110
5.575V
1111
5.700V
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REGISTER7 DESCRIPTION
Memory location: 0x07
Description
Bits
Memory type
Default value
ENBATMON
D7
R/W
0
D6
R/W
1
BATDROOP[2:0]
D5
R/W
0
D4
R/W
0
Bit
Description
ENBATMON
Enable / Disable Battery Voltage Droop Monitoring Bit
0: Battery voltage droop monitoring disabled.
1: Battery voltage droop monitoring enabled.
BATDROOP[2:0]
Battery Voltage Droop
000: 50mV
001: 75mV
010: 100mV
011: 125mV
100: 150mV
101: 175mV
110: 200mV
111: 225mV
REVID[2:0]
Silicon Revision ID
FREE
D3
R/W
0
D2
R
1
REVID[2:0]
D1
R
1
D0
R
0
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APPLICATION INFORMATION
•
•
•
•
•
•
•
•
•
•
INDUCTOR SELECTION
INPUT CAPACITOR
OUTPUT CAPACITOR
NTC SELECTION
CHECKING LOOP STABILITY
LED FLASH CURRENT LEVEL OPTIMIZATION vs. BATTERY DROOP
LED FORWARD VOLTAGE CALIBRATION
LAYOUT CONSIDERATIONS
THERMAL INFORMATION
TYPICAL APPLICATIONS
INDUCTOR SELECTION
A boost converter requires two main passive components for storing energy during the conversion. A boost
inductor and a storage capacitor at the output are required.
The TPS6131x device integrates current-limit protection circuitry. The valley current of the PMOS rectifier is
sensed to limit the maximum current flowing through the synchronous rectifier and the inductor. The valley peak
current limit (1250mA/1750mA) is user selectable via the I2C interface.
In order to optimize solution size the TPS6131x device has been designed to operate with inductance values
between a minimum of 1.3 mH and maximum of 2.9 mH. In typical high-current white LED applications a 2.2mH
inductance is recommended.
The highest peak current through the inductor and the power switch depends on the output load, the input and
output voltages. The maximum average inductor current and the maximum inductor peak current can be
estimated using Equation 2 and Equation 3:
VOUT
IL » IOUT ´
η ´ VIN
(2)
IL(PEAK) =
VIN ´ D
2 ´ f ´ L
+
IOUT
(1 - D) ´ h
with D =
VOUT - VIN
VOUT
(3)
With
f = switching frequency (2MHz)
L = inductance value (2.2mH)
h = estimated efficiency (85%)
The losses in the inductor caused by magnetic hysteresis losses and copper losses are a major parameter for
total circuit efficiency.
Table 7. List of Inductors
MANUFACTURER
SERIES
DIMENSIONS
TDK
VLF3014AT
2.6mm x 2.8mm x 1.4mm max. height
COILCRAFT
LPS3015
3.0mm x 3.0mm x 1.5mm max. height
MURATA
LQH2HPN
2.5mm x 2.0mm x 1.2mm max. height
TOKO
FDSE0312
3.0mm x 3.0mm x 1.2mm max. height
MURATA
LQM32PN
3.2mm x 2.5mm x 1.0mm max. height
40
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ILIM SETTINGS
1250mA (typ.)
1750mA (typ.)
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INPUT CAPACITOR
For good input-voltage filtering, low ESR ceramic capacitors are recommended. A 10mF input capacitor is
recommended to improve transient behavior of the regulator and EMI behavior of the total power supply circuit.
The input capacitor should be placed as close as possible to the input pin of the converter.
OUTPUT CAPACITOR
The major parameter necessary to define the output capacitor is the maximum allowed output-voltage ripple of
the converter. This ripple is determined by two parameters of the capacitor, the capacitance and the ESR. It is
possible to calculate the minimum capacitance needed for the defined ripple, supposing that the ESR is zero, by
using Equation 4:
IOUT × (V OUT - VIN)
Cmin »
f ´ DV ´ V OUT
(4)
Parameter f is the switching frequency and ΔV is the maximum allowed ripple.
With a chosen ripple voltage of 10mV, a minimum capacitance of 10mF is needed. The total ripple is larger due
to the ESR of the output capacitor. This additional component of the ripple can be calculated using Equation 5:
DVERR = IOUT ´ RESR
(5)
The total ripple is the sum of the ripple caused by the capacitance and the ripple caused by the ESR of the
capacitor. Additional ripple is caused by load transients. This means that the output capacitor has to completely
supply the load during the charging phase of the inductor. A reasonable value of the output capacitance depends
on the speed of the load transients and the load current during the load change.
For the standard current white LED application, a minimum of 3mF effective output capacitance is usually
required when operating with 2.2mH (typ) inductors. For solution size reasons, this is usually one or more
X5R/X7R ceramic capacitors.
Depending on the material, size and therefore margin to the rated voltage of the used output capacitor,
degradation on the effective capacitance can be observed. This loss of capacitance is related to the DC bias
voltage applied. It is therefore always recommended to check that the selected capacitors are showing enough
effective capacitance under real operating conditions.
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NTC SELECTION
The TPS6131x requires a negative thermistor (NTC) for sensing the LED temperature. Once the temperature
monitoring feature is activated, a regulated bias current (c.a. 24mA) is driven out of the TS port to produce a
voltage across the thermistor.
If the temperature of the NTC-thermistor rises due to the heat dissipated by the LED, the voltage on the TS input
pin decreases. When this voltage goes below the “warning threshold”, the LEDWARN bit in REGISTER6 is set.
This flag is cleared by reading the register.
If the voltage on the TS input decreases further and falls below “hot threshold”, the LEDHOT bit in REGISTER6
is set and the device goes automatically in shutdown mode to avoid damaging the LED. This status is latched
until the LEDHOT flag gets cleared by software.
The selection of the NTC-thermistor value strongly depends on the power dissipated by the LED and all
components surrounding the temperature sensor and on the cooling capabilities of each specific application. With
a 220kΩ (at 25°C) thermistor, the valid temperature window is set between 60°C to 90°C. The temperature
window can be enlarged by adding external resistors to the TS pin application circuit. In order to obtain proper
triggering of the LEDWARN and LEDHOT flags in noisy environments, the TS signal may require additional
filtering capacitance.
Figure 56. Temperature Monitoring Characteristic
Table 8. List of Negative Thermistor (NTC)
42
MANUFACTURER
PART NUMBER
VALUE
MURATA
NCP18WM224J03RB
220kΩ
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CHECKING LOOP STABILITY
The first step of circuit and stability evaluation is to examine the following signals from a steady-state
perspective:
• Switching node, SW
• Inductor current, IL
• Output ripple voltage, VOUT(AC)
These are the basic signals that must be measured when evaluating a switching converter. If the switching
waveform shows large duty-cycle jitter or the output voltage or inductor current shows oscillations, the regulation
loop may be unstable. This is often a result of improper board layout and/or L-C combination.
As a next step in the evaluation of the regulation loop, test the load transient response. VOUT can be monitored
for settling time, overshoot or ringing that helps judge the converter's stability. With no ringing, the loop has
usually more than 45° of phase margin.
Because the damping factor of the circuitry is directly related to several resistive parameters (e.g., MOSFET
rDS(on)) that are temperature dependant, the loop stability should be analyzed over the input voltage range, output
current range, and temperature range.
LED FLASH CURRENT LEVEL OPTIMIZATION vs. BATTERY DROOP
In cell phone applications, the camera engine is normally specified over an operating temperature range down to
0°C or –10°C. In order to achieve a reliable system operation, the LED flash current needs to be rated according
to the maximum tolerable battery voltage drop (i.e. highest battery impedance, lowest ambient temperature).
To dynamically optimize the LED flash current (i.e. light output) vs. battery state-of-charge and temperature, we
could consider the following self-adjustment procedure. This algorithm could be embedded into the
auto-exposure, auto white-balance or red-eye reduction pre-flash algorithms.
Base-band processor to compute battery ESR
~
~
Battery Voltage
~
~
Battery Voltage
Measurement
tCRITICAL
Pre-Flash
Flash (Capture)
(3 ms)
(133 ms)
~
~
IFLASH
(Optimum)
LED Current
~
~
~
~
Flash Synchronization
(Camera ISP)
Figure 57. Image Capture Sequence
•
Phase 1: Pre-Flash, Battery Impedance Estimation
The battery voltage usually drops by a few hundreds of millivolts during a high-power flash strobe. For short
durations, this voltage droop should not be subject to the battery intrinsic capacitance (i.e. relaxation effect)
but rather to its cell impedance.
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Based on the state of the Tx-MASK input, the battery voltage drop (during pre-flash) and the LED current
level, the base-band processor can compute an estimated cell-impedance value (ESR).
Depending on the ambient temperature, the battery state-of-charge (SoC), the flash (capture) duration and
the actual status of the various RF interfaces, the base-band processor can determine a safe battery voltage
droop (to be tolerated during the forthcoming strobe sequence) as well as a maximum flash current rating.
The maximum flash current setting can be estimated by considering nominal LEDs and approximately 85%
power efficiency in the driver.
Phase 2: Battery Loading Monitoring Prior To Image Capture
For a reliable system operation, the base-band processor should make sure that no 'parasitic' high-current
load suddenly impacts the budgeted battery voltage sag. The most critical timing is referenced as tCRITICAL.
The interrupt subroutine (running on the base-band processor) should be ready to detect any 'parasitic'
battery load event that could occur prior to the image capture (refer to SFT bit description). In such a
situation, the battery voltage droop budget and the maximum LED current settings would need to be revised.
Figure 58. 900mAh, Li-Ion Battery Transient Response vs. SoC and Temperature
44
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LED FORWARD VOLTAGE CALIBRATION
High-power LEDs tend to exhibit a wide forward voltage distribution. The TPS6131x device integrates a
self-calibration procedure that can be used to determine the optimum super-capacitor pre-charge voltage based
on the actual worst case LED forward voltage and ESR of the storage capacitor. This calibration procedure is
meant to start at a minimum output voltage, and can be initiated by writing the SELFCAL bit (preferably with
MODE_CTRL[1:0] = 00, ENVM = 0).
The calibration procedure monitors the sense voltage across the low-side current regulators (according to
ENLED[3:1] bits setting) and registers the worst case LED (i.e. the LED featuring the largest forward voltage).
The TPS6131x device automatically sweeps through its output voltage range and performs a short duration flash
strobe for each step (refer to FC13[4:0] and FC2[5:0] bits settings).
The sequence is stopped as soon as the device detects that each of the low-side current regulators have enough
headroom voltage (i.e. 400mV typ.). The device returns the according output voltage in the register OV[3:0] and
sets the SELFCAL bit. This bit is only being reset at the (re-)start of a calibration cycle. In other words, when
SELFCAL is asserted the output voltage register (OV[3:0]) returns the result of the last calibration sequence.
Output Voltage, VOUT
~200 ms
ESR x ILED
Feedback Sense
Comparator Information
VBAT
Power Good, PG
~200 ms
LED Flash Current, IFLASH
Feedback Sense Comparator Output
VLED > 400 mV
OV[3:0]
0000
0001
0010
0011
0100
0101
Self-Calibration,
SELFCAL bit (write)
Self-Calibration,
SELFCAL bit (read)
X
Figure 59. LED Forward Voltage Calibration Principle
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TPS61310
SLVS978 – MARCH 2010
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LAYOUT CONSIDERATIONS
As for all switching power supplies, the layout is an important step in the design, especially at high peak currents
and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as
well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground
tracks.
The input capacitor, output capacitor, and the inductor should be placed as close as possible to the IC. Use a
common ground node for power ground and a different one for control ground to minimize the effects of ground
noise. Connect these ground nodes at any place close to one of the ground pins of the IC.
To lay out the control ground, it is recommended to use short traces as well, separated from the power ground
traces. This avoids ground shift problems, which can occur due to superimposition of power ground current and
control ground current.
L1
GND
SDA
COUT
INDLED
B2: SCL
B3: NRESET
C3: Tx_MASK
D3: STRB1
D4: GPIO/PG
STRB0
1
TS
CIN
GND
VIN
LED2
LED1 LED3
Figure 60. Suggested Layout (Top)
46
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THERMAL INFORMATION
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependant issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the
power-dissipation limits of a given component.
Three basic approaches for enhancing thermal performance are listed below:
• Improving the power dissipation capability of the PCB design
• Improving the thermal coupling of the component to the PCB
• Introducing airflow in the system
Junction-to-ambient thermal resistance is highly dependent on application and board layout. In applications
where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board
design. The maximum junction temperature (TJ) of the TPS6131x is 150°C.
PDIS - Single Pulse Constant Power Dissipation - W
The maximum power dissipation is especially critical when the device operates in the linear down mode at high
LED current. For single-pulse power thermal analysis (e.g., flash strobe), the allowable power dissipation for the
device is given by Figure 61. These values are derived using the reference design.
10
9
8
TJ = 65°C rise
7
6
5
4
3
2
TJ = 40°C rise
1
No Airflow
0
0
20
40
60
80 100 120 140 160 180 200
Pulse Width - ms
Figure 61. Single Pulse Power Capability
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TYPICAL APPLICATIONS
TPS61310
L
2.2 mH
SW
SW
VOUT
CO
AVIN
2.5 V..5.5 V
10 mF
CI
HARDWARE RESET
CAMERA ENGINE
FLASH SYNCHRONIZATION
NRESET
LED 1
STRB0
LED 2
STRB1
LED 3
D1
D2
INDLED
SCL
SDA
I2C I/F
RF PA TX ACTIVE
Privacy
Indicator
Tx-MASK
NTC
TS
GPIO/PG
220k
AGND
PGND
PGND
Figure 62. 2x 600mA High Power White LED Solution Featuring Privacy Indicator
TPS61310
L
2.2 mH
SW
SW
VOUT
CO
AVIN
2.5 V..5.5 V
10 mF
CI
D1
Privacy
Indicator
HARDWARE RESET
CAMERA ENGINE
FLASH SYNCHRONIZATION
NRESET
LED 1
STRB0
LED 2
STRB1
LED 3
INDLED
I2C I/F
RF PA TX ACTIVE
SCL
SDA
Tx-MASK
NTC
TS
GPIO/PG
220k
AGND
PGND
PGND
Figure 63. 1200mA High Power White LED Solution Featuring 'Back-Drive' Privacy Indicator
48
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SLVS978 – MARCH 2010
PACKAGE SUMMARY
CHIP SCALE PACKAGE
(BOTTOM VIEW)
D
A4
A3
A2
A1
B4
B3
B2
B1
C4
C3
C2
C1
D4
D3
D2
D1
E4
E3
E2
E1
CHIP SCALE PACKAGE
(TOP VIEW)
YMLLLLS
TPS613__
A1
Code:
YM — Year Month date code
LLLL — Lot trace code
S — Assembly site code
E
CHIP SCALE PACKAGE DIMENSIONS
The TPS6131x device is available in a 20-bump chip scale package (YFF, NanoFree™). The package
dimensions are given as:
• D = 2170 ±30 mm
• E = 1928 ±30 mm
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