TPS61158
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SLVSBR3 – MAY 2013
30V WLED Driver with Integrated Power Diode
Check for Samples: TPS61158
FEATURES
DESCRIPTION
•
•
•
With 30V rated integrated switch FET and power
diode, the TPS61158 is a boost converter that drives
LEDs in series. The boost converter runs at 750kHz
fixed switching frequency to reduce output ripple,
improve conversion efficiency, and allows for the use
of small external components.
1
•
•
•
•
•
•
•
•
2.7V to 5.5V Input Voltage Range
28V Open LED Protection (up to 8 LEDs)
Integrated 0.6A 30V Internal Switch FET and
Power Diode
750kHz Switching Frequency
Flexible Digital and PWM Brightness Control
– 1-Wire Control Interface (EasyScale)
– PWM Dimming Control Interface
Up to 100:1 PWM Dimming Ratio
Integrated Loop Compensation
Built-in Soft Start
Built-in WLED Open protection
Thermal Shutdown
2mm x 2mm x 0.8mm 6-pin QFN Package with
Thermal Pad
APPLICATIONS
•
•
•
•
•
•
Feature Phones
Smart Phones
Portable Media Players
Ultra Mobile Devices
GPS Receivers
Backlight for Small and Media Form Factor
LCD Display
The default white LED current is set with the external
sensor resistor RFB, and the feedback voltage is
regulated to 200mV, as shown in the typical
application. During the operation, the LED current can
be controlled using the 1-wire digital interface
(Easyscale™ protocol) through the CTRL pin.
Alternatively, a pulse width modulation (PWM) signal
can be applied to the CTRL pin through which the
duty cycle determines the feedback reference
voltage. In either digital or PWM mode, the
TPS61158 does not burst the LED current; therefore,
it does not generate audible noises on the output
capacitor. For maximum protection, the device
features integrated open LED protection that disables
the TPS61158 to prevent the output voltage from
exceeding the IC's absolute maximum voltage ratings
during open LED conditions. The TPS61158 is
available in a space-saving, 2mm × 2mm QFN
package with thermal pad.
TYPICAL APPLICATION
L
22µH
2.7V ~ 5.5V
Up to 8 LEDs
VBAT
Cin
2.2µF
VIN
PWM or 1-wire
dimming control
Cout
1µF
TPS61158
LX
CTRL
VOUT
GND
FB
RFB
10
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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TPS61158
SLVSBR3 – MAY 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION (1)
(1)
ORDERING
PACKAGE
PACKAGE MARKING
TPS61158DRV
QFN 2 x 2 6L - DRV
SIW
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
VALUE
MIN
Voltage range (2)
ESD rating
MAX
UNIT
VIN
–0.3
6
V
VOUT, LX
–0.3
30
V
FB, CTRL
–0.3
7
V
2
kV
500
V
HBM
CDM
See Thermal
Information Table
Continuous power dissipation
Operating junction temperature range
–40
150
°C
Storage temperature range
–65
150
°C
(1)
(2)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
THERMAL INFORMATION
THERMAL METRIC (1)
Junction-to-ambient thermal resistance (2)
θJA
(3)
TPS61158
DRV (6 PINS)
70.4
θJCtop
Junction-to-case (top) thermal resistance
θJB
Junction-to-board thermal resistance (4)
39.8
ψJT
Junction-to-top characterization parameter (5)
2.5
ψJB
Junction-to-board characterization parameter (6)
40.2
θJCbot
Junction-to-case (bottom) thermal resistance (7)
10.2
(1)
(2)
(3)
(4)
(5)
(6)
(7)
2
UNITS
94.8
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
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RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VIN
Input voltage range
2.7
5.5
VOUT
Output voltage range
Vin
29
V
IOUT
Output load current
30
mA
L
Inductor
22
µH
CI
Input capacitor
µF
CO
Output capacitor
FPWM
Input PWM signal frequency range
TA
Operating ambient temperature
TJ
Operating junction temperature
10
V
1.0
10
0.47
2.2
µF
20
100
kHz
–40
85
°C
–40
125
°C
ELECTRICAL CHARACTERISTICS
VIN=3.6V, CTRL=High, IFB current=20mA, IFB voltage=200mV, TA = –40°C to 85°C, typical values are at TA = 25°C (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VIN ramp down
2.2
2.35
VIN ramp up
2.5
2.65
UNIT
POWER SUPPLY
VIN
Input voltage range
VIN_UVLO
VIN under voltage lockout threshold
VIN_HYS
VIN under voltage lockout hysteresis
IQ
ISD
2.7
5.5
275
Operating quiescent current into VIN
Shutdown current
V
V
mV
Device enable, no switching and no load
(VFB = 0.4V)
0.3
0.5
Device enable, switching 750kHz
and no load (VFB = 0V)
0.5
1.65
CTRL = GND
0.1
1
mA
µA
CONTROL LOGIC AND TIMING
VH
CTRL logic high voltage
VL
CTRL logic Low voltage
1.2
RPD
CTRL pin internal pull-down resistor
VCTRL = 1.8 V
tSD
CTRL pulse width to shutdown
CTRL from high to low
3.5
194
V
0.4
300
V
kΩ
ms
VOLTAGE AND CURRENT REGULATION
VREF
Voltage feedback regulation voltage
Duty = 100%
IFB
FB pin bias current
VFB = 200mV
tREF
VREF filter time constant
200
206
mV
2
µA
230
µs
POWER SWITCH AND DIODE
RDS(ON)
N-channel MOSFET on-resistance
VIN = 3.6 V, TA = 25°C,
IOUT = 100 mA
VF
Power diode forward voltage
IDIODE = 0.2A
ILEAK_LX
LX pin leakage current
VLX = 28V
Ω
0.6
1
0.75
1
V
0.1
2
µA
600
750
900
kHz
88%
94%
OSCILLATOR
fSW
Dmax
Oscillator frequency
Maximum duty cycle of boost switching
VFB = 0V, measured on the drive signal
of the switch MOSFET
PROTECTION AND SOFTSTART
ILIM
NMOS current limit
ILIM_Start
Start up current limit
tILIM_Start
Time step for start up current limit
VOVP
Open LED protection threshold
VIN = 3.6V, D = DMAX, TA = 0°C to 85°C,
Tested at VOUT pin
0.5
27.5
0.6
0.7
mA
8
ms
28.2
29
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ELECTRICAL CHARACTERISTICS (continued)
VIN=3.6V, CTRL=High, IFB current=20mA, IFB voltage=200mV, TA = –40°C to 85°C, typical values are at TA = 25°C (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
EasyScale TIMING
tes_detect
Easy Scale detection time (1)
tes_delay
Easy Scale detection delay
tes_win
Easy Scale detection window time
tstart
Start time of program stream
tEOS
End time of program stream
tH_LB
High time of low bit
CTRL low
Measured from CTRL high
Logic 0
450
µs
100
µs
3.5
ms
3.5
µs
3.5
600
µs
3.5
300
µs
600
µs
2x
tL_LB
Low time of low bit
Logic 0
tH_HB
High time of high bit
Logic 1
2x
tL_HB
600
µs
tL_HB
Low time of high bit
Logic 1
3.5
300
µs
VACKNL
Acknowledge output voltage low
Open drain, Rpullup = 15kΩ to VIN
0.4
V
tvalACK
Acknowledge valid time
See (2)
3.5
µs
tACKN
Duration of acknowledge condition
See (2)
900
µs
tH_LB
THERMAL SHUTDOWN
Tshutdown
Thermal shutdown threshold
160
°C
Thys
Thermal shutdown hysteresis
15
°C
(1)
(2)
4
To select EasyScale mode, the CTRL pin has to be low for more than tes_detect during tes_win
Acknowledge condition active 0, this condition will only be applied in case the RFA bit is set. Open drain output, line needs to be pulled
high by the host with resistor load.
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DEVICE INFORMATION
(TOP VIEW)
CTRL
1
VIN
2
VOUT
3
Thermal
pad
6
LX
5
GND
4
FB
PIN FUNCTIONS
PIN
NO.
NAME
I/O
DESCRIPTION
I
Control pin of the boost converter. It is a multi-functional pin which can be used for enable control, PWM and
digital dimming.
VIN
I
The input supply pin for the IC. Connect VIN to a supply voltage between 2.7V and 5.5V.
VOUT
O
Output of the boost converter.
4
FB
I
Feedback pin for current. Connect the sense resistor from FB to GND.
5
GND
O
Ground
6
LX
I
This is the switching node of the IC. Connect the inductor between the VIN and LX pin.
7
Thermal
Pad
1
CTRL
2
3
The thermal pad should be soldered to the analog ground plane. If possible, use thermal via to connect to
ground plane for ideal power dissipation.
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FUNCTIONAL BLOCK DIAGRAM
L
VBAT
Cin
2.2µF
22µH
LX
VIN
VOUT
UVLO
Cout
1µF
Gate driver
control
OVP
detection
VOVP
Ramp
Generator
OSC
+
Current
Sensor
Rsense
Comp
Soft
start-up
FB
Error
Amp
CTRL
VREF
RFB
10
PWM & EasyScale
Reference Control
GND
6
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TYPICAL CHARACTERISTICS
TABLE OF GRAPHS
TITLE
DESCRIPTION
FIGURE
Dimming Efficiency
VIN = 3.6V; 6 LEDs (VOUT = 18.3V), 8 LEDs (VOUT = 24.4V); RFB = 10Ohm; PWM Freq =
40kHz; L = 22µH
Figure 1
Dimming Efficiency
VIN = 3V, 3.6V, 4.2V, 5V; 6 LEDs (VOUT = 18.3V); RFB = 10Ohm; PWM Freq = 40kHz; L = 22µH
Figure 2
Dimming Efficiency
VIN = 3V, 3.6V, 4.2V, 5V; 8 LEDs (VOUT = 24.4V); RFB = 10Ohm; PWM Freq = 40kHz; L = 22µH
Figure 3
Switch Current Limit vs
Temperature
VIN = 3.6V
Figure 4
Switch Current Limit vs VIN TA = 25°C
Figure 5
FB Voltage vs EasyScale
Step
VIN = 3.6V
Figure 6
FB voltage vs PWM duty
cycle
VIN = 3.6V; PWM Freq = 20kHz and 40kHz
Figure 7
Output Ripple at PWM
Dimming
VIN = 3.6V; 8 LEDs (VOUT = 24.4V); RFB = 10Ohm; PWM Freq = 20kHz; L = 22µH
Figure 8
Switching Waveform
VIN = 3.6V; 8 LEDs (VOUT = 24.4V); RFB = 10Ohm; PWM Duty = 100%; L = 22µH
Figure 9
Switching Waveform
VIN = 3.6V; 8 LEDs (VOUT = 24.4V); RFB = 10Ohm; PWM Freq = 20kHz; PWM Duty = 25%; L =
22µH
Figure 10
Startup Waveform
VIN = 3.6V; 8 LEDs (VOUT = 24.4V); RFB = 10Ohm; PWM Duty = 100%; L = 22µH
Figure 11
Startup Waveform
VIN = 3.6V; 8 LEDs (VOUT = 24.4V); RFB = 10Ohm; PWM Freq = 20kHz; PWM Duty = 25%; L =
22µH
Figure 12
Shutdown Waveform
VIN = 3.6V; 8 LEDs (VOUT = 24.4V); RFB = 10Ohm; PWM Duty = 100%; L = 22µH
Figure 13
Shutdown Waveform
VIN = 3.6V; 8 LEDs (VOUT = 24.4V); RFB = 10Ohm; PWM Freq = 20kHz; PWM Duty = 25%; L =
22µH
Figure 14
Open LED Protection
VIN = 3.6V; 6 LEDs (VOUT = 18.3V); RFB = 10Ohm; PWM Duty = 100%; L = 22µH
Figure 15
EFFICIENCY
vs
DIMMING DUTY CYCLE
EFFICIENCY
vs
DIMMING DUTY CYCLE
100
100
VIN = 3.6V
RFB = 10
90
Efficiency (%)
Efficiency (%)
90
80
70
60
6 LEDs
8 LEDs
50
20
40
60
Dimming Duty Cycle (%)
70
60
6 LEDs (VOUT = 18.3V)
8 LEDs (VOUT = 24.4V
0
80
80
100
VIN
V
V
IN ==33V
V
V
VIN
3.6V
IN ==3.6
V
V
VIN
4.2V
IN ==4.2
V
V
VIN
IN ==55V
6 LEDs (VOUT = 18.3V)
RFB = 10
50
0
20
40
60
80
100
Dimming Duty Cycle (%)
Figure 1.
Figure 2.
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EFFICIENCY
vs
DIMMING DUTY CYCLE
SWITCH CURRENT LIMIT
vs
DUTY CYCLE
0.7
Ilim - SwitchCurrent Limit (A)
100
Efficiency (%)
90
80
70
60
VIN
= 3V
V
IN = 3 V
VIN
3.6V
V
V
IN ==3.6
V
V
VIN
4.2V
IN ==4.2
V
V
VIN
IN ==55V
8 LEDs (VOUT = 24.4V)
RFB = 10
50
0
20
40
60
80
0.65
0.6
0.55
VIN = 3.6V
0.5
-60
100
-40
-20
0
40
60
Figure 3.
Figure 4.
SWITCH CURRENT LIMIT
vs
TEMPERATURE
FB VOLTAGE
vs
EASYSCALE STEP
1
200
0.9
180
0.8
160
VFB - FB Voltage (mV)
Ilim - Switch Current Limit (A)
20
0.7
0.6
0.5
0.4
0.3
0.2
0.1
Temperature =
80
100
120
140
Temperature (oC)
Dimming Duty Cycle (%)
25oC
140
120
100
80
60
40
20
0
VFB (mV)
0
2.5
3
3.5
4
4.5
5
5.5
6
0
2
4
6
8 10 12 14 16 18 20 22 24 26 28 30 32
VIN - Input Voltage (V)
EasyScale Step
Figure 5.
Figure 6.
FB VOLTAGE
vs
DIMMING DUTY CYCLE
OUTPUT RIPPLE at PWM DIMMING
250
DimmingDuty = 50% @ 20kHz
VFB - FB Voltage (mV)
CTRL 2V/div
200
150
VOUT (AC) 100mV/div
100
50
ILED10mA/div
20kHz
40kHz
0
0
20
40
60
80
100
Dimming Duty Cycle (%)
Figure 7.
8
Figure 8.
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SWITCHING WAVEFORM - DIMMING DUTY = 100%
SW 20V/div
SWITCHING WAVEFORM - DIMMING DUTY = 25%
SW 20V/div
VOUT (AC) 200mV/div
VOUT (AC) 50mV/div
IL100mA/div
IL100mA/div
Dimming Duty = 100%
Dimming Duty = 25%
Figure 9.
Figure 10.
START-UP DIMMING DUTY = 100%
START-UP DIMMING DUTY = 25%
CTRL 2V/div
CTRL 2V/div
VOUT 20V/div
VOUT 20V/div
ILED20mA/div
ILED5mA/div
IL200mA/div
IL100mA/div
Dimming Duty = 100%
Dimming Duty = 25%
Figure 11.
Figure 12.
SHUTDOWN DIMMING DUTY = 100%
SHUTDOWN DIMMING DUTY = 25%
CTRL 2V/div
CTRL 2V/div
VOUT 20V/div
VOUT 20V/div
ILED20mA/div
ILED5mA/div
IL200mA/div
IL100mA/div
Dimming Duty = 25%
Dimming Duty = 100%
Figure 13.
Figure 14.
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OPEN LED PROTECTION
VFB 200mV/div
VOUT 10V/div
ILED20mA/div
IL200mA/div
Figure 15.
10
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DETAILED DESCRIPTION
OPERATION
The TPS61158 is a high efficiency boost converter with integrated power diode in a small package size. The
device is ideal for driving white LED in series. The serial LED connection provides even illumination by sourcing
the same output current through all LEDs, eliminating the need for expensive factory calibration. The device
integrates a 30V/0.6A low side switch MOSFET and a 30V power diode, and operates in pulse width modulation
(PWM) with 750 kHz fixed switching frequency. For operation see the block diagram. The duty cycle of the
converter is set by the error amplifier output and the current signal applied to the PWM control comparator. The
control architecture is based on traditional current-mode control; therefore, slope compensation is added to the
current signal to allow stable operation for duty cycles larger than 50%. The feedback loop regulates the FB pin
to a low reference voltage (200mV typical), reducing the power dissipation in the current sense resistor.
SOFT START-UP
Soft-start circuitry is integrated into the IC to avoid a high inrush current during start-up. After the device is
enabled, the voltage at FB pin ramps up to the reference voltage in 32 steps with each step taking 341μs. This
ensures that the output voltage rises slowly to reduce the input current. Additionally, during the start up process,
the current limit of the switch is set to half of the normal current limit spec. During this period, the input current is
kept below 360mA (typical). See the start-up waveform of a typical example.
SHUTDOWN
The TPS61158 enters shutdown mode when the CTRL voltage is logic low for more than 3.5ms. During
shutdown, the input supply current for the device is less than 1μA (max). Although the internal FET does not
switch in shutdown mode, there is still a DC current path between the input and the LEDs through the inductor
and the power diode. The minimum forward voltage of the LED array must exceed the maximum input voltage to
ensure that the LEDs remain off in shutdown. In the typical application with two or more LEDs, the forward
voltage is large enough to reverse bias the diode and keep leakage current low.
CURRENT PROGRAM
The FB voltage is regulated by a low 0.2V reference voltage. The LED current is programmed externally using a
current-sense resistor RFB in series with the LED string. The value of the RFB is calculated using Equation 1:
V
RFB = FB
ILED
(1)
Where:
RFB = current sense resistor at FB pin
VFB = 200mV (regulated voltage of FB pin)
ILED = full-scale output current of LEDs
The output current tolerance depends on the FB voltage accuracy and the current sensor resistor accuracy.
LED BRIGHTNESS DIMMING MODE SELECTION
The CTRL pin is used for the control input for both dimming modes, PWM dimming and 1 wire dimming. The
dimming mode for the TPS61158 is selected each time the device is enabled. The default dimming mode is
PWM dimming. To enter the 1 wire mode, the following digital pattern on the CTRL pin must be recognized by
the IC every time the IC starts from the shutdown mode.
1. Pull CTRL pin high to enable the TPS61158, and to start the 1 wire detection window.
2. After the EasyScale detection delay (tes_delay, 100μs) expires, drive CTRL low for more than the EasyScale
detection time (tes_detect, 450μs).
3. The CTRL pin has to be low for more than EasyScale detection time before the EasyScale detection window
(tes_win, 3.5ms) expires. EasyScale detection window starts from the first CTRL pin low to high transition.
The IC immediately enters the 1 wire mode once the above 3 conditions are met. The EasyScale communication
can start before the detection window expires. Once the dimming mode is programmed, it can not be changed
without another start up. This means the IC needs to be shutdown by pulling the CTRL low for 3.5ms and
restarts. See the Dimming Mode Detection and Soft Start (Figure 16) for a graphical explanation.
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Insert battery
PWM signal
high
CTRL
low
PWM
mode
xxxxxxx
xxxxxxx
xxxxxxx
Startup
delay
FB ramp
Shutdown delay
200mV x duty cycle
FB
t
Insert battery
Enter ES mode
Programming
code
Enter ES mode
Timing window
Programming code
high
CTRL
low
ES detect time
ES
mode
Shutdown
xxxxxxx
xxxxxxxxx
FB ramp
delay
ES detect delay
FB ramp
Programmed value
(if not programmed, 200mV default )
FB
Startup delay
IC
Shutdown
50mV
Startup delay
xxx
50mV
Figure 16. Dimming Mode Detection and Soft Start
PWM BRIGHTNESS DIMMING
When the CTRL pin is constantly high, the FB voltage is regulated to 200mV typically. However, the CTRL pin
allows a PWM signal to reduce this regulation voltage; therefore, it achieves LED brightness dimming. The
relationship between the duty cycle and FB voltage is given by Equation 2.
VFB = Duty × 200 mV
(2)
Where:
Duty = duty cycle of the PWM signal
200 mV = internal reference voltage
As shown in Figure 17, the IC chops up the internal 200mV reference voltage at the duty cycle of the PWM
signal. The pulse signal is then filtered by an internal low pass filter. The output of the filter is connected to the
error amplifier as the reference voltage for the FB pin regulation. Therefore, although a PWM signal is used for
brightness dimming, only the WLED DC current is modulated, which is often referred as analog dimming. This
eliminates the audible noise which often occurs when the LED current is pulsed in replica of the frequency and
duty cycle of PWM control. Unlike other scheme which filters the PWM signal for analog dimming, TPS61158
regulation voltage is independent of the PWM logic voltage level which often has large variations.
For optimum performance, use the PWM dimming frequency in the range of 20kHz to 100kHz. Since the CTRL
pin is logic only pin, adding an external RC filter applied to the pin does not work.
The minimum dimming duty cycle the IC can support is 1% within the PWM dimming frequency range
20kHz~100kHz.
12
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VBG
200mV
CTRL
Error
Amplifer
EA output
FB
Figure 17. Block Diagram of Programmable FB Voltage Using PWM Signal
DIGITAL 1 WIRE BRIGHTNESS DIMMING
The CTRL pin features a simple digital interface to allow digital brightness control. The digital dimming can save
the processor power and battery life as it does not require a PWM signal all the time, and the processor can
enter idle mode if available.
The TPS61158 adopts the EasyScale™ protocol for the digital dimming, which can program the FB voltage to
any of the 32 steps with single command. The step increment increases with the voltage to produce pseudo
logarithmic curve for the brightness step. See the Table 1 for the FB pin voltage steps. The default step is full
scale when the device is first enabled (VFB = 200mV). The programmed reference voltage is stored in an internal
register. A power reset clears the register value and reset it to default.
EasyScale™: 1 WIRE DIGITAL DIMMING
EasyScale is a simple but flexible one pin interface to configure the FB voltage. The interface is based on a
master-slave structure, where the master is typically a microcontroller or application processor. Figure 18 and
Table 2 give an overview of the protocol. The protocol consists of a device specific address byte and a data byte.
The device specific address byte is fixed to 58 hex. The data byte consists of five bits for information, two
address bits ("00"), and the RFA bit. The RFA bit set to high indicates the Request for Acknowledge condition.
The Acknowledge condition is only applied if the protocol was received correctly. The advantage of EasyScale
compared with other one pin interfaces is that its bit detection is in a large extent independent from the bit
transmission rate. It can automatically detect bit rates between 1.1kBit/sec and up to 100kBit/sec.
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Table 1. Selectable FB Voltage
FB
VOLTAGE
(mV)
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
1
5
0
0
0
0
1
2
8
0
0
0
1
0
3
11
0
0
0
1
1
4
14
0
0
1
0
0
5
17
0
0
1
0
1
6
20
0
0
1
1
0
7
23
0
0
1
1
1
8
26
0
1
0
0
0
9
29
0
1
0
0
1
10
32
0
1
0
1
0
11
35
0
1
0
1
1
12
38
0
1
1
0
0
13
44
0
1
1
0
1
14
50
0
1
1
1
0
15
56
0
1
1
1
1
16
62
1
0
0
0
0
17
68
1
0
0
0
1
18
74
1
0
0
1
0
19
80
1
0
0
1
1
20
86
1
0
1
0
0
21
92
1
0
1
0
1
22
98
1
0
1
1
0
23
104
1
0
1
1
1
24
116
1
1
0
0
0
25
128
1
1
0
0
1
26
140
1
1
0
1
0
27
152
1
1
0
1
1
28
164
1
1
1
0
0
29
176
1
1
1
0
1
30
188
1
1
1
1
0
31
200
1
1
1
1
1
DATA IN
DATABYTE
Device Address
Start
Start DA7 DA6 DA5 DA4 DA3 DA2 DA1
0
1
0
1
1
0
0
DA0 EOS Start RFA
0
A1
A0
D4
D3
D2
D1
D0
EOS
DATA OUT ACK
Figure 18. EasyScale™ Protocol Overview
14
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Table 2. EasyScale™ Bit Description
BYTE
BIT
NUMBER
NAME
7
DA7
0 (MSB device address)
6
DA6
1
5
DA5
0
4
DA4
3
DA3
2
DA2
0
1
DA1
0
0
DA0
0 (LSB device address)
7 (MSB)
RFA
Request for acknowledge. If high, acknowledge is applied by device.
6
A1
0 (Address bit A1)
5
A0
0 (Address bit A0)
4
D4
3
D3
2
D2
Data bit D2
1
D1
Data bit D1
0 (LSB)
D0
Data bit D0
Device
Address
Byte 72 hex
Data byte
TRANSMISSION
DIRECTION
1
IN
1
Data bit D4
IN
ACK
Data bit D3
Acknowledge condition active 0, this condition will only be applied to
case RFA bit is set. Open drain output, line needs to be pulled high
by the host with a pullup resistor. This feature can only be used if the
master has an open drain output stage. In case of a push pull output
stage Acknowledge condition may not be requested!
OUT
t Start
DATA IN
DESCRIPTION
t Start
Address Byte
DATA Byte
Static High
Static High
DA7
0
DA0
0
D0
1
RFA
0
TEOS
TEOS
Figure 19. Easy Scale Timing, without acknowledge (RFA = 0)
t Start
DATA IN
t
Address Byte
Start
DATA Byte
Static High
Static High
DA7
0
DA0
0
TEOS
RFA
1
D0
1
Controller needs to
Pullup Data Line via a
resistor to detect ACKN
DATA OUT
t valACK
ACKN
t ACKN
Acknowledge
true, Data Line
pulled down by
device
Acknowledge
false, no pull
down
Figure 20. Easy Scale Timing, with acknowledge (RFA = 1)
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tLow
Low Bit
(Logic 0)
tHigh
tLOW
tHigh
High Bit
(Logic 1)
Figure 21. EasyScale™— Bit Coding
All bits are transmitted MSB first and LSB last. Figure 19 shows the protocol without acknowledge request (Bit
RFA = 0), Figure 20 with acknowledge (Bit RFA = 1) request. Prior to both bytes, device address byte and data
byte, a start condition must be applied. For this, the CTRL pin must be pulled high for at least tstart (3.5μs) before
the bit transmission starts with the falling edge. If the CTRL pin is already at high level, no start condition is
needed prior to the device address byte. The transmission of each byte is closed with an End of Stream
condition for at least tEOS (3.5μs).
The bit detection is based on a Logic Detection scheme, where the criterion is the relation between tLOW and
tHIGH (refer to Figure 21). It can be simplified to:
• Low Bit (Logic 0): tLOW ≥ 2 x tHIGH
• High Bit (Logic 1): tHIGH ≥ 2 x tLOW
The bit detection starts with a falling edge on the CTRL pin and ends with the next falling edge. Depending on
the relation between tHIGH and tLOW, the logic 0 or 1 is detected.
The acknowledge condition is only applied if:
• Acknowledge is requested by setting RFA bit to 1.
• The transmitted device address matches with the device address of the IC
• Device address byte and data byte are received correctly.
If above conditions are met, after tvalACK (3.5μs) delay from the moment when the last falling edge of the protocol
is detected, an internal ACKN-MOSFET is turned on to pull the CTRL pin low for the time tACKN (900μs
maximum), then the Acknowledge condition is valid. During the tvalACK delay, the master controller keeps the line
low; after the delay, it should release the line by outputting high impedance and then detect the acknowledge
condition. If it reads back a logic 0, it means the IC has received the command correctly. The CTRL pin can be
used again by the master when the acknowledge condition ends after tACKN time.
Note that the acknowledge condition can only be requested in case the master device has an open drain output.
For a push-pull output stage, the use a series resistor in the CTRL line to limit the current to 500μA is
recommended to for such cases as:
• an accidentally requested acknowledge, or
• to protect the internal ACKN-MOSFET.
UNDERVOLTAGE LOCKOUT
An undervoltage lockout prevents operation of the device at input voltages below typical 2.2V. When the input
voltage is below the undervoltage threshold, the device is shutdown and the internal switch FET is turned off. If
the input voltage rises by undervoltage lockout hysteresis, the IC restarts.
OPEN LED PROTECTION
Open LED protection circuitry prevents IC damage as the result of white LED disconnection. The TPS61158
monitors the voltages at the VOUT pin and FB pin. The circuitry turns off the switch FET and shuts down the IC
completely if both of the following two conditions are met: 1) the VOUT voltage reaches OVP threshold (28.2V
typical), 2) FB voltage is lower than half of its regulation voltage. This means the LED string is open or the FB pin
is short to ground. As a result, the output voltage falls to the level of the input supply. The device remains in
shutdown mode until it is enabled by pulling down the CTRL pin logic low for at least 3.5ms and then pulling it
high.
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THERMAL SHUTDOWN
An internal thermal shutdown turns off the device when the typical junction temperature of 160°C is exceeded.
The device is released from shutdown automatically when the junction temperature decreases by 15°C.
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APPLICATION INFORMATION
MAXIMUM OUTPUT CURRENT
The overcurrent limit in a boost converter limits the maximum input current and thus maximum input power for a
given input voltage. Maximum output power is less than maximum input power due to power conversion losses.
Therefore, the current limit setting, input voltage, output voltage and efficiency can all change maximum current
output. The current limit clamps the peak inductor current; therefore, the ripple has to be subtracted to derive
maximum DC current. The ripple current is a function of switching frequency, inductor value and duty cycle. The
following equations take into account of all the above factors for maximum output current calculation.
1
IP =
1
1
L ´ FS ´ (
)
+
VOUT + VF - VIN VIN
(3)
Where
IP = inductor peak to peak ripple
L = inductor value
FS = switching frequency
VOUT = output voltage of the boost converter. It is equal to the sum of VFB and the voltage drop across LEDs.
VF = forward voltage of internal power diode. 0.75V typical
V ´ (I - I / 2) ´ h
I OUT _ max = IN LIM P
VOUT
(4)
Where
IOUT_max = maximum output current of the boost converter
ILIM = over current limit
η = boost efficiency (85%, typical)
To calculate the maximum output current in the worst case, use the minimum input voltage, maximum output
voltage and maximum forward voltage of internal power diode (1V). In order to leave enough design margin,
the minimum current limit value 0.5A, the minimum switching frequency 600kHz, the inductor value with 30% tolerance, and a low power conversion efficiency, such as 80% or lower are recommended for the
calculation. For instance, when minimum VIN is 3.0V, 8 LEDs output equivalent to VOUT is 26V, the inductor
is 22uH, then the maximum output current is 33mA in the worst case.
INDUCTOR SELECTION
The selection of the inductor affects steady state operation as well as transient behavior, loop stability and the
power conversion efficiency. These factors make it the most important component in power regulator design.
There are three important inductor specifications, inductor value, DC resistance and saturation current.
Considering inductor value alone is not enough. The inductor value determines the inductor ripple current.
Choose an inductor that can handle the necessary peak current without saturating, according to half of the peakto-peak ripple current given by Equation 3, plus the inductor DC current given by:
V
´I
Iin _ DC = OUT OUT
VIN ´ h
(5)
Inductor values can have ±20% or even ±30% tolerance with no current bias. When the inductor current
approaches saturation level, its inductance can decrease 20% to 35% from the 0A value depending on how the
inductor vendor defines saturation. When selecting an inductor, please make sure its rated current, especially the
saturation current, is larger than its peak current during the operation. Using an inductor with a smaller
inductance value causes larger current ripple. This reduces the boost converter’s maximum output current,
causes large input voltage ripple and reduces efficiency. Large inductance value provides much more output
current and higher conversion efficiency. For these reasons, a 10μH to 22μH inductor value range is
recommended. A 22μH inductor optimizes the efficiency for most application while maintaining low inductor peak
to peak ripple. Table 3 lists the recommended inductors for TPS61158. TPS61158 has built-in slope
compensation to avoid sub-harmonic oscillation associated with current mode control. If the inductor value is
lower than 10μH, the slope compensation may not be adequate, and the loop can be unstable. Therefore,
customers need to verify the inductor in their application if it is different from the recommended values.
18
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Table 3. Recommended Inductors
PART NUMBER
L (μH)
DCR MAX (mΩ)
SATURATION CURRENT
(A)
Size (L x W x H mm)
VENDOR
LPS3015-103ML
10
440
0.73
3.0 x 3.0 x 1.5
Coilcraft
LPS3015-223ML
22
825
0.5
3.0 x 3.0 x 1.5
Coilcraft
1229AS-H-100M
10
288
0.75
3.5 x 3.7 x 1.2
TOKO
1229AS-H-220M
22
672
0.5
3.5 x 3.7 x 1.2
TOKO
VLS3012ET-100M
10
336
0.64
3.0 x 3.0 x 1.2
TDK
VLS3012ET-220M
22
756
0.44
3.0 x 3.0 x 1.2
TDK
INPUT AND OUTPUT CAPACITOR SELECTION
The output capacitor is mainly selected to meet the requirements for the output ripple and loop stability. This
ripple voltage is related to the capacitor’s capacitance and its equivalent series resistance (ESR). Assuming a
capacitor with zero ESR, the minimum capacitance needed for a given ripple can be calculated by
- VIN ) ´ IOUT
(V
COUT = OUT
VOUT ´ FS ´ Vripple
(6)
Where: Vripple = peak-to-peak output ripple. The additional output ripple component caused by ESR is
calculated using:
Vripple_ESR = IOUT × RESR
(7)
Due to its low ESR, Vripple_ESR can be neglected for ceramic capacitors, but must be considered if tantalum or
electrolytic capacitors are used.
Care must be taken when evaluating a ceramic capacitor’s derating under DC bias, aging and AC signal. The DC
bias can significantly reduce capacitance. Ceramic capacitors can lose as much as 50% of its capacitance at its
rated voltage. Therefore, leave the margin on the voltage rating to ensure adequate capacitance at the required
output voltage.
The capacitor in the range of 1μF to 10μF is recommended for input side. The output requires a capacitor in the
range of 0.47μF to 2.2μF. The output capacitor affects the loop stability of the boost regulator. If the output
capacitor is below the range, the boost regulator can potentially become unstable.
The popular vendors for high value ceramic capacitors are:
TDK (http://www.component.tdk.com/components.php)
Murata (http://www.murata.com/cap/index.html)
LAYOUT CONSIDERATION
As for all switching power supplies, especially those high frequency and high current ones, layout is an important
design step. If layout is not carefully done, the regulator could suffer from instability as well as noise problems.
Therefore, use wide and short traces for high current paths. The input capacitor Cin needs to be close to the VIN
pin and GND pin in order to reduce the input ripple seen by the IC. If possible, choose higher capacitance value
for it. If the ripple seen at VIN pin is so large that it affects the boost loop stability or internal circuits operation,
R1 and C1 is recommended to compose a filter to decouple the noise (refer to Figure 23). The SW pin carries
high current with fast rising and falling edges. Therefore, the connection between the SW pin to the inductor
should be kept as short and wide as possible. The output capacitor Cout should be put close to VOUT pin. It is
also beneficial to have the ground of Cout close to the GND pin since there is large ground return current flowing
between them. FB resistor should be put close to FB pin. When laying out signal grounds, it is recommended to
use short traces separated from power ground traces, and connect them together at a single point close to the
GND pin.
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ADDITIONAL APPLICATION CIRCUITS
L
22µH
2.7V ~ 5.5V
Up to 8 LEDs
VBAT
Cin
2.2µF
Cout
1µF
TPS61158
VIN
PWM or 1-wire
dimming control
LX
CTRL
VOUT
GND
FB
RFB
10
Figure 22. TPS61158 to Drive up to 8 LEDs
L
22µH
2.7V ~ 5.5V
Up to 8 LEDs
VBAT
R1
10
Cin
2.2µF
VIN
C1
1µF
PWM or 1-wire
dimming control
Cout
1µF
TPS61158
LX
CTRL
VOUT
GND
FB
RFB
10
Figure 23. TPS61158 to Drive up to 8 LEDs with RC Filter at VIN Pin
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PACKAGE OPTION ADDENDUM
www.ti.com
29-May-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
TPS61158DRVR
ACTIVE
SON
DRV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
SIW
TPS61158DRVT
PREVIEW
SON
DRV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
SIW
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
29-May-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPS61158DRVR
Package Package Pins
Type Drawing
SON
DRV
6
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
3000
180.0
8.4
Pack Materials-Page 1
2.3
B0
(mm)
K0
(mm)
P1
(mm)
2.3
1.15
4.0
W
Pin1
(mm) Quadrant
8.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-May-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS61158DRVR
SON
DRV
6
3000
210.0
185.0
35.0
Pack Materials-Page 2
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