Inchange Semiconductor Product Specification 2N6931 2N6932 Silicon NPN Power Transistors DESCRIPTION ・With TO-3PN package ・High voltage ,high speed APPLICATIONS ・Off-line power supplies ・High-voltage inverters ・Switching regulators PINNING PIN DESCRIPTION 1 Base 2 Collector;connected to mounting base 3 Emitter Fig.1 simplified outline (TO-3PN) and symbol 导体 半 电 Absolute maximum ratings (Ta=25℃) SYMBOL 固 VCBO PARAMETER CONDITIONS IC M E ES ANG 2N6931 VEBO INCH Collector-emitter voltage Emitter-base voltage UNIT 450 Open emitter 2N6932 VCEO C U D ON 2N6931 Collector-base voltage TOR VALUE 300 Open base 2N6932 Open collector V 650 V 400 8 V IC Collector current 10 A ICM Collector current-peak 15 A IB Base current 5 A IBM Base current-peak 7 A IE Emitter current 15 A IEM Emitter current-peak 22 A PC Collector power dissipation 150 W Tj Junction temperature 150 ℃ Tstg Storage temperature -65~150 ℃ TC=25℃ Inchange Semiconductor Product Specification 2N6931 2N6932 Silicon NPN Power Transistors CHARACTERISTICS Tj=25℃ unless otherwise specified SYMBOL VCEO(SUS) PARAMETER Collector-emitter sustaining voltage CONDITIONS 2N6931 TYP. MAX UNIT 300 IC=0.2A ;L=25mH 2N6932 V(BR)EBO MIN V 400 Emitter-base breakdown voltage IE=50mA ;IC=0 VCEsat Collector-emitter saturation voltage IC=10A ;IB=2A TC=100℃ 1.0 2.0 V VBEsat Base-emitter saturation voltage IC=10A ;IB=2A TC=100℃ 1.5 1.5 V 2N6931 VCE=450V; VBE=-1.5V TC=100℃ 0.1 1.0 2N6932 VCE=650V; VBE=-1.5V TC=100℃ 0.1 1.0 ICEV Collector cut-off current 8 IEBO Emitter cut-off current VEB=8V; IC=0 hFE DC current gain IC=10A ; VCE=3V Collector output capacitance f=1MHz;VCB=10V COB 体 半导 固电 Delay time tr Rise time tstg tf R O T UC 35 80 300 pF 0.1 μs 0.7 μs 2.5 μs 0.5 μs IC=10A; IB1=-IB2=2A VCC=300V, RC=30Ω VBB=-5V;tp=30μs Storage time mA 8 D N O IC N A H INC td mA 2 M E S GE Switching times resistive load V Fall time THERMAL CHARACTERISTICS SYMBOL Rth j-c PARAMETER Thermal resistance junction to case 2 VALUE UNIT 0.83 ℃/W Inchange Semiconductor Product Specification 2N6931 2N6932 Silicon NPN Power Transistors PACKAGE OUTLINE 导体 半 电 固 R O T UC D N O IC M E S GE N A H INC Fig.2 outline dimensions (unindicated tolerance:±0.10 mm) 3