PI74AVC+16820 2.5V 10-Bit Flip-Flop with Dual and 3-State Outputs Features Description • PI74AVC+16820 is designed for low-voltage operation, VCC = 1.65V to 3.6V • True ±24mA Balanced Drive @ 3.3V • IOFF supports Partial power-down operation • 3.6V I/O Tolerant inputs and outputs • All outputs contain a patented DDC (Dynamic DriveControl) circuit that reduces noise without degrading propagation delay. • Industrial operation: –40°C to +85°C • Packaging (Pb-free & Green available): – 56-pin 240-mil wide plastic TSSOP (A) Pericom Semiconductor’s PI74AVC+16820, a 10-bit flip-flop designed for 1.65V to 3.6V VCC operation. It is designed with edge-triggered D-type flip- flops. On the positive transition of clock (CLK) input. The device provides true data at the Q outputs. A buffered output-enable (OE) input can be used to place the ten outputs in either a normal logic state (HIGH or LOW level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capacity to drive bus lines without the need for interface or pullup components. OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power-up or powerdown, OE should be tied to VCC through a pullup resistor whose minimum value is determined by the current sinking capability of the driver. Pin Configuration ��� ��� ��� ��� ��� ��� ��� ��� ��� ��� ��� ��� ��� ��� ��� ��� ��� ��� ��� ��� ��� ��� ��� ��� ��� ���� ���� ��� 06-0172 � � � � � � � � � �� �� �� �� �� �� �� �� �� �� �� �� �� �� �� �� �� �� �� �� �� �� �� �� �� �� �� �� �� �� �� �� �� �� �� �� �� �� �� �� �� �� �� �� �� �� �� ��� �� �� ��� �� �� ��� �� �� �� ��� �� �� �� �� �� �� ��� �� �� �� ��� �� �� ��� ��� �� �� Block Diagram 1OE 2OE CLK D1 1 28 2 56 55 C1 1D 3 1Q1 1Q2 TO 9 OTHER CHANNELS 1 PS8446E 06/01/06 PI74AVC+16820 2.5V 10-Bit Flip-Flop w/Dual and 3-State Outputs Maximum Ratings Truth Table each Flip-Flop(1) (Above which the useful life may be impaired. For user guidelines, not tested.) Inputs Supply voltage range, VCC ...................................... –0.5V to +4.6V Input voltage range, VI ............................................. –0.5V to +4.6V Voltage range applied to any output in the high-impedance or power-off state, VO(1) ........ –0.5V to +4.6V Voltage range applied to any output in the high or low state, VO(1,2) ........................... –0.5V to VCC +0.5V Input clamp current, IIK (VI <0) ..................................... –50mA Output clamp current, IOK (VO <0)................................ –50mA Continuous output current, IO ........................................ ±50mA Continuous current through each VCC or GND ........... ±100mA Package thermal impedance, θJA(3) .............................. 64°C/W Storage Temperature range, Tstg ....................... –65°C to 150°C 2. 3. OEn CLK Dn Qn L ↑ H H L ↑ L L L L X Qo H X X Z Notes: 1. H = High Signal Level, L = Low Signal Level, X = Irrelevant; Z = High Impedance, Qo = Output Level before the indicated steady-state conditions were established. Pin Description Notes: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 1. Outputs Pin Name Description OE Output Enable Input (Active LOW) CLK Clock Input (Active HIGH) Qn 3-State Outputs Dn Data Inputs GND Ground VCC Power Input & output negative-voltage ratings may be exceeded if the input and output curent rating are observed. Output positive-voltage rating may be exceeded up to 4.6V maximum if the output current rating is observed. The package thermal impedance is calculated in accordance with JESD 51. 06-0172 2 PS8446E 06/01/06 PI74AVC+16820 2.5V 10-Bit Flip-Flop w/Dual and 3-State Outputs Recommended Operating Conditions(1) Parameters VCC Description Supply Voltage Test Conditions Min. Max. Operating 1.65 3.6 Data retention only 1.2 VCC = 1.2V VIH High-level Input Voltage VCC = 1.65V to 1.95V VCC = 2.3V to 2.7V VCC = 3V to 3.6V VCC 0.65 x VCC 1.7 2 VCC = 1.2V VIL Low-level Input Voltage VI Input Voltage VO Output Voltage IOH IOL High-level output current Low-level output current ∆T∆V Input transition rise or fall rate TA Operating free-air temperature Units GND VCC = 1.65V to 1.95V V 0.35 x VCC VCC = 2.3V to 2.7V 0.7 VCC = 3V to 3.6V 0.8 0 3.6 Active State 0 VCC 3-State 0 3.6 VCC = 1.65V to 1.95V –6 VCC = 2.3V to 2.7V – 12 VCC = 3V to 3.6V – 24 mA VCC = 1.65V to 1.95V 6 VCC = 2.3V to 2.7V 12 VCC = 3V to 3.6V 24 VCC = 1.65V to 3.6V 5 ns/V 85 C° –40 Notes: 1. All unused inputs must be held at VCC or GND to ensure proper device operation. 06-0172 3 PS8446E 06/01/06 PI74AVC+16820 2.5V 10-Bit Flip-Flop w/Dual and 3-State Outputs DC Electrical Characteristics (Over the Operating Range, TA = –40°C +85°C) Test Conditions(1) Parameters VCC Min. 1.65V to 3.6V VCC –0.2V IOH = –6mA, VIH = 1.07V 1.65V 1.2 IOH = –12mA, VIH = 1.7V 2.3V 1.75 3V 2 IOH = –100µA VOH IOH = –24mA, VIH = 2V IOL = 100µA VOL Typ. Max. V 1.65V to 3.6V 0.2 IOL = 6mA, VIH = 0.57V 1.65V 0.45 IOL = 12mA, VIH = 0.7V 2.3V 0.55 IOL = 24mA, VIH = 0.8V 3V 0.8 II VI = VCC or GND 3.6V ±2.5 IOFF 0 ±10 IOZ VI or VO = 3.6V VI = VCC or GND 3.6V ±10 ICC VO = VCC or GND, VO = 0 3.6V 40 2.5V 4 3.3V 4 2.5V 6 3.3V 6 2.5V 8 3.3V 8 Control Inputs CI VI = VCC or GND Data Inputs CO Outputs VO = VCC or GND Units mA pF Notes: 1. Typical values are measured at TA = 25°C. 06-0172 4 PS8446E 06/01/06 PI74AVC+16820 2.5V 10-Bit Flip-Flop w/Dual and 3-State Outputs Timing Requirements (Over recommended operating free-air temperature range, unless otherwise noted, see Figures 1 thru 4) VCC = 1.2V Min. VCC = 1.5V ± 0.1V Max. Min. VCC = 1.8V ± 0.15V Max. Min. VCC = 2.5V ± 0.2V Max. fCLOCK Clock Frequency Min. Max. 150 tW Pulse duration, CLK high or low VCC = 3.3V ± 0.3V Min. 180 180 6 3 3 tSU Setup time, data before CLK 5.7 3.5 2.5 tH Hold time, data after CLK 1.2 1 1 Units Max. MHz ns Switching Characteristics (Over recommended operating free-air temperature range, unless otherwise noted, see Figures 1 thru 4) From (Input) Parameters To (Output) VCC = 1.2V Min. Max. VCC = 1.5V ± 0.1V VCC = 1.8V ± 0.15V VCC = 2.5V ± 0.2V VCC = 3.3V ± 0.3V Min. Min. Min. Min. Max. fMAX Max. 150 Max. 180 Units Max. 180 MHz tPD CLK Q 4 3.2 2.7 tEN OE Q 5.8 5.1 4.5 tDIS OE Q 5 4.6 4.2 VCC = 1.8V ± 0.15V VCC = 2.5V ± 0.2V VCC = 3.3V ± 0.3V Typical Typical Typical 40 48 55 23 27 32 ns Operating Characteristics, TA= 25°C Parameters Cpd Power Dissipation Capacitance 06-0172 Test Conditions Outputs Enabled Outputs Disabled CL = 0pF, f = 10 MHz, 2 outputs switching 5 Units pF PS8446E 06/01/06 PI74AVC+16820 2.5V 10-Bit Flip-Flop w/Dual and 3-State Outputs PARAMETER MEASUREMENT INFORMATION VCC = 1.2V and 1.5V ± 0.1V S1 2-ohm From Output Under Test CL = 15pF (See Note 1) 2xVCC Open GND 2-ohm Test S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 x VCC GND Load Circuit VCC Timing Input VCC/2 tW 0V tsu VCC th VCC/2 0V VCC/2 0V Voltage Waveforms Pulse Duration Voltage Waveforms Setup and Hold Times Output Control (Low Level Enabling) VCC/2 0V tPHL VCC/2 VCC/2 tPZL Output Waveform 2 S1 at GND (see Note 2) VOH VCC/2 VCC Output Waveform 1 S1 at 2 x VCC (see Note 2) t PZH VCC VCC/2 tPLH Output VCC/2 VCC Data Input Input VCC/2 Input VOL Voltage Waveforms Propagation Delay Times VCC/2 tPLZ 0V VCC VCC/2 VOL +0.1V tPHZ VCC/2 VOH –0.1V VOL VOH 0V Voltage Waveforms Enable and Disable Times Figure 1. Load Circuit and Voltage Waveforms Notes: 1. CL includes probe and jig capacitance. 2. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. • All input impulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tR ≤ 2.0ns, tF ≤ 2.0ns. • The outputs are measured one at a time with one transition per measurement. • tPLZ and tPHZ are the same as tdis • tPZL and tPZH are the same as ten • tPLH and tPHL are the same as tpd 06-0172 6 PS8446E 06/01/06 PI74AVC+16820 2.5V 10-Bit Flip-Flop w/Dual and 3-State Outputs PARAMETER MEASUREMENT INFORMATION VCC = 1.8V ±0.15V S1 1K-ohm From Output Under Test CL = 30pF (See Note 1) 2xVCC Open GND 1K-ohm Test S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 x VCC GND Load Circuit VCC Timing Input VCC/2 tW 0V tsu VCC th VCC Data Input VCC/2 0V 0V VCC/2 Voltage Waveforms Pulse Duration Output Control (Low Level Enabling) VCC VCC/2 VOH VCC/2 VCC/2 VCC VCC/2 tPZL Output Waveform 1 S1 at 2 x VCC (see Note 2) t PZH 0V tPHL tPLH Output VCC/2 VCC/2 Voltage Waveforms Setup and Hold Times Input VCC/2 Input Output Waveform 2 S1 at GND (see Note 2) VOL Voltage Waveforms Propagation Delay Times VCC/2 tPLZ 0V VCC VCC/2 VOL + 0.15V tPHZ VCC/2 VOL V VOH – 0.15V OH 0V Voltage Waveforms Enable and Disable Times Figure 2. Load Circuit and Voltage Waveforms Notes: 1. CL includes probe and jig capacitance. 2. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. • All input impulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tR ≤ 2.0ns, tF ≤ 2.0ns. • The outputs are measured one at a time with one transition per measurement. • tPLZ and tPHZ are the same as tdis • tPZL and tPZH are the same as ten • tPLH and tPHL are the same as tpd 06-0172 7 PS8446E 06/01/06 PI74AVC+16820 2.5V 10-Bit Flip-Flop w/Dual and 3-State Outputs PARAMETER MEASUREMENT INFORMATION VCC = 2.5V ±0.2V 500-ohm From Output Under Test CL = 30pF (See Note 1) S1 2xVCC Open GND 500-ohm Test S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 x VCC GND Load Circuit VCC Timing Input VCC/2 tW 0V tsu VCC th VCC Data Input VCC/2 0V 0V VCC/2 Voltage Waveforms Pulse Duration Output Control (Low Level Enabling) VCC VCC/2 VOH VCC/2 VCC/2 VCC VCC/2 tPZL Output Waveform 1 S1 at 2 x VCC (see Note 2) t PZH 0V tPHL tPLH Output VCC/2 VCC/2 Voltage Waveforms Setup and Hold Times Input VCC/2 Input Output Waveform 2 S1 at GND (see Note 2) VOL Voltage Waveforms Propagation Delay Times VCC/2 tPLZ 0V VCC VCC/2 VOL + 0.15V tPHZ VCC/2 VOL V VOH – 0.15V OH 0V Voltage Waveforms Enable and Disable Times Figure 3. Load Circuit and Voltage Waveforms Notes: 1. CL includes probe and jig capacitance. 2. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. • All input impulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tR ≤ 2.0ns, tF ≤ 2.0ns. • The outputs are measured one at a time with one transition per measurement. • tPLZ and tPHZ are the same as tdis • tPZL and tPZH are the same as ten • tPLH and tPHL are the same as tpd 06-0172 8 PS8446E 06/01/06 PI74AVC+16820 2.5V 10-Bit Flip-Flop w/Dual and 3-State Outputs PARAMETER MEASUREMENT INFORMATION VCC = 3.3V ±0.3V 500-ohm From Output Under Test CL = 30pF (See Note 1) S1 2xVCC Open GND 500-ohm Test S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 x VCC GND Load Circuit VCC Timing Input VCC/2 tW 0V tsu VCC th VCC Data Input VCC/2 0V 0V VCC/2 Voltage Waveforms Pulse Duration Output Control (Low Level Enabling) VCC VCC/2 VOH VCC/2 VCC/2 VCC VCC/2 tPZL Output Waveform 1 S1 at 2 x VCC (see Note 2) t PZH 0V tPHL tPLH Output VCC/2 VCC/2 Voltage Waveforms Setup and Hold Times Input VCC/2 Input Output Waveform 2 S1 at GND (see Note 2) VOL Voltage Waveforms Propagation Delay Times VCC/2 tPLZ 0V VCC VCC/2 VOL + 0.3V tPHZ VCC/2 VOH – 0.3V VOL VOH 0V Voltage Waveforms Enable and Disable Times Figure 4. Load Circuit and Voltage Waveforms Notes: 1. CL includes probe and jig capacitance. 2. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. • All input impulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tR ≤ 2.0ns, tF ≤ 2.0ns. • The outputs are measured one at a time with one transition per measurement. • tPLZ and tPHZ are the same as tdis • tPZL and tPZH are the same as ten • tPLH and tPHL are the same as tpd 06-0172 9 PS8446E 06/01/06 PI74AVC+16820 2.5V 10-Bit Flip-Flop w/Dual and 3-State Outputs Packaging Mechanical: 56-pin TSSOP (A) �� ���� ���� � ���� ���� ��� ��� ���� ���� ���� ���� ���� ������������� ���� ���� ������ ���� ����� ���� ���� ���� ���� ���� ���� ���� ������������������� ���� �������������� ���� ���� ���� ���� ���� ���� ���� ���� ���� ��� ���� Ordering Information Ordering Code Package Code Package Description PI74AVC+16820A A 56-pin, 240-mil wide plastic TSSOP PI74AVC+16820AE A Pb-free & Green, 56-pin, 240-mil wide plastic TSSOP Notes: • Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ • E = Pb-free & Green • Adding an X suffix = Tape/Reel Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com 06-0172 10 PS8446E 06/01/06