SCAS011B − D2957, JULY 1987 − REVISED APRIL 1993
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54ACT11241 . . . JT PACKAGE
74ACT11241 . . . DB, DW OR NT PACKAGE
3-State Outputs Drive Bus Lines or Buffer
Memory Address Registers
Inputs Are TTL-Voltage Compatible
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
EPICt (Enhanced-Performance Implanted
CMOS) 1-mm Process
500-mA Typical Latch-Up Immunity at 125°C
Package Options Include Plastic SmallOutline Packages, Plastic Shrink
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and Ceramic
300-mil DIPs
(TOP VIEW)
1Y1
1Y2
1Y3
1Y4
GND
GND
GND
GND
2Y1
2Y2
2Y3
2Y4
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
1G
1A1
1A2
1A3
1A4
VCC
VCC
2A1
2A2
2A3
2A4
2G
54ACT11241 . . . FK PACKAGE
description
(TOP VIEW)
1A3
1A4
VCC
NC
VCC
2A1
2A2
These octal buffers or line drivers are designed
specifically to improve both the performance and
density of three-state memory address drivers,
clock drivers, and bus-oriented receivers and
transmitters. Taken together with the ACT11240
and ACT11244, these devices provide the choice
of selected combinations of inverting and
noninverting outputs, symmetrical G (active-low
output control) inputs, and complementary G and
G inputs. These devices feature high fan-out.
5
1A2
1A1
1G
NC
1Y1
1Y2
1Y3
3 2 1 28 27 26
25
6
24
7
23
8
22
9
21
10
20
11
19
12 13 14 15 16 17 18
2A3
2A4
2G
NC
2Y4
2Y3
2Y2
1Y4
GND
GND
NC
GND
GND
2Y1
The 54ACT11241 is characterized for operation
over the full military temperature range of − 55°C
to 125°C. The 74ACT11241 is characterized for
operation from − 40°C to 85°C.
4
NC − No internal connection
FUNCTION TABLE
OUTPUT
CONTROL
1G
DATA
INPUT
1A
OUTPUT
1Y
OUTPUT
CONTROL
2G
DATA
INPUT
2A
OUTPUT
2Y
H
X
Z
L
X
Z
L
L
L
H
L
L
L
H
H
H
H
H
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1993, Texas Instruments Incorporated
!"#$%&" ' ()##*& %' "! +),-(%&" .%&*/
#".)(&' ("!"#$ &" '+*(!(%&"' +*# &0* &*#$' "! *1%' '&#)$*&'
'&%.%#. 2%##%&3/ #".)(&" +#"(*''4 ."*' "& *(*''%#-3 (-).*
&*'&4 "! %-- +%#%$*&*#'/
•
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POST OFFICE BOX 1443 HOUSTON, TEXAS 77001
•
2−1
SCAS011B − D2957, JULY 1987 − REVISED APRIL 1993
logic symbol†
1G
1A1
1A2
1A3
1A4
2G
2A1
2A2
2A3
2A4
24
logic diagram (positive logic)
EN
1G
23
1
22
2
21
3
20
4
13
1Y1
1A1
24
23
1
22
2
21
3
20
4
1Y1
1Y2
1Y3
1A2
1Y2
1Y4
1A3
1Y3
EN
17
9
16
10
15
11
14
12
1A4
2Y1
1Y4
13
2Y2
2G
2Y3
2Y4
2A1
† This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
2A2
2A3
2A4
17
9
2Y1
16
10 2Y2
15
11
14
12
2Y3
2Y4
Pin numbers shown are for the DW, JT, and NT packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 200 mA
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
}Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at the se or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2−2
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•
SCAS011B − D2957, JULY 1987 − REVISED APRIL 1993
recommended operating conditions
54ACT11241
MIN
MAX
MIN
MAX
4.5
5.5
4.5
5.5
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
Input voltage
0
VO
IOH
Output voltage
0
High-level output current
IOL
Dt /Dv
Low-level output current
TA
Operating free-air temperature
High-level input voltage
74ACT11241
2
2
0.8
Input transition rise or fall rate
UNIT
V
V
0.8
V
VCC
VCC
V
−24
−24
mA
24
24
mA
VCC
VCC
0
0
V
0
10
0
10
ns/ V
−55
125
− 40
85
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = − 50 mA
A
VOH
IOH = − 24 mA
IOH = − 50 mA{
IOH = − 75 mA{
54ACT11241
4.5 V
4.4
4.4
4.4
5.5 V
5.4
5.4
5.4
4.5 V
3.94
3.7
3.8
5.5 V
4.94
4.7
4.8
MIN
MAX
MIN
MAX
UNIT
V
3.85
5.5 V
3.85
4.5 V
IOL = 24 mA
74ACT11241
MIN
5.5 V
IOL = 50 mA
A
VOL
TA = 25°C
TYP
MAX
VCC
0.1
0.1
0.1
5.5 V
0.1
0.1
0.1
4.5 V
0.36
0.5
0.44
5.5 V
0.36
0.5
0.44
V
IOL = 50 mA{
IOL = 75 mA{
5.5 V
IOZ
II
VO = VCC or GND
VI = VCC or GND
5.5 V
± 0.5
± 10
±5
mA
5.5 V
± 0.1
±1
±1
mA
ICC
VI = VCC or GND,
5.5 V
8
160
80
mA
DICC}
One input at 3.4 V,
Other inputs at GND or VCC
5.5 V
0.9
1
1
mA
Ci
VI = VCC or GND
VO = VCC or GND
1.65
5.5 V
IO = 0
1.65
5V
4
Co
5V
10
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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•
pF
pF
2−3
SCAS011B − D2957, JULY 1987 − REVISED APRIL 1993
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A
Y
tPZH
tPZL
G or G
Y
tPHZ
tPLZ
G or G
Y
MIN
TA = 25°C
TYP
MAX
54ACT11241
74ACT11241
MIN
MAX
MIN
MAX
1.5
6.6
9
1.5
10.7
1.5
10
1.5
6.3
8.5
1.5
9.5
1.5
9.1
1.5
7.5
11.3
1.5
13
1.5
12.3
1.5
7.4
10.5
1.5
11.9
1.5
11.3
1.5
7.6
10.6
1.5
11.4
1.5
11
1.5
8.2
11.2
1.5
12
1.5
11.7
UNIT
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
TEST CONDITIONS
TYP
Outputs enabled
Cpd
Power dissipation capacitance per buffer
UNIT
27
CL = 50 pF,
Outputs disabled
f = 1 MHz
9
pF
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
Output
Control
(low-level
enabling)
3V
1.5 V
0V
tPHL
Output
Waveform 2
S1 at GND
(see Note C)
VOH
50% VCC
3V
50% VCC
VOL
1.5 V
1.5 V
0V
tPZL
tPLZ
Output
Waveform 1
S1 at 2 × VCC
(see Note C)
1.5 V
tPLH
Output
S1
Open
2 × VCC
GND
500 Ω
LOAD CIRCUIT
Input
(see Note B)
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
50% VCC
20% VCC
VOL
tPHZ
tPZH
VOLTAGE WAVEFORMS
[ VCC
50% VCC
80% VCC
VOH
[0V
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
2−4
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