TPS51363 www.ti.com SLUSBB5A – FEBRUARY 2013 – REVISED JUNE 2013 22-V Input, 8-A or 10-A Converter With Integrated FET Check for Samples: TPS51363 FEATURES DESCRIPTION • • • The TPS51363 is a high-voltage input, synchronous converter with integrated FET, based on D-CAP2™ control topology, which enables fast transient response and supports both POSCAP and all MLCC output capacitors. TI proprietary FET technology combined with TI leading-edge package technology provides the highest density solution for single-output power rail such as VCCIO and VDDQ for DDR notebook memory, or any point-of-load (POL) in wide application. 1 2 • • • • • • • • • • Input Voltage Range: 3 V to 22 V Output Voltage Range: 0.6 V to 2 V 8-A or 10-A Integrated FET Converter (see Table 1) Fewest External Components Soft-Start Time Programmable by External Capacitor Switching Frequency: 400 kHz and 800 kHz D-CAP2™ Architecture to Enable POSCAP and All MLCC Output Capacitor Usage Integrated and Temperature Compensated Low-Side On-Resistance Sensing for Accurate OCL Protection Powergood Output OCL, OVP, UVP and UVLO Protections Thermal Shutdown (non-latch) Output Discharge Function Integrated Boost MOSFET Switch 28-Pin, 3.5-mm × 4.5-mm, RVE, QFN Package with 0.4-mm Pitch and 1-mm Height The feature set includes switching frequency of 400 kHz and 800 kHz. Programmable soft-start time with an external capacitor. auto skip, pre-bias startup, integrated bootstrap switch, power good, enable and a full suite of fault protection schemes, including OCL, UVP, OVP, 5-V UVLO and thermal shutdown. It is packaged in 3.5 mm × 4.5 mm, 0.4-mm pitch, 28pin QFN (RVE), and specified from -10°C to 85°C. Table 1. Current Ratings FREQUENCY SETTING MAX IDC 800 kHz 8A 400 kHz 10 A APPLICATIONS • • Notebook Computers (VCCIO) Memory Rails (DDR VDDQ) SIMPLIFIED APPLICATION VSNS GSNS 23 22 21 GSNS VSNS SLEW 20 19 TRIP GND 18 17 16 15 V5 VIN VIN VIN 24 REFIN2 PGND 14 PGND 13 25 REFIN 26 VREF PGND 12 TPS51363 PGND 11 27 NU PGND 10 28 EN PGOOD 1 EN PGOOD VIN 7.4 V to 20 V NU MODE NC 2 3 4 BST SW SW SW SW 5 6 7 8 9 VOUT 1.05 V UDG-12205 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. D-CAP2 is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013, Texas Instruments Incorporated TPS51363 SLUSBB5A – FEBRUARY 2013 – REVISED JUNE 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) (1) (2) ORDERABLE DEVICE NUMBER TA PACKAGE –10°C to 85°C Plastic Quad Flat Pack (QFN) TPS51363RVET TPS51363RVER (2) PINS 28 TRANSPORT MEDIA MINIMUM ORDER QUANTITY Small tape-and-reel 250 Large tape-and-reel 3000 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the TI website at www.ti.com. Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VALUE VIN UNIT MIN MAX –0.3 30 36 BST transient <10 ns 38 w/r/t SW Input voltage range (2) 6 SW 30 EN, TRIP, NU, MODE, V5 -0.3 SLEW, VSNS, REFIN, REFIN2 Output voltage range (2) –0.3 3.6 GSNS –0.35 0.35 PGND -0.3 0.3 PGOOD –0.3 6 VREF –0.3 3.6 –5 36 NC Electrostatic discharge Human body model (HBM) QSS 009-105 (JESD22-A114A) 2000 Charged device model (CDM) QSS 009-147 (JESD22-C101B.01) –10 150 Storage temperature range, Tstg –55 150 (2) V V 500 Junction temperature range, TJ (1) V 6 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the network ground terminal unless otherwise noted. . 2 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS51363 TPS51363 www.ti.com SLUSBB5A – FEBRUARY 2013 – REVISED JUNE 2013 . THERMAL INFORMATION TPS51363 THERMAL METRIC (1) θJA Junction-to-ambient thermal resistance 40.2 θJCtop Junction-to-case (top) thermal resistance 22.8 θJB Junction-to-board thermal resistance 20.1 ψJT Junction-to-top characterization parameter 1.6 ψJB Junction-to-board characterization parameter 19.4 θJCbot Junction-to-case (bottom) thermal resistance 2.2 (1) UNITS QFN (RVE) (28 PINS) °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) Supply voltage range VIN V5 BST SW Input voltage range Output voltage range MIN MAX 3 22 4.6 5.5 –0.1 33.5 –3 27 EN, TRIP, NU, MODE –0.1 5.5 SLEW, VSNS, REFIN, REFIN2 –0.1 3.5 GSNS –0.1 0.3 PGND –0.1 0.1 PGOOD –0.1 5.5 VREF, SLEW –0.1 3.5 –10 85 Operating free-air temperature, TA UNIT Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS51363 V °C 3 TPS51363 SLUSBB5A – FEBRUARY 2013 – REVISED JUNE 2013 www.ti.com ELECTRICAL CHARACTERISTICS over operating free-air temperature range, VIN = 12 V, VV5 = 5 V, MODE = GND, VEN = 3.3 V (unless otherwise noted) PARAMETER TEST CONDITION MIN TYP MAX UNIT SUPPLY CURRENT IV5 V5 supply current TA=25°C, No load, VEN = 5 V 560 μA IV5SDN V5 shutdown current TA=25°C, No load, VEN = 0 V 1 μA VREF OUTPUT VVREF Reference voltage IVREF(OCL) Current limit IVREF = 30 µA, w.r.t. GSNS 0 µA ≤ IVREF ≤ 300 µA, -10°C ≤ TA ≤ 85°C (VVREF–VGSNS) = 1.7 V 2 -1.0% 0.4 V 1.0% 1 mA VOLTAGE AMPLIFIER IVSNS VSNS input current VVSNS = 1 V IVSNS(DIS) VSNS discharge current VEN = 0 V, VVSNS = 0.5 V -1 1 μA 12 mA SWITCH TIMING tOFF(min) Minimum off-time 320 ns tDEAD1 Deadtime1 (1) SW rising to falling 35 ns tDEAD2 Deadtime2 (1) SW falling to rising 10 ns INTERNAL BOOT STRAP SW VFBST Forward foltage VV5 - BST, TA = 25°C, IF = 10 mA IBST BST leakage current TA = 25°C, VBST = 14 V, VSW = 7 V 0.1 0.2 V 0.01 1.5 μA MOSFET ON-RESISTANCE RDS(on)H High-side on-resistance TA = 25°C, VV5 = 5 V 20 mΩ RDS(on)L Low-side on-resistance TA = 25°C, VV5 = 5 V 10 mΩ LOGIC THRESHOLD VMODE(TH) MODE threshold voltage VLL EN low-level voltage VLH EN high-level voltage VL(HYST) EN hysteresis voltage VL(LK) EN input leakage current MODE = Float 2.5 V 0.35 0.9 V 0.25 -1 V 0 V 1 μA SOFT-START ISS Soft-Start current Soft-start current source μA 10 PGOOD COMPARATOR VPGTH PGOOD threshold PGOOD in from lower (startup) IPG PGOOD sink current VPGOOD = 0.5V tPG(CMPSS) PGOOD start-up delay PGOOD comparator startup delay IPG(LK) PGOOD leakage current (1) 4 92% 6 mA 1.5 -1 0 ms 1 μA Ensured by design. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS51363 TPS51363 www.ti.com SLUSBB5A – FEBRUARY 2013 – REVISED JUNE 2013 ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range, VIN = 12 V, VV5 = 5 V, MODE = GND, VEN = 3.3 V (unless otherwise noted) PARAMETER TEST CONDITION MIN TYP MAX UNIT OVERCURRENT LIMIT LEVEL IOCL Current limit threshold VZC (2) Zero cross detection offset VTRIP = 0 V, valley current set point, TA=25°C 7 8 9 VTRIP = 5 V, valley current set point, TA=25°C 10.5 12 13.5 0 A mV PROTECTIONS VPOR V5 POR threshold voltage (2) Reset OVP fault 1.7 V VPORHYS V5 POR threshold voltage hysteresis (2) Reset OVP fault hysteresis 85 mV VUVLO V5 UVLO threshold voltage VOVP OVP threshold voltage OVP detect voltage tOVPDLY OVP propagation delay With 100 mV overdrive VOOB OOB threshold voltage VUVP UVP threshold voltage tUVPDLY UVP delay Wake-up 4.3 4.4 4.6 Shutdown 3.8 4 4.2 118% 120% 123% 430 105.5% UVP detect voltage 63% V ns 109.5% 66% 69% 1 ms THERMAL SHUTDOWN TSDN (2) Thermal shutdown threshold (2) Shutdown temperature Hysteresis 140 10 °C Ensured by design. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS51363 5 TPS51363 SLUSBB5A – FEBRUARY 2013 – REVISED JUNE 2013 www.ti.com DEVICE INFORMATION VIN VIN 16 15 14 VIN 17 13 V5 18 12 GND 19 NU 11 TRIP 20 PGND PGND EN 10 SLEW 21 26 VSNS VREF 27 22 25 PGND 28 GSNS REFIN PGND 24 PGND 1 2 3 4 5 6 7 8 9 NU MODE NC BST SW SW SW SW Thermal Pad PGOOD REFIN2 6 23 RVE PACKAGE 28 PINS (TOP VIEW) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS51363 TPS51363 www.ti.com SLUSBB5A – FEBRUARY 2013 – REVISED JUNE 2013 PIN FUNCTIONS NAME NO. I/O/P DESCRIPTION BST 5 I Power supply for internal high side MOSFET. Connect a 0.1-µF bootstrap capacitor between this pin and SW pin. EN GND 28 I Enable signal, 1.05-V logic compatible. 19 — General device ground. GSNS 23 O GND sense input. Connect GSNS to general/system ground or GND sensing point at the output return. MODE 3 I Frequency (400 kHz or 800 kHz) programmable input (see Table 3). NC 4 — Not connected. NU 2, 27 — Not used for external applications. — Power ground. Connect to the system ground. 10 11 PGND 12 13 14 PGOOD 1 O PGOOD output. Connect a pull-up resistor with a value of 100 kΩ to this pin. Power PAD 29 — Connect to system ground by multiple vias. REFIN 25 I Target output voltage input pin. 0.6 V to 2 V, 1.05 V/1.2 V built-in (GND and Open) (see Table 2). REFIN2 24 I Tie to GND or float. This input is used to determine the fixed voltage setpoint (see Table 2). SLEW 21 O Connect a capacitor between this pin and GND for soft start and integrator functions. O Switching node output. Connect external inductor. 6 SW 7 8 9 TRIP 20 I OCL programmable input (see Table 4). V5 18 I 5-V power supply for analog circuits and gate driver. 15 I 16 I VIN Power supply input pin. Apply 3-V to 22-V of supply voltage. 17 I VREF 26 O 2-V reference output. Connect A 0.22-µF ceramic capacitor between this pin and the GNDS pin. VSNS 22 I Output voltage sense input. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS51363 7 TPS51363 SLUSBB5A – FEBRUARY 2013 – REVISED JUNE 2013 www.ti.com FUNCTIONAL BLOCK DIAGRAM REFIN REFIN2 PGOOD VREFIN – 34% VREF Reference + UV Reference Detection VREFIN + 20% + Delay GSNS + EN VREFIN + 20% Soft-Start + OV VREFIN - 8/34% SLEW VSNS VREFIN + PWM + · · · · · Control Mode On-Time Selection Control Logic On/Off Time Minimum On /Off SKIP/FCCM OCL/OVP/UVP Disharge MODE BST VIN Discharge Phase Compensation SW XCON tON One Shot TRIP TRIP Detection OCL Reference Voltage V5 OC + NOC + + 5-V UVLO + PGND V5OK ZC 4.4 V/4.0 V GND TPS51363 UDG-12235 8 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS51363 TPS51363 www.ti.com SLUSBB5A – FEBRUARY 2013 – REVISED JUNE 2013 TYPICAL CHARACTERISTICS 100 100 90 90 80 fSW = 400kHz LOUT = 1µH TA = 25°C VOUT = 1.05V 70 1 Output Current (A) fSW = 800kHz LOUT = 0.33µH TA = 25°C VOUT = 1.05V VIN = 7.4V VIN = 11.1V VIN = 20V 60 0.1 10 1 Output Current (A) G001 Figure 1. Figure 2. EFFICIENCY vs OUTPUT CURRENT EFFICIENCY vs OUTPUT CURRENT 100 90 90 Efficiency (%) 100 80 fSW = 400kHz LOUT = 1µH TA = 25°C VOUT = 1.35V 70 1 Output Current (A) VIN = 7.4V VIN = 11.1V VIN = 20V 1 Output Current (A) G003 Figure 3. Figure 4. FREQUENCY vs OUTPUT CURRENT FREQUENCY vs OUTPUT CURRENT 600 G002 fSW = 800kHz LOUT = 0.33µH TA = 25°C VOUT = 1.35V 60 0.1 10 10 80 70 VIN = 7.4V VIN = 11.1V VIN = 20V 60 0.1 10 G004 1000 fSW = 400kHz LOUT = 1µH TA = 25°C VOUT = 1.05V VIN = 7.4V VIN = 11.1V VIN = 20V fSW = 800kHz LOUT = 0.33µH TA = 25°C VOUT = 1.05V 950 900 Frequency (kHz) 550 Frequency (kHz) 80 70 VIN = 7.4V VIN = 11.1V VIN = 20V 60 0.1 Efficiency (%) EFFICIENCY vs OUTPUT CURRENT Efficiency (%) Efficiency (%) EFFICIENCY vs OUTPUT CURRENT 500 450 400 VIN = 7.4V VIN = 11.1V VIN = 20V 850 800 750 700 350 300 650 1 2 3 4 5 6 7 Output Current (A) 8 9 10 600 1 G005 Figure 5. 2 3 4 5 6 7 Output Current (A) 8 9 10 G006 Figure 6. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS51363 9 TPS51363 SLUSBB5A – FEBRUARY 2013 – REVISED JUNE 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) FREQUENCY vs OUTPUT CURRENT FREQUENCY vs OUTPUT CURRENT 600 1000 fSW = 400kHz LOUT = 1µH TA = 25°C VOUT = 1.35V fSW = 800kHz LOUT = 0.33µH TA = 25°C VOUT = 1.35V 950 900 Frequency (kHz) Frequency (kHz) 550 VIN = 7.4V VIN = 11.1V VIN = 20V 500 450 400 VIN = 7.4V VIN = 11.1V VIN = 20V 850 800 750 700 350 300 650 1 2 3 4 5 6 7 Output Current (A) 8 9 600 10 1.07 VIN = 7.4V VIN = 11.1V VIN = 20V 1.09 1.08 1.03 10 G008 1.03 1.00 0.1 10 VIN = 7.4V VIN = 11.1V VIN = 20V 1.04 1.01 1 Output Current (A) fSW = 800kHz LOUT = 0.33µH TA = 25°C VOUT = 1.05V 1.05 1.02 1 Output Current (A) G009 Figure 9. Figure 10. OUTPUT VOLTAGE vs OUTPUT CURRENT OUTPUT VOLTAGE vs OUTPUT CURRENT 1.40 10 G010 1.40 fSW = 400kHz LOUT = 1µH TA = 25°C VOUT = 1.35V VIN = 7.4V VIN = 11.1V VIN = 20V 1.39 Output Voltage (V) 1.38 1.36 1.35 1.34 1.33 1.37 1.35 1.34 1.33 1.32 1.31 1.31 10 VIN = 7.4V VIN = 11.1V VIN = 20V 1.36 1.32 1 Output Current (A) fSW = 800kHz LOUT = 0.33µH TA = 25°C VOUT = 1.35V 1.30 0.1 G011 Figure 11. 10 9 1.06 1.01 1.00 0.1 Output Voltage (V) 1.07 1.02 1.30 0.1 8 1.10 fSW = 400kHz LOUT = 1µH TA = 25°C VOUT = 1.05V 1.04 1.37 5 6 7 Output Current (A) OUTPUT VOLTAGE vs OUTPUT CURRENT 1.05 1.38 4 OUTPUT VOLTAGE vs OUTPUT CURRENT 1.06 1.39 3 Figure 8. Output Voltage (V) Output Voltage (V) 1.08 2 Figure 7. 1.10 1.09 1 G007 1 Output Current (A) 10 G012 Figure 12. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS51363 TPS51363 www.ti.com SLUSBB5A – FEBRUARY 2013 – REVISED JUNE 2013 TYPICAL CHARACTERISTICS (continued) 60 225 60 225 40 180 40 180 20 135 20 135 0 90 0 90 1k −40 −45 −60 −90 1M −80 Gain Phase 10k 100k Frequency (Hz) −20 0 270 Power Stage Design = 0.33µH + 6 × 22µF 45 fSW = 800kHz IOUT = 8A TA = 25°C VIN = 12V VOUT = 1.05V 1k 0 Gain Phase 10k G013 100k Frequency (Hz) Figure 13. Figure 14. GAIN and PHASE vs FREQUENCY GAIN and PHASE vs FREQUENCY −45 −90 1M G014 80 60 225 60 225 40 180 40 180 20 135 20 135 0 90 0 90 Power Stage Design = 1µH + 6 × 22µF −20 −60 −80 45 fSW = 400kHz IOUT = 8A TA = 25°C VIN = 12V VOUT = 1.35V −40 1k −40 −45 −60 100k Frequency (Hz) −90 1M −80 270 Power Stage Design = 0.33µH + 6 × 22µF −20 0 Gain Phase 10k Gain (dB) 270 80 45 fSW = 800kHz IOUT = 8A TA = 25°C VIN = 12V VOUT = 1.35V 1k 0 Gain Phase 10k G015 100k Frequency (Hz) −45 −90 1M Figure 15. Figure 16. OUTPUT VOLTAGE RIPPLE vs OUTPUT CURRENT OUTPUT VOLTAGE RIPPLE vs OUTPUT CURRENT Figure 17. f = 400kHz, VIN = 20V, IOUT = 0.1A Figure 18. f = 400kHz, VIN = 20V, IOUT = 8A Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS51363 Phase (°) −60 −80 45 fSW = 400kHz IOUT = 8A TA = 25°C VIN = 12V VOUT = 1.05V −40 Phase (°) Gain (dB) −20 Gain (dB) 80 Power Stage Design = 1µH + 6 × 22µF Phase (°) 270 80 Gain (dB) GAIN and PHASE vs FREQUENCY Phase (°) GAIN and PHASE vs FREQUENCY G016 11 TPS51363 SLUSBB5A – FEBRUARY 2013 – REVISED JUNE 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) 12 OUTPUT VOLTAGE RIPPLE vs OUTPUT CURRENT OUTPUT VOLTAGE RIPPLE vs OUTPUT CURRENT Figure 19. f = 800kHz, VIN = 20V, IOUT = 0.1A Figure 20. f = 800kHz, VIN = 20V, IOUT = 8A TRANSIENT PERFORMANCE vs SWITCHING FREQUENCY TRANSIENT PERFORMANCE vs SWITCHING FREQUENCY Figure 21. f = 400kHz, VIN = 20V, IOUT = 0–5A Figure 22. f = 800kHz, VIN = 20V, IOUT = 0–6A vs START-UP vs START-UP Figure 23. f = 400kHz, VIN = 20V, IOUT = 8A Figure 24. f = 800kHz, VIN = 20V, IOUT = 0A Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS51363 TPS51363 www.ti.com SLUSBB5A – FEBRUARY 2013 – REVISED JUNE 2013 TYPICAL CHARACTERISTICS (continued) vs SHUTDOWN vs SHUTDOWN Figure 25. f = 400kHz, VIN = 20V, IOUT = 8A Figure 26. f = 800kHz, VIN = 20V, IOUT = 0A AMBIENT TEMPERATURE vs OUTPUT CURRENT 90 Ambient Temperature (°C) 80 70 60 50 40 30 20 200 LFM Natural Convection 0 1 2 3 4 5 6 7 Output Current (A) fSW = 800 kHz VIN = 20 V VOUT =1.5 V 8 9 10 G017 Figure 27. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS51363 13 TPS51363 SLUSBB5A – FEBRUARY 2013 – REVISED JUNE 2013 www.ti.com APPLICATION INFORMATION Functional Overview The TPS51363 is an 8-A or 10-A (see Table 1), integrated FET synchronous step-down converter with differential voltage feedback support. It uses adaptive on-time D-CAP2 for compensation-less stable loop operation in POSCAP, POSCAP/MLCCs and all MLCCs output capacitor configurations. TPS51363 automatically operates in discontinuous mode to optimize light-load efficiency. A configurable 400-kHz or 800-kHz switching frequency enables optimization of the power train for cost, size and efficiency performance of the design. VREF, REFIN, REFIN2 and Output Voltage This device provides a 2.0-V, accurate voltage reference from the VREF pin. This output has a 300-uA sourcing current capability to drive voltage setpoint reference through a voltage divider circuit as shown in Figure 28. To ensure higher overall system voltage accuracy, the sum of the total resistance from VREF to GND should be designed to be more than 67kohm. A MLCC capacitor with a value of 0.1uF or larger should be attached close to the VREF pin. The voltage setpoint range supported by this device is between 0.6 V and 2.0 V. This device also supports resistor-less fixed voltage operation by the use of both REFIN and REFIN2 pins. Table 2 lists all the possible fixed voltage configurations by the REFIN and REFIN2 pin. The TPS51363 detects the state of both REFIN and REFIN2 during the initial startup and decides the output voltage setpoint for the operation. Table 2. REFIN and REFIN2 Pin Settings VOLTAGE (V) VOUT OUTPUT VOLTAGE (V) REFIN PIN (VREFIN) REFIN2 PIN (VREFIN2) GND GND 1.05 Float GND 1.2 GND Float 1.5 Float Float 1.35 Resistor dividers Either GND or Float Adjustable from 0.6 to 2.0 VREF 2 V TPS51363 Either REFIN2 R1 REFIN R2 VREF 0.1 mF UDG-13013 Figure 28. Setting the Output Voltage 14 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS51363 TPS51363 www.ti.com SLUSBB5A – FEBRUARY 2013 – REVISED JUNE 2013 PWM Operation TPS51363 employs DCAP2 mode operation. It uses an internal phase compensation network (RC1, RC2, CC1, CC2 and gain) to work with very low ESR output capacitors such as multi-layer ceramic capacitor (MLCC). The role of such network is to sense and scale the current ripple component of the output inductor current information and then use it in conjunction with the voltage feedback signal to achieve loop stability of the converter. The transconductance (gM) amplifier and SLEW capacitor (C1) forms an integrator. The output ripple voltage generated is inversed and averaged by this integrator. The AC information is superimposed onto otherwise DC information and forms a reference voltage at the input of the PWM comparator. As long as the integrator time constant is much larger than the inverse of the loop crossover frequency, the AC component is negligible. f gM £ 0 (2p ´ C1) 10 where • • gM is 60 µS f0 is 1/3 or 1/4 of the switching frequency (fSW) (1) The voltage difference (VSLEW – VVSNS) is then compared to the G×(CSP-CSN) (see Figure 30) voltage at the PWM comparator inputs. The PWM comparator creates a SET signal to turn on the high-side MOSFET during each cycle when the current level falls below the loop demand (see Figure 29). PWM Inductor Current REFIN Output Voltage SLEW CSP - CSN CSP - CSN SLEW - VOUT (1) tON UDG-13015 Time Figure 29. On-Time Waveforms (1) (1) ON time is initiated by (VOUT-SLEW) and (CSP-CSN) crossover Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS51363 15 TPS51363 SLUSBB5A – FEBRUARY 2013 – REVISED JUNE 2013 www.ti.com The device operates at two distinct switching frequencies, 400 kHz and 800 kHz. The switching frequency is configured by MODE pin for this converter operation (see Table 3). For stable operation of the buck converter, it is generally recommended to have a unity gain crossover (f0) of 1/4 or 1/3 or the switching frequency. (see Table 3). Table 3. Mode and Recommended Frequency Settings FREQUENCY (kHz) MODE CROSSOVER (f0) SWITCHING (fSW) MIN MAX GND 100 133 400 FLOAT 200 267 800 Given the range of the recommended unity gain frequency, the power stage design is flexible, as long as the following equation is satisfied. 1 1 fLC = £ ´ f0 10 2p ´ LOUT ´ COUT (2) Operating in D-CAP2 mode, the overall loop response is dominated by the internal phase compensation network. The compensation network is designed to have two identical zeros at 4 kHz (400-kHz operation) and 8 kHz (800kHz operation) in the frequency domain, which serves the purpose of splitting the LC double pole into one low frequency pole (same as the L-C double pole) and one high-frequency pole (greater than the unity gain crossover frequency). VIN CC1 VSNS SW R C1 22 CC2 SLEW C1 CSP CSN 21 G – – + + REFIN RC2 PWM Comparator LX Control Logic and Driver VOUT ESR 25 R LOAD C OUT PGND R1 VREF 26 + 2.0 V R2 TPS51363 UDG-13014 Figure 30. Simplified Architecture Illustrating DCAP2 Mode Light-Load Operation The mandatory light load operation for TPS51363 is referred to as auto skip. In auto-skip mode, the control logic automatically reduces its switching frequency to improve light load efficiency. To achieve this intelligence, a zero crossing detection comparator is used to prevent negative inductor current by turning off the low side FET when the SW crossing zero is detected. The equation below shows the boundary load condition of this skip mode and continuous conduction operation. (V - VOUT ) VOUT 1 ILOAD(LL ) = IN ´ ´ 2 ´ LX VIN fSW (3) 16 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS51363 TPS51363 www.ti.com SLUSBB5A – FEBRUARY 2013 – REVISED JUNE 2013 Power Sequences: Soft-Start and Power Good Prior to asserting EN high, the power stage conversion voltage and V5IN voltage should be up and running. When EN is asserted high, TPS51363 provides soft start operation to suppress in-rush current during startup. The soft start action is achieved by an internal SLEW current of 10 µA (typ) sourcing into a small external MLCC capacitor connected from SLEW pin to GND. Use Equation 4 to determine the soft-start timing. V tSS = CSLEW ´ OUT ISLEW where • • • CSLEW is the soft-start capacitance VOUT is the output voltage ISLEW is the internal, 10-µA current source (4) The TPS51363 includes a PGOOD open drain output. During the startup, once the output voltage is slewing up within -8% of the final setpoint target, the PGOOD becomes asserted after 1.5 ms of delay from the end of the soft-start period. During the operation, if the output voltage rises beyond 120% (typ) of the setpoint, the PGOOD pin becomes immediately de-asserted without hysteresis. Re-asserting the PGOOD pin requires either resetting either the V5IN pin or the EN pin. If the output voltage falls below 68% (typ) of the setpoint, the PGOOD pin becomes immediately de-asserted without hysteresis. Re-asserting the PGOOD pin requires resetting either the V5IN pin or the EN pin. Fault Protection Overcurrent Limit TPS51363 integrates both high side and low side FETs to support a maximum DC current of 8-A or 10-A operation. The current sensing method employed for over current limit is to monitor the SW node during the “ON” state of the low side FET for each switching cycle. TRIP pin is used to program one of the two current limits for TPS51363 operation (see Table 4). When the overcurrent limit is detected, the converter does not allow the next “ON” cycle for the high side FET until the overcurrent limit is no longer reached. This ensures the safe operation of the converter. And when the overcurrent limit condition persists, the current to the load exceeds the current to the output capacitors, the output voltage tends to fall. When the output voltage falls below the undervoltage protection threshold, the converter latch shut down. Table 4. TRIP Pin Settings TRIP TYPICAL OCL LIMIT IOCL (A) GND 8 5V 12 Negative Overcurrent Limit TPS51363 is also protected by the negative over current limit. Both positive and negative current limit is programmed by the TRIP pin. Negative current limit level is the same as that of positive current limit level (see Table 4). During the normal converter operation, negative current is not allowed due to the mandatory light load operation for this device (Auto Skip). It is during the OOB or OVP operation, negative overcurrent might be engaged. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS51363 17 TPS51363 SLUSBB5A – FEBRUARY 2013 – REVISED JUNE 2013 www.ti.com Out-of-Bounds Operation (OOB) When the output voltage rises to 8% above the target value, the out-of-bound operation starts. During the OOB operation, the controller operates in forced PWM-only mode by turning on low side FET. Turning on the low side FET beyond the zero inductor current can quickly discharge the output capacitor thus causing VOUT to fall quickly towards setpoint. During the operation, the cycle by cycle negative current limit is also activated to ensure the safe operation of the internal FETs. Overvoltage Profection (OVP) and Undervoltage Protection (UVP) When the output voltage rises to a level 20% (typ) higher than the setpoint voltage, an overvoltage condition is present. When a 0-V event is detected, the converter turns off the high side FET and turns on the low side FET. The operation continues until the cycle by cycle negative current limit is reached and low side FET is turned off and high side FET is turned on, for a minimum on-time. After the minimum on-time expires, the high side FET is driven off and low side FET is driven on again until negative current limit is reached or VOUT is discharged to 0 V. When the VOUT is discharged to 0 V, both high-side and low-side FETs are latched off. An OVP fault requires the V5IN voltage to fall below POR threshold or EN reset to clear. Undervoltage Protection (UVP) The undervoltage protection (UVP) is set when the VOUT voltage falls below 68% (typ) of the setpoint voltage for 1msec or longer. In this fault condition, the converter turns off both high-side and low-side FETs. The UVP function is enabled after 1.4 ms of soft start completion. An UVP fault requires 5-V UVLO or EN reset. V5IN Undervoltage Lockout (UVLO) Protection TPS51363 has a 5-V supply undervoltage lockout protection (UVLO) threshold. When the V5IN voltage is lower than UVLO threshold voltage, Vout is shut off. This is a non-latch protection. Power-On-Reset (POR) To prevent single rail supply voltage brown-out due to output OV condition, when the output voltage is shut down due to OVP fault, Power-on-Reset (POR) on V5IN is implemented. To reset OVP fault, V5IN voltage must fall below POR threshold voltage of 1.7 V (typ) or EN reset to clear. Thermal Shutdown TPS51363 includes an internal temperature monitor. If the die temperature exceeds the threshold (published in the EC table of this datasheet), the converter will be shutdown. This is a non-latch protection and the operation is restarted with soft-start sequence when the device temperature is reduced by the hysteresis. 18 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS51363 TPS51363 www.ti.com SLUSBB5A – FEBRUARY 2013 – REVISED JUNE 2013 DESIGN PROCEDURE Introduction The simplified design procedure is done for a VCCIO rail for Intel platform application using TPS51363. Step One: Determine the system specifications. The VCCIO rail requirements provide the following key parameters: • VOUT = 1.05 V • ICC(max) = 6 A • IDYN(max) = 4 A Step Two: Determine the power supply design specifications. The input voltage range and operating frequency are of primary interest. For this example: • 7.4 V ≤ VIN ≤ 19.5 V • fSW = 800 kHz Step Three: Set the output voltage. TPS51363 supports resistor-less fixed voltage operation by the use of both REFIN and REFIN2 pins (see Table 2). Grounding both REFIN and REFIN2 pins provides a 1.05-V fixed output setpoint. Step Four: Determine inductance value and choose inductor. Smaller values of inductor have better transient performance and smaller physical size but higher ripple and lower efficiency. Higher values have the opposite characteristics. It is common practice to limit the ripple current to 25% to 50% of the maximum current. For this example,use 30% as a starting point. IL(P-P)= 6 A × 0.30 = 1.8 A. For a switching frequency of 800 kHz, maximum 19.5-V input and 1.05-V output. æ L= V ´ dT = IP-P VOUT ö ÷ f è SW ´ VIN ø æ (VIN - VOUT )´ ç IP-P ö 1.05V ÷ è 800kHz ´ 19.5 V ø = 0.68 mH 1.8 A (19.5 V - 1.05 V )´ ç = (5) For this application, a 0.68-µH, 6.8-mm × 7.3-mm × 3.0-mm inductor with typical DCR of 4.8 mΩ and heating current of 16 A is chosen. The Cyntec part number of the inductor is PIMB063T. Step Five: Calculate SLEW capacitance. The SLEW pin is used to program the soft-start time. During soft-start operation, the current source used to program the SLEW rate is 10 µA (typ). In this design example, the soft-start timing should be target to be in the range of 500 µs to 2 ms. The proper slew rate design minimizes large inductor current perturbation during the startup, thus reducing the possibility of acoustic noise in the system. dt CSLEW = ISLEW ´ = 10nF DVOUT (6) • • • ISLEW = 10 µA, dt = tSS = 1 ms ΔVOUT = 1.05 V Step Six: Select the proper OCL. There are two options for the over current limit (see Table 4). For this application example, because ICC(max) = 6 A, the proper OCL level should be set at least 30% over the ICC(max) level, which makes the 8-A OCL appropriate for this design. Grounding the TRIP pin achieves this effect. Step Seven: Determine the output capacitance. The amount of the output capacitance needed for this design is both a function of loop stability and of transient requirement. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS51363 19 TPS51363 SLUSBB5A – FEBRUARY 2013 – REVISED JUNE 2013 www.ti.com Stability considerations The switching frequency of the design example is 800 kHz (which is set by the MODE pin, see Table 4). For DCAP2 mode operation, it is generally recommended to have a unity gain crossover (f0) of less than 1/4 or 1/3 of the switching frequency, which is approximately between 200 kHz and 266 kHz. In this design example, use 1/4. f f0 = SW = 200kHz 4 (7) Given the range of the recommended unity gain crossover frequency, the power stage design is flexible, as long as the L-C double pole frequency is less than 10% of f0. When the above criterion is met, the internal compensation network provides sufficient phase boost at the unity gain crossover frequency such that the converter is stable with sufficient phase margin (greater than 60°). When the ESR frequency of the output bulk capacitor is in the vicinity of the unity gain crossover frequency of the loop, additional phase boost can be achieved. This applies to higher ESR output bulk capacitor, POSCAP and SPCAP. When the ESR frequency of the output capacitor is beyond the unity gain crossover frequency of the control loop, no additional phase boost is achieved. This applies to low or ultra low ESR output capacitor, such as MLCCs. For this application example,consider only all MLCCs for output capacitors. Based on Equation 3 and Equation 7, the minimum capacitance for stable operation is calculated to be 110 µF. Transient considerations • • • IDYN(max) = 4 A di/dt = 2.5 A/µs VOUT deviation = ±3% for the given transient Use Equation 8 and Equation 9 to estimate the amount of capacitance needed for a given dynamic load/release. ö 2 æV ´t L ´ DILOAD(max) ´ ç OUT SW + tMIN(off ) ÷ ç VIN(min) ÷ è ø COUT(min_ under) = æ æ VIN(min) - VOUT ö ö 2 ´ DVLOAD(insert) ´ ç ç ÷ ´ tSW - tMIN(off ) ÷ ´ VOUT ÷ çç ÷ VIN(min) ø èè ø (8) ( ( ) 2 ) LOUT ´ DILOAD(max) COUT(min_ over) = 2 ´ DVLOAD(release) ´ VOUT (9) Based on these calculation, to meet the transient requirement, the minimum amount of capacitance in this design is 164 µF. Considering both stability and transient, the minimum capacitance is 164 µF. The design example uses 8, 22-µF capacitors with minor consideration of the MLCC derating for both DC and AC effect. Step Eight: Select decoupling and peripheral components For the TPS51363, peripheral capacitors use the following minimum values of ceramic capacitance. X5R or better temperature coefficient is recommended. Tighter tolerance and higher voltage rating are always appropriate. • V5IN decoupling ≥ 2.2 µF, ≥ 10 V • VREF decoupling 0.1 µF to 1 µF, ≥ 4 V • Bootstrap capacitor ≥ 0.1 µF, ≥ 10 V • Pull-up resistors on PGOOD, 100 kΩ Step Nine: Layout guidelines Figure 31 applies to the layer where device is situated. Additional reinforcement of VIN, PGND, and VOUT through vias are always recommended. 20 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS51363 TPS51363 NU MODE NC VIN 1 4 5 6 7 8 9 SW PGOOD PGND SW 4 PGND SW 3 PGND SW 2 PGND BST 1 PGND 1 3 1 5 1 2 1 6 1 1 1 7 1 0 V5 VIN GND 1 8 VIN SLEW TRIP 1 9 2 8 EN 2 0 2 7 NU 2 1 2 6 VREF 2 2 2 5 REFIN 2 3 2 4 REFIN2 VSNS SLUSBB5A – FEBRUARY 2013 – REVISED JUNE 2013 GSNS www.ti.com Figure 31. TPS51363 Design Layout Input capacitors, output capacitors, and the output inductor are the power components and should be placed on one side of the PCB. Small signal components can be placed on the same side of the PCB with proper ground isolation or the opposite side with at least one inner ground plane in between, depending on the system/motherboard design requirement. All sensitive analog traces and components such as VSNS, GSNS, SLEW, VREF, REFIN and REFIN2 should be placed away from the high voltage switching node, such as SW and BST to avoid switching noise coupling. Use internal layer(s) as ground plane(s) and shield feedback traces from power traces. VSNS can be connected directly to the output voltage sense point at the load device or the bulk capacitor at the converter side. Connect GSNS to ground return at the general ground plane/layer. VSNS and GSNS can be used for the purpose of remote sensing across the load device, however, ensure to minimize the routing trace length to prevent excess noise injection into the sense lines. In order to effectively remove heat from the package, prepare the thermal land and solder to the package thermal pad. Wide trace of the component-side copper, connected to this thermal land, helps to dissipate the heat. Numerous vias (at least 6) with a 0.3-mm diameter connected from the thermal land to the internal/solder side ground plane(s) should be used to help dissipation. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS51363 21 TPS51363 SLUSBB5A – FEBRUARY 2013 – REVISED JUNE 2013 www.ti.com REFERENCE DESIGNS This section describes two typical application circuits using the TPS51363. Design 1 This design is a VCCIO application with an output voltage of 1.05 V, maximum processor current (ICC(max)) of 6 A, an OCL of 8 A and a switching frequency of 800 kHz. V5 5V 2.2 mF VSNS 10 nF GSNS 0.1 μF 23 22 21 GSNS VSNS SLEW 20 19 TRIP GND 18 17 16 15 V5 VIN VIN VIN 2 x 10 mF GND 24 REFIN2 PGND 14 GND 25 REFIN PGND 13 26 VREF 0.1 mF PGND 12 TPS51363 27 NU PGND 11 28 EN PGND 10 PGOOD NU MODE NC 1 2 3 4 VIN 7.4 V to 20 V BST SW SW SW SW 5 6 7 8 9 8 x 22 mF 0.68 mH EN VOUT 0.1 mF PGOOD 1.05 V UDG-13029 Figure 32. Design 1: Application Schematic Table 5. Design 1: List of Materials 22 REFERENCE DESIGNATOR QTY SPECIFICATION MANUFACTURER PART NUMBER CIN 2 10 µF, 25 V Taiyo Yuden TMK325BJ106MM COUT 8 22 µF, 6.3 V Murata GRM21BB30J226ME38 LOUT 1 0.68 µH, 4.8 mΩ Cyntec PIMB063T-R68MS-63 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS51363 TPS51363 www.ti.com SLUSBB5A – FEBRUARY 2013 – REVISED JUNE 2013 Design 2: This design is a DDR3L, VDDQ, application with an output voltage of 1.35 V, maximum processor current (ICC(max)) of 8 A, an OCL of 12 A, and a switching frequency of 400 kHz. V5 5V 2.2 mF VSNS 10 nF GSNS 0.1 μF 23 22 21 GSNS VSNS SLEW 20 TRIP GND 18 17 16 15 V5 VIN VIN VIN 4 x 10 mF 24 REFIN2 PGND 14 25 REFIN PGND 13 26 VREF 0.1 mF 19 PGND 12 TPS51363 27 NU PGND 11 28 EN PGND 10 PGOOD NU MODE NC 1 2 3 4 VIN 7.4 V to 20 V BST SW SW SW SW 5 6 7 8 9 270 mF 1 mH EN VOUT 0.1 mF PGOOD 1.35 V UDG-13018 Figure 33. Design 2: Application Schematic Table 6. Design 2: List of Materials REFERENCE DESIGNATOR QTY SPECIFICATION MANUFACTURER PART NUMBER CIN 4 10 µF, 25 V Taiyo Yuden TMK325BJ106MM COUT 1 270 µF, 2 V Panasonic 2TPSF270M6E LOUT 1 1 µH, 6.7 mΩ Cyntec PIMB063T-1R0MS-63 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS51363 23 TPS51363 SLUSBB5A – FEBRUARY 2013 – REVISED JUNE 2013 www.ti.com REVISION HISTORY NOTE: Page numbers of current version may differ from previous versions. Changes from Original (February 2013) to Revision A Page • Added MIN and MAX values to IOCL spec in Elec Char table ............................................................................................... 5 • Changed the Functional Block Diagram VREFIN signal line identifier on the UV-detect device from "VREFIN – 32%" to "VREFIN – 34%". Changed signal line identifier on the high-side comparator from "VREFIN+ 8/20%" to "VREFIN+ 20%". Changed the high-side device symbol from hysteresis to a comparator. Changed signal line identifier on the lowside device from "VREFIN– 8/32%" to "VREFIN– 8/34%. ........................................................................................................... 8 • Added Land pads for a 0.1-µF capacitor between VIN and PGND of the TPS51363 Design Layout figure. .................... 21 • Added a 0.1-µF capacitor symbol between VIN and PGND of the Design 1: Application Schematic. ............................... 22 • Changed LOUT inductor part number from PIMB063T to PIMB063T-R68MS-63 in Design 1: List of Materials table. ....... 22 • Changed text from "LPDDR3" to "DDR3L" in Design 2 description section. ...................................................................... 23 • Added 0.1 µF capacitor symbol between VIN and PGND in Design 2: Application Schematic figure ............................... 23 • Changed LOUT inductor spec from 1 µH, 6.5 mΩ to 6.7 mΩ, and part number from PCME063T to PIMB063T1R0MS-63 in Design 2: List of Materials table. .................................................................................................................. 23 24 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS51363 PACKAGE OPTION ADDENDUM www.ti.com 11-Aug-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) FX033 ACTIVE VQFN RVE 28 3000 Pb-Free (RoHS Exempt) CU NIPDAU Level-2-260C-1 YEAR -10 to 85 TPS51363 FX033Z ACTIVE VQFN RVE 28 3000 Pb-Free (RoHS Exempt) CU NIPDAU Level-2-260C-1 YEAR -10 to 85 TPS51363 TPS51363RVER ACTIVE VQFN RVE 28 3000 Pb-Free (RoHS Exempt) CU NIPDAU Level-2-260C-1 YEAR -10 to 85 TPS51363 TPS51363RVET ACTIVE VQFN RVE 28 250 Pb-Free (RoHS Exempt) CU NIPDAU Level-2-260C-1 YEAR -10 to 85 TPS51363 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 16-May-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS51363RVER VQFN RVE 28 3000 330.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1 TPS51363RVET VQFN RVE 28 250 180.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-May-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS51363RVER VQFN RVE 28 3000 367.0 367.0 35.0 TPS51363RVET VQFN RVE 28 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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