3VD037060NEJL 3VD037060NEJL STRUCTURE N-CH MOSFET CHIPS WITH ESD PROTECTED DESCRIPTION ¾ 3VD037060NEJL is a N-Channel enhancement mode MOS-FET chip fabricated in advanced silicon epitaxial planar technology. ¾ Zener diode ESD protected up to 500V (HBM). ¾ High density cell design for low RDS (ON). ¾ Rugged and reliable. ¾ Fast switching performance. ¾ High saturation current capability. ¾ The chips may be packaged in SOT-23 type . CHIP TOPOGRAPHY ¾ The packaged product is widely used in the small servo motor control, power MOS-FET gate drivers, and other switching applications. ¾ Die size: 0.37mm*0.37mm. ¾ Chip Thickness: 230±20μm. ¾ Top metal: Al, Backside Metal: Au. EQUIVALENT CIRCUIT ABSOLUTE MAXIMUM RATINGS (Tamb=25°C) Parameter Symbol Ratings Unit Drain-Source Voltage VDS 60 V Gate-Source Voltage VGS ±20 V ID 100 mA Drain Current --Plused * IDM 600 mA Power Dissipation (SOT-23) PD 200 mW Operation Junction Temperature TJ 150 °C Tstg -55-150 °C Drain Current Storage Temperature Note:* Repetitive rating: pulse width limited by maximum junction temperature. ELECTRICAL CHARACTERISTICS (Tamb=25°C) Parameter Symbol Drain-Source Breakdown Voltage V(BR)DSS Min. Typ. Max. Unit VGS=0V, ID=10µA 60 - - V Vth(GS) VDS= VGS, ID=250µA 1.2 - 2.0 V Gate-body Leakage lGSS VDS=0V, VGS =±20V - - ±5 µA Zero Gate Voltage Drain Current IDSS VDS=60V, VGS =0V - - 1 µA VGS=5.0V, ID=100mA - 4 6 VGS=10V, ID=100mA - 3 5 Gate-Threshold Voltage* Drain-Source On-Resistance * RDS(on) Test conditions HANGZHOU SILAN MICROELECTRONICS CO.,LTD Http: www.silan.com.cn REV:1.1 Ω 2008.10.15 Page 1 of 1