TPA6130A2 YZH RTJ www.ti.com SLOS488B – NOVEMBER 2006 – REVISED FEBRUARY 2008 138-mW DIRECTPATH™ STEREO HEADPHONE AMPLIFIER WITH I2C VOLUME CONTROL • FEATURES 1 • DirectPath™ Ground-Referenced Outputs – Eliminates Output DC Blocking Capacitors – Reduces Board Area – Reduces Component Height and Cost – Full Bass Response Without Attenuation • Power Supply Voltage Range: 2.5 V to 5.5 V • 64 Step Audio Taper Volume Control • High Power Supply Rejection Ratio (>100 dB PSRR) • Differential Inputs for Maximum Noise Rejection (68 dB CMRR) • High-Impedance Outputs When Disabled • Advanced Pop and Click Suppression Circuitry Digital I2C Bus Control – Per Channel Mute and Enable – Software Shutdown – Multi-Mode Support: Stereo HP, Dual Mono HP, and Single-Channel BTL Operation – Amplifier Status Space Saving Packages – 20 Pin, 4 mm x 4 mm QFN – 16 ball, 2 mm x 2 mm WCSP ESD Protection of 8 kV HBM and IEC Contact 2 • • APPLICATIONS • • • • Mobile Phones Portable Media Players Notebook Computers High Fidelity Applications DESCRIPTION The TPA6130A2 is a stereo DirectPath™ headphone amplifier with I2C digital volume control. The TPA6130A2 has minimal quiescent current consumption, with a typical IDD of 4 mA, making it optimal for portable applications. The I2C control allows maximum flexibility with a 64 step audio taper volume control, channel independent enables and mutes, and the ability to configure the outputs into stereo, dual mono, or a single receiver speaker BTL amplifier that drives 300 mW of power into 16 Ω loads. The TPA6130A2 is a high fidelity amplifier with an SNR of 98 dB. A PSRR greater than 100 dB enables direct-to-battery connections without compromising the listening experience. The output noise of 9 µVrms (typical A-weighted) provides a minimal noise background during periods of silence. Configurable differential inputs and high CMRR allow for maximum noise rejection in the noisy environment of a mobile device. TPA6130A2 packaging includes a 2 by 2 mm chip-scale package, and a 4 by 4 mm QFN package. SIMPLIFIED APPLICATION DIAGRAM 2 I C GPIO Audio Source SCL SDA SD LEFTINM Left Out M HPLEFT 0.47 mF Left Out P LEFTINP 0.47 mF Right Out M RIGHTINM TPA6130A2 HPRIGHT 0.47 mF Right Out P RIGHTINP GND 0.47 mF GND CPP CPN CPVSS 1 mF VDD 1 mF VDD 1 mF 1 mF 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DirectPath is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2008, Texas Instruments Incorporated TPA6130A2 www.ti.com SLOS488B – NOVEMBER 2006 – REVISED FEBRUARY 2008 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. FUNCTIONAL BLOCK DIAGRAM LEFTINM Left HPLEFT LEFTINP Gain Control De-Pop RIGHTINM HPRIGHT Right RIGHTINP Thermal Current Limit Charge Pump Power Management CPP CPN SD I2C Interface and Control SDA SCL CPVSS VDD GND VDD GND Headphone channels are independently enabled and muted. The I2C interface controls channel gain, device modes, and charge pump activation. The charge pump generates a negative supply voltage for the output amplifiers. This allows a 0 V bias at the outputs, eliminating the need for bulky output capacitors. The thermal block detects faults and shuts down the device before damage occurs. The I2C register records thermal fault conditions. The current limit block prevents the output current from getting high enough to damage the device. The De-Pop block eliminates audible pops during power-up, power-down, and amplifier enable and disable events. 2 Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): TPA6130A2 TPA6130A2 www.ti.com A3 A2 A1 CPN CPP GND VDD VDD GND CPP CPN B1 B2 B3 B4 B4 B3 B2 B1 HPLEFT CPVSS LEFTINP LEFTINM LEFTINM LEFTINP CPVSS HPLEFT C1 C2 C3 C4 C4 C3 C2 C1 VDD GND GND VDD D1 D2 D3 D4 D4 D3 D2 D1 HPRIGHT SCL SDA SD SD SDA SCL HPRIGHT RIGHTINP RIGHTINM RIGHTINM RIGHTINP Top (Symbol Side) View WCSP Package (YZH) GND CPP CPN CPVSS 20 19 18 17 16 LEFTINM 1 15 CPVSS LEFTINP 2 14 HPLEFT GND 3 13 GND RIGHTINP 4 12 VDD RIGHTINM 5 11 HPRIGHT T op View 6 7 8 9 10 GND A4 GND A4 SCL A3 SDA A2 SD A1 VDD SLOS488B – NOVEMBER 2006 – REVISED FEBRUARY 2008 Bottom (Ball Side) View WCSP Package (YZH) Top View QFN Package (RTJ) TERMINAL FUNCTIONS TERMINAL INPUT/ OUTPUT/ POWER (I/O/P) DESCRIPTION BALL WCSP PIN QFN VDD A4 20 P Charge pump voltage supply. VDD must be connected to the common VDD voltage supply. Decouple to GND (pin 19 on the QFN) with its own 1 µF capacitor. GND A3 19 P Charge pump ground. GND must be connected to common supply GND. It is recommended that this pin be decoupled to the VDD of the charge pump pin (pin 20 on the QFN). CPP A2 18 P Charge pump flying capacitor positive terminal. Connect one side of the flying capacitor to CPP. CPN A1 17 P Charge pump flying capacitor negative terminal. Connect one side of the flying capacitor to CPN. LEFTINM B4 1 I Left channel negative differential input. Impedance must be matched to LEFTINP. Connect the left input to LEFTINM when using single-ended inputs. LEFTINP B3 2 I Left channel positive differential input. Impedance must be matched to LEFTINM. AC ground LEFTINP near signal source while maintaining matched impedance to LEFTINM when using single-ended inputs. CPVSS B2 15, 16 P Negative supply generated by the charge pump. Decouple to pin 19 on the QFN or a GND plane. Use a 1 µF capacitor. HPLEFT B1 14 O Headphone left channel output. Connect to left terminal of headphone jack. RIGHTINM C4 5 I Right channel negative differential input. Impedance must be matched to RIGHTINP. Connect the right input to RIGHTINM when using single-ended inputs. RIGHTINP C3 4 I Right channel positive differential input. Impedance must be matched to RIGHTINM. AC ground RIGHTINP near signal source while maintaining matched impedance to RIGHTINM when using single-ended inputs. GND C2 3, 9, 10, 13 P Analog ground. Must be connected to common supply GND. It is recommended that this pin be used to decouple VDD for analog. Use pin 13 to decouple pin 12 on the QFN package. VDD C1 12 P Analog VDD. VDD must be connected to common VDD supply. Decouple with its own 1-µF capacitor to analog ground (pin 13 on the QFN). SD D4 6 I Shutdown. Active low logic. 5V tolerant input. SDA D3 7 I/O SDA - I2C Data. 5V tolerant input. SCL D2 8 I SCL - I2C Clock. 5V tolerant input. HPRIGHT D1 11 O Headphone light channel output. Connect to the right terminal of the headphone jack. Thermal pad N/A Die Pad P Solder the thermal pad on the bottom of the QFN package to the GND plane of the PCB. It is required for mechanical stability and will enhance thermal performance. NAME 3 Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): TPA6130A2 TPA6130A2 www.ti.com SLOS488B – NOVEMBER 2006 – REVISED FEBRUARY 2008 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range, TA = 25°C (unless otherwise noted) VALUE / UNIT Supply voltage, VDD VI –0.3 V to 6.0 V RIGHTINx, LEFTINx Input voltage –2.7 V to 3.6 V SD, SCL, SDA –0.3 V to 7 V Output continuous total power dissipation See Dissipation Rating Table TA Operating free-air temperature range –40°C to 85°C TJ Operating junction temperature range –40°C to 125°C Tstg Storage temperature range –65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C HBM Output Pins ESD Protection 8 kV HBM All Other Pins IEC Contact ESD Protection (2) 3.5 kV No External Protection 8 kV V14MLA0603 Varistors Used for External Protection 15 kV 12.8 Ω Minimum Load Impedance (1) (2) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Tested to IEC 61000-4-2 standards on a TPA6130A2 EVM. DISSIPATION RATINGS TABLE (1) (2) PACKAGE TA ≤ 25°C POWER RATING RTJ YZH DERATING FACTOR (1) (2) TA = 70°C POWER RATING TA = 85°C POWER RATING 4100 mW 41 mW/°C 2250 mW 1640 mW 970 mW 9.7 mW/°C 530 mW 390 mW Derating factor measured with JEDEC High K board: 1S2P - One signal layer and two plane layers. See JEDEC Standard 51-3 for Low-K board, JEDEC Standard 51-7 for High-K board, and JEDEC Standard 51-12 for using package thermal information. Please see JEDEC document page for downloadable copies: http://www.jedec.org/download/default.cfm. AVAILABLE OPTIONS TA –40°C to 85°C (1) (2) PACKAGED DEVICES (1) PART NUMBER SYMBOL 20-pin, 4 mm × 4 mm QFN TPA6130A2RTJ (2) BSG 16-ball, 1,98 mm × 1.98 mm (+0,01mm, –0,09 mm) TPA6130A2YZH BRU For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. The RTJ package is only available taped and reeled. To order, add the suffix “R” to the end of the part number for a reel of 3000, or add the suffix “T” to the end of the part number for a reel of 250 (e.g., TPA6130A2RTJR). RECOMMENDED OPERATING CONDITIONS Supply voltage, VDD VIH High-level input voltage SCL, SDA, SD MIN MAX 2.5 5.5 1.3 SCL, SDA VIL Low-level input voltage TA Operating free-air temperature –40 4 V V 0.6 SD UNIT V 0.35 V 85 °C Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): TPA6130A2 TPA6130A2 www.ti.com SLOS488B – NOVEMBER 2006 – REVISED FEBRUARY 2008 ELECTRICAL CHARACTERISTICS TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT |VOS| Output offset voltage VDD = 2.5 V to 5.5 V, inputs grounded 150 400 µV PSRR Power supply rejection ratio VDD = 2.5 V to 5.5 V, inputs grounded –109 –90 dB CMRR Common mode rejection ratio VDD = 2.5 V to 5.5 V |IIH| High-level input current VDD = 5.5 V, VI = VDD |IIL| Low-level input current VDD = 5.5 V, VI = 0 V –68 1 SD 10 SCL, SDA, SD Supply current µA 1 µA 4 6 mA Shutdown mode, VDD = 2.5V to 5.5 V, SD = 0 V 0.4 1 µA SW Shutdown mode, VDD = 2.5V to 5.5 V, SWS = 1 25 75 µA Both HP amps disabled, VDD = 2.5V to 5.5 V, SWS = 0, Charge Pump enabled, SD = VDD 1.4 2.5 mA VDD = 2.5 V to 5.5 V, SD = VDD IDD dB SCL, SDA TIMING CHARACTERISTICS (1) (2) For I2C Interface Signals Over Recommended Operating Conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT 400 kHz Frequency, SCL tw(H) Pulse duration, SCL high 0.6 µs tw(L) Pulse duration, SCL low 1.3 µs tsu1 Setup time, SDA to SCL 300 ns th1 Hold time, SCL to SDA 10 ns t(buf) Bus free time between stop and start condition 1.3 µs tsu2 Setup time, SCL to start condition 0.6 µs th2 Hold time, start condition to SCL 0.6 µs tsu3 Setup time, SCL to stop condition 0.6 µs (1) (2) No wait states TYP fSCL VPull-up = VDD A pull-up resistor ≤2 kΩ is required for a 5 V I2C bus voltage. tw(L) tw(H) SCL t su1 th1 SDA Figure 1. SCL and SDA Timing 5 Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): TPA6130A2 TPA6130A2 www.ti.com SLOS488B – NOVEMBER 2006 – REVISED FEBRUARY 2008 SCL th2 t(buf) tsu2 tsu3 Start Condition Stop Condition SDA Figure 2. Start and Stop Conditions Timing OPERATING CHARACTERISTICS VDD = 3.6 V , TA = 25°C, RL = 16 Ω (unless otherwise noted) PARAMETER TEST CONDITIONS Stereo, Outputs out of phase, THD = 1%, f = 1 kHz, Gain = 0.1 dB PO Output power Bridge-tied load, THD = 1%, f = 1 kHz, Gain = 0.1 dB MIN 60 VDD = 3.6V 127 VDD = 5V 138 VDD = 2.5V 110 VDD = 3.6V 230 VDD = 5V THD+N kSVR ΔAv Total harmonic distortion plus noise Supply ripple rejection ratio PO = 35 mW 0.0029% f = 1 kHz 0.0055% f = 20 kHz 0.0027% 200 mVpp ripple, f = 217 Hz -97 200 mVpp ripple, f = 1 kHz -93 200 mVpp ripple, f = 20 kHz -76 fosc Charge pump switching frequency See Figure 33 Signal-to-noise ratio Po = 35 mW ZO Tri-state HP output impedance CO Output capacitance -90 dB V/µs 9 300 Differential input impedance Thermal shutdown mW 0.3 VDD = 3.6V, A-weighted, Gain = 0.1 dB Start-up time from shutdown SNR UNIT 1% Slew rate Noise output voltage MAX 290 f = 100 Hz Gain matching Vn TYP VDD = 2.5V 400 µVRMS 500 kHz 5 ms 98 dB Threshold 180 °C Hysteresis 35 °C HiZ left and right bits set. HP amps disabled. DC value. 25 MΩ 80 pF 6 Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): TPA6130A2 TPA6130A2 www.ti.com SLOS488B – NOVEMBER 2006 – REVISED FEBRUARY 2008 TYPICAL CHARACTERISTICS C(PUMP, DECOUPLE, ,BYPASS, CPVSS) = 1 µF, CI = 2.2µF. All THD + N graphs taken with outputs out of phase (unless otherwise noted). Table of Graphs FIGURE Total harmonic distortion + noise vs Output power 3–8 Total harmonic distortion + noise vs Frequency 9–22 Supply voltage rejection ratio vs Frequency 23-25 Common mode rejection ratio vs Frequency 26-27 Output power vs Load 28-29 Output voltage vs Load 30-31 Power Dissipation vs Output power 32 Differential Input Impedance vs Gain 33 Shutdown time 34 Startup time 35 RL = 16 W, 1 Gain = 0.1 dB, VDD = 3.6 V, fIN = 1 kHz, Stereo 0.1 In Phase Out of Phase 0.01 0.001 100m 1m 10m 100m 1 10 RL = 32 W, Gain = 0.1 dB, VDD = 3.6 V, 1 fIN = 1 kHz, Stereo 0.1 0.01 PO - Output Power - W 1m 10m 100m PO - Output Power - W 1 10 RL = 16 W, 1 Gain = 0.1 dB, fIN = 1 kHz, Stereo VDD = 2.5 V VDD = 3 V 0.1 VDD = 3.6 V 0.01 VDD = 5 V 0.001 100m 1m 10m 100m 1 PO - Output Power - W Figure 4. Figure 5. TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 10 RL = 32 W, Gain = 0.1 dB, fIN = 1 kHz, 1 Stereo VDD = 2.5 V 0.1 VDD = 5 V 0.01 VDD = 3.6 V 0.001 100m VDD = 3 V 1m 10m 100m 1 10 RL = 16 W, Gain = 6.1 dB, fIN = 1 kHz, 1 BTL VDD = 2.5 V VDD = 3 V 0.1 VDD = 3.6 V VDD = 5 V 0.01 0.001 100m 1m 10m 100m 1 2 THD+N - Total Harmonic Distortion + Noise - % Figure 3. THD+N - Total Harmonic Distortion + Noise - % THD+N - Total Harmonic Distortion + Noise - % In Phase Out of Phase 0.001 100m TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER THD+N - Total Harmonic Distortion + Noise - % 10 TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER THD+N - Total Harmonic Distortion + Noise - % THD+N - Total Harmonic Distortion + Noise - % TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 10 RL = 32 W, VDD = 5 V Gain = 6.1 dB, fIN = 1 kHz, 1 BTL VDD = 3.6 V VDD = 2.5 V 0.1 VDD = 3 V 0.01 0.001 100m 1m 10m 100m PO - Output Power - W PO - Output Power - W PO - Output Power - W Figure 6. Figure 7. Figure 8. 1 2 7 Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): TPA6130A2 TPA6130A2 www.ti.com SLOS488B – NOVEMBER 2006 – REVISED FEBRUARY 2008 RL = 16 W, VDD = 2.5 V, Gain = 0.1 dB, Stereo 0.1 PO = 20 mW PO = 1 mW 0.01 PO = 4 mW 0.001 20 100 1k 10k 20k 100 RL = 16 W, VDD = 3 V, 10 Gain = 0.1 dB, Stereo 1 PO = 40 mW PO = 20 mW 0.1 PO = 5 mW 0.01 0.001 20 100 RL = 16 W, VDD = 3.6 V, Gain = 0.1 dB, Stereo 0.1 PO = 70 mW PO = 35 mW 0.01 PO = 5 mW 0.001 20 100 1k f - Frequency - Hz 10k 20k Figure 11. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 1 RL = 16 W, VDD = 5 V, Gain = 0.1 dB, Stereo 0.1 PO = 50 mW PO = 80 mW 0.01 PO = 5 mW 0.001 20 100 1k f - Frequency - Hz 10k 20k 1 RL = 32 W, VDD = 2.5 V, Gain = 0.1 dB, Stereo 0.1 PO = 20 mW PO = 1 mW 0.01 PO = 4 mW 0.001 20 100 1k f - Frequency - Hz 10k 20k THD+N - Total Harmonic Distortion + Noise - % Figure 10. THD+N - Total Harmonic Distortion + Noise - % Figure 9. 1 RL = 32 W, VDD = 3 V, Gain = 0.1 dB, Stereo 0.1 PO = 20 mW PO = 40 mW 0.01 PO = 5 mW 0.001 20 100 1k f - Frequency - Hz 10k 20k Figure 13. Figure 14. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 1 RL = 32 W, VDD = 3.6 V, Gain = 0.1 dB, Stereo PO = 35 mW 0.1 PO = 70 mW 0.01 PO = 5 mW 0.001 20 100 1k f - Frequency - Hz Figure 15. 10k 20k 1 RL = 32 W, VDD = 5 V, Gain = 0.1 dB, Stereo 0.1 PO = 50 mW PO = 70 mW 0.01 PO = 5 mW 0.001 20 100 1k f - Frequency - Hz 10k 20k Figure 16. 8 THD+N - Total Harmonic Distortion + Noise - % Figure 12. THD+N - Total Harmonic Distortion + Noise - % THD+N - Total Harmonic Distortion + Noise - % 10k 20k 1 f - Frequency - Hz f - Frequency - Hz THD+N - Total Harmonic Distortion + Noise - % 1k TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY THD+N - Total Harmonic Distortion + Noise - % 1 TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY THD+N - Total Harmonic Distortion + Noise - % THD+N - Total Harmonic Distortion + Noise - % TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 1 RL = 16 W, VDD = 2.5 V, Gain = 6.1 dB, BTL 0.1 PO = 100 mW PO = 5 mW 0.01 PO = 25 mW 0.001 20 100 1k f - Frequency - Hz 10k 20k Figure 17. Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): TPA6130A2 TPA6130A2 www.ti.com SLOS488B – NOVEMBER 2006 – REVISED FEBRUARY 2008 VDD = 3.6 V, Gain = 6.1 dB, BTL 0.1 PO = 200 mW PO = 25 mW 0.01 0.001 20 PO = 100 mW 100 1k f - Frequency - Hz 10k 20k 1 RL = 16 W, VDD = 5 V, Gain = 6.1 dB, BTL 0.1 PO = 200 mW PO = 100 mW 0.001 20 100 1k f - Frequency - Hz 10k 20k 1 RL = 32 W, VDD = 2.5 V, Gain = 6.1 dB, BTL 0.1 PO = 100 mW PO = 5 mW 0.01 PO = 25 mW 0.001 20 100 1k f - Frequency - Hz 10k 20k Figure 18. Figure 19. Figure 20. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY SUPPLY VOLTAGE REJECTION RATIO vs FREQUENCY RL = 32 W, VDD = 3.6 V, Gain = 6.1 dB, BTL 0.1 PO = 200 mW PO = 25 mW 0.01 0.001 20 PO = 100 mW 100 1k f - Frequency - Hz 10k 20k 1 0 RL = 32 W, VDD = 5 V, Gain = 6.1 dB, BTL 0.1 PO = 200 mW PO = 25 mW 0.01 0.001 20 PO = 100 mW 100 1k f - Frequency - Hz kSVR - Supply Voltage Rejection Ratio - V 1 RL = 16 W, -20 -40 -60 VDD = 3.6 V VDD = 2.5 V -80 -100 -120 20 10k 20k Gain = 0.1 dB, Cp = 1 mF, Stereo VDD = 5 V 100 1k 10k 20k f - Frequency - Hz Figure 21. Figure 22. Figure 23. SUPPLY VOLTAGE REJECTION RATIO vs FREQUENCY SUPPLY VOLTAGE REJECTION RATIO vs FREQUENCY COMMON MODE REJECTION RATIO vs FREQUENCY -20 Gain = 0.1 dB, Cp = 1 mF, Stereo -40 VDD = 3.6 V -60 VDD = 2.5 V -80 -100 -120 20 VDD = 5 V 100 1k 10k 20k f - Frequency - Hz Figure 24. CMRR - Common-Mode Rejection Ratio - dB 0 RL = 32 W, kSVR - Supply Voltage Rejection Ratio - V 0 kSVR - Supply Voltage Rejection Ratio - V PO = 25 mW 0.01 TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY THD+N - Total Harmonic Distortion + Noise - % RL = 16 W, THD+N - Total Harmonic Distortion + Noise - % 1 TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY THD+N - Total Harmonic Distortion + Noise - % THD+N - Total Harmonic Distortion + Noise - % THD+N - Total Harmonic Distortion + Noise - % TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY RL = 16 W, -20 Gain = 6.1 dB, Cp = 1 mF, BTL -40 -60 -80 VDD = 2.5 V VDD = 3.6 V -100 -120 20 VDD = 5 V 100 1k 10k 20k f - Frequency - Hz Figure 25. 0 -10 -20 RL = 16 W, Gain = 0.1 dB, CI = 2.2 mF, Stereo -30 -40 -50 -60 VDD = 2.5 V VDD = 3.6 V -70 -80 20 VDD = 5 V 100 1k 10k 20k f - Frequency - Hz Figure 26. 9 Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): TPA6130A2 TPA6130A2 www.ti.com SLOS488B – NOVEMBER 2006 – REVISED FEBRUARY 2008 OUTPUT POWER vs LOAD 0 OUTPUT POWER vs LOAD 250 500 RL = 16 W, Gain = 6.1 dB, CI = 2.2 mF, -20 200 BTL -30 -40 -50 VDD = 2.5 V -60 fIN = 1 kHz, Gain = 0.1 dB, THD+N = 1%, Stereo VDD = 5 V VDD = 3.6 V 400 PO - Output Power - mW -10 PO - Output Power - mW CMRR - Common-Mode Rejection Ratio - dB COMMON MODE REJECTION RATIO vs FREQUENCY 150 100 VDD = 3.6 V 50 -70 -80 20 100 1k 300 200 VDD = 3.6 V 100 VDD = 2.5 V VDD = 2.5 V VDD = 5 V 0 10 10k 20k 0 10 1k 100 f - Frequency - Hz Load - W Figure 27. Figure 28. Figure 29. OUTPUT VOLTAGE vs LOAD OUTPUT VOLTAGE vs LOAD POWER DISSIPATION vs OUTPUT POWER 6 1 13 RL = 16 W, 4.5 4 VDD = 2.5 V 3 VDD = 3.6 V THD + N = 1% Gain = 0.1 dB, fIN = 1 kHz, 2 VDD = 5 V 9 7 VDD = 3.6 V 5 VDD = 2.5 V THD + N = 1% Gain = 6.1 dB, fIN = 1 kHz, 3 Stereo 1.5 PD - Power Dissipation - W 11 5 VO - Output Voltage - VPP VO - Output Voltage - VPP VDD = 5 V 2.5 Gain = 0.1 dB, Stereo 0.8 VDD = 5 V 0.6 0.4 VDD = 3.6 V 0.2 VDD = 2.5 V BTL 1 10 1k 100 Load - W 5.5 3.5 fIN = 1 kHz, Gain = 6.1 dB, THD+N = 1%, BTL VDD = 5 V 100 1 10 1000 0 100 Load - W Load - W Figure 30. 1000 0 50 100 150 200 250 300 350 400 PO - Output Power - mW Figure 31. Figure 32. DIFFERENTIAL INPUT IMPEDANCE vs GAIN Differential Input Impedance - kW 100 90 80 70 60 50 40 VDD = 3.6 V 30 -60 -50 -40 -30 -20 -10 0 10 Gain - dB Figure 33. 10 Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): TPA6130A2 TPA6130A2 www.ti.com SLOS488B – NOVEMBER 2006 – REVISED FEBRUARY 2008 1 Output SWS Disable 0.75 Voltage - V 0.5 0.25 0 -0.25 -0.5 -0.75 -1 0 200m 400m 600m 800m 1m 1.2m 1.4m 1.6m 1.8m 2m 7m 8m 9m 10m t - Time - s Figure 34. Shutdown Time 1 Output 0.75 SWS Enable Voltage - V 0.5 0.25 0 -0.25 -0.5 -0.75 -1 0 1m 2m 3m 4m 5m 6m t - Time - s Figure 35. Startup Time 11 Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): TPA6130A2 TPA6130A2 www.ti.com SLOS488B – NOVEMBER 2006 – REVISED FEBRUARY 2008 APPLICATION INFORMATION SIMPLIFIED APPLICATIONS CIRCUIT VDD CPM CPP VDD 20 19 CPVSS 1 mF GND 1 mF 18 17 16 LEFTINM 0.47 mF 1 15 2 14 LEFTINP 0.47 mF 1 mF GND 13 TPA6130A2 3 CPVSS HPLEFT GND VDD 5 11 SD SD 8 9 HPRIGHT 1 mF 10 GND 7 GND 6 SCL 0.47 mF VDD SCL RIGHTINM 12 SDA 0.47 mF 4 SDA RIGHTINP Headphone Amplifiers Single-supply headphone amplifiers typically require dc-blocking capacitors. The capacitors are required because most headphone amplifiers have a dc bias on the outputs pin. If the dc bias is not removed, the output signal is severely clipped, and large amounts of dc current rush through the headphones, potentially damaging them. The top drawing in Figure 36 illustrates the conventional headphone amplifier connection to the headphone jack and output signal. DC blocking capacitors are often large in value. The headphone speakers (typical resistive values of 16 Ω or 32 Ω) combine with the dc blocking capacitors to form a high-pass filter. Equation 1 shows the relationship between the load impedance (RL), the capacitor (CO), and the cutoff frequency (fC). 1 fc + 2pRLC O (1) CO can be determined using Equation 2, where the load impedance and the cutoff frequency are known. 1 CO + 2pRLf c (2) If fc is low, the capacitor must then have a large value because the load resistance is small. Large capacitance values require large package sizes. Large package sizes consume PCB area, stand high above the PCB, increase cost of assembly, and can reduce the fidelity of the audio output signal. Two different headphone amplifier applications are available that allow for the removal of the output dc blocking capacitors. The Capless amplifier architecture is implemented in the same manner as the conventional amplifier with the exception of the headphone jack shield pin. This amplifier provides a reference voltage, which is 12 Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): TPA6130A2 TPA6130A2 www.ti.com SLOS488B – NOVEMBER 2006 – REVISED FEBRUARY 2008 connected to the headphone jack shield pin. This is the voltage on which the audio output signals are centered. This voltage reference is half of the amplifier power supply to allow symmetrical swing of the output voltages. Do not connect the shield to any GND reference or large currents will result. The scenario can happen if, for example, an accessory other than a floating GND headphone is plugged into the headphone connector. See the second block diagram and waveform in Figure 36. Conventional VDD CO VOUT CO VDD/2 GND Capless VDD VOUT VBIAS GND VBIAS DirectPathTM VDD GND VSS Figure 36. Amplifier Applications The DirectPath™ amplifier architecture operates from a single supply but makes use of an internal charge pump to provide a negative voltage rail. Combining the user provided positive rail and the negative rail generated by the IC, the device operates in what is effectively a split supply mode. The output voltages are now centered at zero volts with the capability to swing to the positive rail or negative rail. The DirectPath™ amplifier requires no output dc blocking capacitors, and does not place any voltage on the sleeve. The bottom block diagram and waveform of Figure 36 illustrate the ground-referenced headphone architecture. This is the architecture of the TPA6130A2. Input-Blocking Capacitors DC input-blocking capacitors block the dc portion of the audio source, and allow the inputs to properly bias. Maximum performance is achieved when the inputs of the TPA6130A2 are properly biased. Performance issues such as pop are optimized with proper input capacitors. The dc input-blocking capacitors may be removed provided the inputs are connected differentially and within the input common mode range of the amplifier, the audio signal does not exceed ±3 V, and pop performance is sufficient. 13 Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): TPA6130A2 TPA6130A2 www.ti.com SLOS488B – NOVEMBER 2006 – REVISED FEBRUARY 2008 CIN is a theoretical capacitor used for mathematical calculations only. Its value is the series combination of the dc input-blocking capacitors, C(DCINPUT-BLOCKING). Use Equation 3 to determine the value of C(DCINPUT-BLOCKING). For example, if CIN is equal to 0.22 µF, then C(DCINPUT-BLOCKING) is equal to about 0.47 µF. 1 C CIN = (DCINPUT-BLOCKING) 2 (3) The two C(DCINPUT-BLOCKING) capacitors form a high-pass filter with the input impedance of the TPA6130A2. Use Equation 3 to calculate CIN, then calculate the cutoff frequency using CIN and the differential input impedance of the TPA6130A2, RIN, using Equation 4. Note that the differential input impedance changes with gain. See Figure 33 for input impedance values. The frequency and/or capacitance can be determined when one of the two values are given. 1 1 fc IN + or C IN + 2p fc R 2p RIN C IN IN IN (4) If a high pass filter with a -3 dB point of no more than 20 Hz is desired over all gain settings, the minimum impedance would be used in the above equation. Figure 33 shows this to be 37 kΩ. The capacitor value by the above equation would be 0.215 µF. However, this is CIN, and the desired value is for C(DCINPUT-BLOCKING). Multiplying CIN by 2 yields 0.43 µF, which is close to the standard capacitor value of 0.47 µF. Place 0.47 µF capacitors at each input terminal of the TPA6130A2 to complete the filter. Charge Pump Flying Capacitor and CPVSS Capacitor The charge pump flying capacitor serves to transfer charge during the generation of the negative supply voltage. The CPVSS capacitor must be at least equal to the flying capacitor in order to allow maximum charge transfer. Low ESR capacitors are an ideal selection, and a value of 1 µF is typical. Decoupling Capacitors The TPA6130A2 is a DirectPath™ headphone amplifier that requires adequate power supply decoupling to ensure that the noise and total harmonic distortion (THD) are low. Use good low equivalent-series-resistance (ESR) ceramic capacitors, typically 1.0 µF. Find the smallest package possible, and place as close as possible to the device VDD lead. Placing the decoupling capacitors close to the TPA6130A2 is important for the performance of the amplifier. Use a 10 µF or greater capacitor near the TPA6130A2 to filter lower frequency noise signals. The high PSRR of the TPA6130A2 will make the 10 µF capacitor unnecessary in most applications. Layout Recommendations Exposed Pad On TPA6130A2RTJ Package Option Solder the exposed metal pad on the TPA6130A2RTJ QFN package to the a pad on the PCB. The pad on the PCB may be grounded or may be allowed to float (not be connected to ground or power). If the pad is grounded, it must be connected to the same ground as the GND pins (3, 9, 10, 13, and 19). See the layout and mechanical drawings at the end of the datasheet for proper sizing. Soldering the thermal pad improves mechanical reliability, improves grounding of the device, and enhances thermal conductivity of the package. GND Connections The GND pin for charge pump should be decoupled to the charge pump VDD pin, and the GND pin adjacent to the Analog VDD pin should be separately decoupled to each other. I2C CONTROL INTERFACE DETAILS Addressing the TPA6130A2 The device operates only as a slave device whose address is 1100000 binary. 14 Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): TPA6130A2 TPA6130A2 www.ti.com SLOS488B – NOVEMBER 2006 – REVISED FEBRUARY 2008 GENERAL I2C OPERATION The I2C bus employs two signals; SDA (data) and SCL (clock), to communicate between integrated circuits in a system. Data is transferred on the bus serially, one bit at a time. The address and data are transferred in byte (8-bit) format with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data terminal (SDA) while the clock is high to indicate start and stop conditions. A high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data-bit transitions must occur within the low time of the clock period. These conditions are shown in Figure 37. The master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another device and then wait for an acknowledge condition. The TPA6130A2 holds SDA low during acknowledge clock period to indicate an acknowledgment. When this occurs, the master transmits the next byte of the sequence. Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the same signals via a bidirectional bus using a wired-AND connection. An external pull-up resistor must be used for the SDA and SCL signals to set the HIGH level for the bus. When the bus level is 5 V, pull-up resistors between 1 kΩ and 2 kΩ in value must be used. 8- Bit Data for Register (N) 8- Bit Data for Register (N+1) Figure 37. Typical I2C Sequence There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is shown in Figure 37. SINGLE-AND MULTIPLE-BYTE TRANSFERS The serial control interface supports both single-byte and multi-byte read/write operations for all registers. During multiple-byte read operations, the TPA6130A2 responds with data, a byte at a time, starting at the register assigned, as long as the master device continues to respond with acknowledges. The TPA6130A2 supports sequential I2C addressing. For write transactions, if a register is issued followed by data for that register and all the remaining registers that follow, a sequential I2C write transaction has taken place. For I2C sequential write transactions, the register issued then serves as the starting point, and the amount of data subsequently transmitted, before a stop or start is transmitted, determines to how many registers are written. SINGLE-BYTE WRITE As shown in Figure 38, a single-byte data write transfer begins with the master device transmitting a start condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of the data transfer. For a write data transfer, the read/write bit must be set to 0. After receiving the correct I2C device address and the read/write bit, the TPA6130A2 responds with an acknowledge bit. Next, the master transmits the register byte corresponding to the TPA6130A2 internal memory address being accessed. After receiving the register byte, the TPA6130A2 again responds with an acknowledge bit. Next, the master device transmits the data byte to be written to the memory address being accessed. After receiving the data byte, the TPA6130A2 again responds with an acknowledge bit. Finally, the master device transmits a stop condition to complete the single-byte data write transfer. 15 Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): TPA6130A2 TPA6130A2 www.ti.com SLOS488B – NOVEMBER 2006 – REVISED FEBRUARY 2008 Start Condition Acknowledge A6 A5 A4 A3 A2 A1 A0 Acknowledge R/W ACK A7 A6 A5 I2C Device Address and Read/Write Bit A4 A3 A2 A1 Acknowledge A0 ACK D7 D6 D5 Register D4 D3 D2 D1 D0 ACK Stop Condition Data Byte Figure 38. Single-Byte Write Transfer MULTIPLE-BYTE WRITE AND INCREMENTAL MULTIPLE-BYTE WRITE A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes are transmitted by the master device to the TPA6130A2 as shown in Figure 39. After receiving each data byte, the TPA6130A2 responds with an acknowledge bit. Register Figure 39. Multiple-Byte Write Transfer SINGLE-BYTE READ As shown in Figure 40, a single-byte data read transfer begins with the master device transmitting a start condition followed by the I2C device address and the read/write bit. For the data read transfer, both a write followed by a read are actually done. Initially, a write is done to transfer the address byte of the internal memory address to be read. As a result, the read/write bit is set to a 0. After receiving the TPA6130A2 address and the read/write bit, the TPA6130A2 responds with an acknowledge bit. The master then sends the internal memory address byte, after which the TPA6130A2 issues an acknowledge bit. The master device transmits another start condition followed by the TPA6130A2 address and the read/write bit again. This time the read/write bit is set to 1, indicating a read transfer. Next, the TPA6130A2 transmits the data byte from the memory address being read. After receiving the data byte, the master device transmits a not-acknowledge followed by a stop condition to complete the single-byte data read transfer. Repeat Start Condition Start Condition Acknowledge A6 A5 A1 A0 R/W ACK A7 I2C Device Address and Read/Write Bit Acknowledge A6 A5 A4 Register A0 ACK Not Acknowledge Acknowledge A6 A5 A1 A0 R/W ACK D7 I2C Device Address and Read/Write Bit D6 D1 Data Byte D0 ACK Stop Condition Figure 40. Single-Byte Read Transfer MULTIPLE-BYTE READ A multiple-byte data read transfer is identical to a single-byte data read transfer except that multiple data bytes are transmitted by the TPA6130A2 to the master device as shown in Figure 41. With the exception of the last data byte, the master device responds with an acknowledge bit after receiving each data byte. 16 Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): TPA6130A2 TPA6130A2 www.ti.com SLOS488B – NOVEMBER 2006 – REVISED FEBRUARY 2008 Repeat Start Condition Start Condition Acknowledge A6 A0 R/W ACK A7 Acknowledge A6 I2C Device Address and Read/Write Bit A5 A0 ACK Acknowledge A6 A0 R/W ACK D7 I2C Device Address and Read/Write Bit Register Acknowledge D0 ACK D7 First Data Byte Acknowledge Not Acknowledge D0 ACK D7 D0 ACK Stop Condition Last Data Byte Other Data Bytes Figure 41. Multiple-Byte Read Transfer Register Map Table 1. Register Map Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1 HP_EN_L HP_EN_R Mode[1] Mode[0] Reserved Reserved Thermal SWS 2 Mute_L Mute_R Volume[5] Volume[4] Volume[3] Volume[2] Volume[1] Volume[0] 3 Reserved Reserved Reserved Reserved Reserved Reserved HiZ_L HiZ_R 4 Reserved Reserved RFT RFT Version[3] Version[2] Version[1] Version[0] 5 RFT RFT RFT RFT RFT RFT RFT RFT 6 RFT RFT RFT RFT RFT RFT RFT RFT 7 RFT RFT RFT RFT RFT RFT RFT RFT 8 RFT RFT RFT RFT RFT RFT RFT RFT Bits labeled "Reserved" are reserved for future enhancements. They may not be written to. When read, they will show a "0" value. Bits labeled "RFT" are reserved for TI testing. Under no circumstances must any data be written to these registers. Writing to these bits may change the function of the device, or cause complete failure. If read, these bits may assume any value. Control Register (Address: 1) BIT 7 6 5 4 3 2 1 0 Function HP_EN_L HP_EN_R Mode[1] Mode[0] Reserved Reserved Thermal SWS Reset Value 0 0 0 0 0 0 0 0 HP_EN_L Enable bit for the left-channel amplifier. Amplifier is active when bit is high. HP_EN_R Enable bit for the right-channel amplifier. Amplifier is active when bit is high. Mode[1:0] Mode bits Mode[1] and Mode[0] select one of three modes of operation. 00 is stereo headphone mode. 01 is dual mono headphone mode. 10 is bridge-tied load mode. Reserved These bits are reserved for future enhancements. They may not be written to. When read they will read as zero. Thermal A 1 on this bit indicates a thermal shutdown was initiated by the hardware. When the temperature drops to safe levels, the device will start to operate again, regardless of bit status. This bit is clear-on-read. SWS Software shutdown control. When the bit is one, the device is in software shutdown. When the bit is low, the charge-pump is active. SWS must be low for normal operation. 17 Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): TPA6130A2 TPA6130A2 www.ti.com SLOS488B – NOVEMBER 2006 – REVISED FEBRUARY 2008 Volume and Mute Register (Address: 2) BIT 7 6 5 4 3 2 1 0 Function Mute_L Mute_R Volume[5] Volume[4] Volume[3] Volume[2] Volume[1] Volume[0] Reset Value 1 1 0 0 0 0 0 0 Mute_L Left channel mute. If this bit is High the left channel is muted. Mute_R Right channel mute. If this bit is High the right channel is muted. Volume[5:0] Six bits for volume control. 111111 indicates the highest gain and 000000 indicates the lowest gain. Output Impedance Register (Address: 3) BIT 7 6 5 4 3 2 1 0 Function Reserved Reserved Reserved Reserved Reserved Reserved HiZ_L HiZ_R Reset Value 0 0 0 0 0 0 0 0 Reserved These bits are reserved for future enhancements. They may not be written to. When read they will read as zero. All writes to these bits will be ignored. HiZ_L Puts left-channel amplifier output in tri-state high impedance mode. HiZ_R Puts right-channel amplifier output in tri-state high impedance mode. I2C address and Version Register (Address: 4) BIT 7 6 5 4 3 2 1 0 Function Reserved Reserved RFT RFT Version[3] Version[2] Version[1] Version[0] Reset Value 0 0 0 0 0 0 0 0 Reserved These bits are reserved for future enhancements. They may not be written to. When read they will read as zero. Version[3:0] The version bits track the revision of the silicon. Valid values are 0010 for released TPA6130A2. RFT Reserved for Test. Do NOT write to these registers. Reserved for test registers (Addresses: 5-8) BIT 7 6 5 4 3 2 1 0 Function RFT RFT RFT RFT RFT RFT RFT RFT Reset Value x x x x x x x x RFT Reserved for Test. Do NOT write to these registers. 18 Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): TPA6130A2 TPA6130A2 www.ti.com SLOS488B – NOVEMBER 2006 – REVISED FEBRUARY 2008 Modes of Operation The TPA6130A2 supports numerous modes of operation. Hardware Shutdown Hardware shutdown occurs when the SD pin is set to logic 0. The device is completely shutdown in this mode, drawing minimal current. This mode overrides all other modes. All information programmed into the registers is lost. When the device starts up again, the registers go back to their default state. Software Shutdown Software shutdown is set by placing a logic 1 in register 1, bit 0. That is the SWS bit. The software shutdown places the device in a low power state, although the current draw is higher than that of hardware shutdown (see the Electrical Characteristics Table for values). Engaging software shutdown turns off the charge pump and disables the outputs. The device is awakened by placing a logic 0 in the SWS bit. Note that when the device is in SWS mode, register 1, bits 7 and 6 will be cleared to reflect the disabled state of the amplifier. All other registers maintain their values. Re-enable the amplifer by placing a logic 0 in the SWS bit. It is necessary to reset the entire register because a full word must be used when writing just one bit. Charge Pump Enabled, HP Amplifiers Disabled The output amplifiers of the TPA6130A2 are enabled by placing a logic 1 in register 1, bits 6 and 7. Place a logic 0 in register 1, bits 6 and 7 to disable the output amplifiers. The left and right outputs can be enabled and disabled individually. When the output amplifiers are disabled, the charge-pump remains on. HiZ State HiZ is enabled by placing a logic 1 in register 3, bits 0 and 1. Place a logic 0 in register 3, bits 0 and 1 to disable the HiZ state of the outputs. The left and right outputs can be placed into a HiZ state individually. The HiZ state puts the outputs into a state of high impedance. Use this configuration when the outputs of the TPA6130A2 share traces with other devices whose outputs may be active. Note that to use the HiZ mode, the TPA6130A2 MUST be active (not in SWS or hardware shutdown). Furthermore, the output amplifiers must NOT be enabled. Stereo Headphone Drive The device is in this mode when the MODE bits in register 1 are 00 and both headphone enable bits are enabled. The two amplifier channels operate independently. This mode is appropriate for stereo playback. Dual Mono Headphone Drive The device is in this mode when the MODE bits in register 1 are 01 and both headphone enable bits are enabled. The left channel is the active input. It is amplified and distributed to both the left and right headphone outputs. Bridge-Tied Load Receiver Drive The device is in this mode when the MODE bits in register 1 are 10 and both headphone enable bits are enabled. In this mode, the device will take the left channel input and drive a single load connected between HPLEFT and HPRIGHT in a bridge-tied fashion. The minimum load for bridge-tied mode is the same as for stereo mode (see table entitled "Absolute Maximum Ratings"). 19 Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): TPA6130A2 TPA6130A2 www.ti.com SLOS488B – NOVEMBER 2006 – REVISED FEBRUARY 2008 Default Mode The TPA6130A2 starts up with the following conditions: • SWS = Off, CHARGE PUMP = On • HP ENABLES = Off • HiZ = Off • MODE = Stereo • HP MUTES = On, VOLUME = -59.5 dB, VOLUME CONTROL The TPA6130A2 volume control is set through the I2C interface. The six volume control register bits are decoded to 64 volume settings that employ an audio taper. See Table 2 for the gain table. The values listed in this table are typical. Each gain step has a different input impedance. See Figure 33. Table 2. Audio Taper Gain Values Gain Control Word (Binary) Mute [7:6], V[5:0] Nominal Gain (dB) Nominal Gain (V/V) Gain Control Word (Binary) Mute [7:6], V[5:0] Nominal Gain (dB) Nominal Gain (V/V) 11XXXXXX –100 0.00001 00100000 –10.9 0.283 00000000 –59.5 0.001 00100001 –10.3 0.305 00000001 –53.5 0.002 00100010 –9.7 0.329 00000010 –50.0 0.003 00100011 –9.0 0.353 00000011 –47.5 0.004 00100100 –8.5 0.379 00000100 –45.5 0.005 00100101 –7.8 0.405 00000101 –43.9 0.007 00100110 –7.2 0.433 00000110 –41.4 0.009 00100111 –6.7 0.462 00000111 –39.5 0.012 00101000 –6.1 0.493 00001000 –36.5 0.015 00101001 –5.6 0.524 00001001 –35.3 0.018 00101010 –5.1 0.557 00001010 –33.3 0.022 00101011 –4.5 0.591 00001011 –31.7 0.026 00101100 –4.1 0.627 00001100 –30.4 0.031 00101101 –3.5 0.664 00001101 –28.6 0.037 00101110 –3.1 0.702 00001110 –27.1 0.043 00101111 –2.6 0.742 00001111 –26.3 0.050 00110000 –2.1 0.783 00010000 –24.7 0.057 00110001 –1.7 0.825 00010001 –23.7 0.065 00110010 –1.2 0.870 00010010 –22.5 0.074 00110011 –0.8 0.915 00010011 –21.7 0.084 00110100 –0.3 0.962 00010100 –20.5 0.093 00110101 0.1 1.010 00010101 –19.6 0.104 00110110 0.5 1.061 00010110 –18.8 0.116 00110111 0.9 1.112 00010111 –17.8 0.129 00111000 1.4 1.165 00011000 –17.0 0.142 00111001 1.7 1.220 00011001 –16.2 0.156 00111010 2.1 1.277 00011010 –15.2 0.172 00111011 2.5 1.335 00011011 –14.5 0.188 00111100 2.9 1.395 00011100 –13.7 0.205 00111101 3.3 1.456 00011101 –13.0 0.223 00111110 3.6 1.520 00011110 –12.3 0.242 00111111 4.0 1.585 00011111 –11.6 0.262 20 Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): TPA6130A2 PACKAGE OPTION ADDENDUM www.ti.com 16-Apr-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPA6130A2RTJR ACTIVE QFN RTJ 20 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPA6130A2RTJRG4 ACTIVE QFN RTJ 20 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPA6130A2RTJT ACTIVE QFN RTJ 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPA6130A2RTJTG4 ACTIVE QFN RTJ 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPA6130A2YZHR ACTIVE DSBGA YZH 16 3000 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM TPA6130A2YZHT ACTIVE DSBGA YZH 16 250 Call TI Level-1-260C-UNLIM Green (RoHS & no Sb/Br) Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Mar-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPA6130A2RTJR Package Package Pins Type Drawing QFN RTJ 20 SPQ Reel Reel Diameter Width (mm) W1 (mm) 3000 330.0 12.4 A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 4.3 4.3 1.5 8.0 12.0 Q2 TPA6130A2RTJT QFN RTJ 20 250 180.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2 TPA6130A2YZHR DSBGA YZH 16 3000 180.0 8.4 2.07 2.07 0.81 4.0 8.0 Q1 TPA6130A2YZHR DSBGA YZH 16 3000 180.0 8.4 2.07 2.07 0.81 4.0 8.0 Q1 TPA6130A2YZHR DSBGA YZH 16 3000 180.0 8.4 2.07 2.07 0.81 4.0 8.0 Q1 TPA6130A2YZHT DSBGA YZH 16 250 180.0 8.4 2.07 2.07 0.81 4.0 8.0 Q1 TPA6130A2YZHT DSBGA YZH 16 250 180.0 8.4 2.07 2.07 0.81 4.0 8.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Mar-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPA6130A2RTJR QFN RTJ 20 3000 346.0 346.0 29.0 TPA6130A2RTJT QFN RTJ 20 250 190.5 212.7 31.8 TPA6130A2YZHR DSBGA YZH 16 3000 190.5 212.7 31.8 TPA6130A2YZHR DSBGA YZH 16 3000 190.5 212.7 31.8 TPA6130A2YZHR DSBGA YZH 16 3000 220.0 220.0 34.0 TPA6130A2YZHT DSBGA YZH 16 250 190.5 212.7 31.8 TPA6130A2YZHT DSBGA YZH 16 250 220.0 220.0 34.0 Pack Materials-Page 2 D: Max = 1964 µm, Min = 1904 µm E: Max = 1964 µm, Min = 1904 µm IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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