TRIQUINT AGR26180EF

Preliminary Data Sheet
May 2004
AGR26180EF
180 W, 2.535 GHz—2.655 GHz, N-Channel E-Mode, Lateral MOSFET
Introduction
The AGR26180EF is a high-voltage, gold-metalized,
enhancement mode, laterally diffused metal oxide
semiconductor (LDMOS) RF power transistor suitable for ultrahigh-frequency (UHF) applications,
including multichannel multipoint distribution service
(MMDS) for broadcasting and communications.
375D–03, STYLE 1
Figure 1. AGR26180EF Flanged Package
Features
Typical performance for MMDS systems.
f = 2600 MHz, IDQ = 1700 mA, Vds = 28 V,
adjacent channel BW = 3.84 MHz, 5 MHz offset;
alternate channel BW = 3.84 MHz, 10 MHz offset.
Typical P/A ratio of 9.8 dB at 0.01% (probability)
CCDF*:
— Output power: 27 W.
— Power gain: 12.5 dB.
— Efficiency: 20%.
— ACPR: –33 dBc.
— ACLR1: –35 dBc.
— Return loss: –12 dB.
Typical pulsed P1dB, 6 µs pulse at 10% duty: 185 W.
High-reliability, gold-metalization process.
Hot carrier injection (HCI) induced bias drift of <5%
over 20 years.
Internally matched.
High gain, efficiency, and linearity.
Integrated ESD protection.
Device can withstand a 10:1 voltage standing wave
ratio (VSWR) at 28 Vdc, 2600 MHz, 180 W output
power pulsed 4 µs at 10% duty.
Large signal impedance parameters available.
*The test signal utilized is 4-channel W-CDMA Test Model 1. This
test signal provides an equivalent reference (occupied bandwidth
and waveform EPF) for the actual performance with an MMDS
waveform.
Table 1. Thermal Characteristics
Parameter
Thermal Resistance,
Junction to Case
Sym
Value
Unit
Rı JC
0.35
°C/W
Table 2. Absolute Maximum Ratings*
Parameter
Drain-source Voltage
Gate-source Voltage
Total Dissipation at
TC = 25 °C
Derate Above 25 °C
Operating Junction
Temperature
Storage Temperature
Range
Sym
Value
65
VDSS
VGS –0.5, +15
PD
500
—
TJ
3
200
Unit
Vdc
Vdc
W
W/°C
°C
TSTG –65, +150
°C
* Stresses in excess of the absolute maximum ratings can cause
permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at
these or any other conditions in excess of those given in the
operational sections of the data sheet. Exposure to absolute
maximum ratings for extended periods can adversely affect
device reliability.
Table 3. ESD Rating*
AGR26180EF
HBM
MM
CDM
Minimum (V)
500
50
1000
Class
1B
A
4
* Although electrostatic discharge (ESD) protection circuitry has
been designed into this device, proper precautions must be
taken to avoid exposure to ESD and electrical overstress (EOS)
during all handling, assembly, and test operations. PEAK
Agere Devices
employs a human-body model (HBM), a machine model (MM),
and a charged-device model (CDM) qualification requirement in
order to determine ESD-susceptibility limits and protection
design evaluation. ESD voltage thresholds are dependent on the
circuit parameters used in each of the models, as defined by
JEDEC's JESD22-A114B (HBM), JESD22-A115A (MM), and
JESD22-C101A (CDM) standards.
Caution: MOS devices are susceptible to damage from electrostatic charge. Reasonable precautions in handling and packaging MOS devices should be
observed.
AGR26180EF
180 W, 2.535 GHz—2.655 GHz, N-Channel E-Mode, Lateral MOSFET
Preliminary Data Sheet
May 2004
Electrical Characteristics
Recommended operating conditions apply unless otherwise specified: TC = 30 °C.
Table 4. dc Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
V(BR)DSS
IGSS
IDSS
65
—
—
—
—
—
—
6
200
18
Vdc
µAdc
µAdc
GFS
—
2.8
3.0
—
12
3.4
3.7
0.08
—
4.0
4.6
—
S
Vdc
Vdc
Vdc
Off Characteristics
300 µA)
Drain-source Breakdown Voltage (VGS = 0, ID = 400
Gate-source Leakage Current (VGS = 5 V, VDS = 0 V)
Zero Gate Voltage Drain Leakage Current (VDS = 28 V, VGS = 0 V)
On Characteristics
Forward Transconductance (VDS = 10 V, ID = 1 A)
Gate Threshold Voltage (VDS = 10 V, ID = 600 µA)
Gate Quiescent Voltage (VDS = 28 V, ID = 2 x 850 mA)
Drain-source On-voltage (VGS = 10 V, ID = 1 A)
VGS(TH)
VGS(Q)
VDS(ON)
Table 5. RF Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
CRSS
—
4.0
—
pF
—
12.5
—
dB
IM3
—
–36
—
dBc
ACPR
—
–40
—
dBc
—
dB
Dynamic Characteristics
Reverse Transfer Capacitance
(VDS = 28 V, VGS = 0, f = 1.0 MHz)
(This part is internally matched on both the input and output.)
Test Fixture)
Functional Tests (in
(in Supplied
Agere Systems
Supplied Test Fixture)
Common-source Amplifier Power Gain*
Drain Efficiency*
Third-order Intermodulation Distortion*
(IM3 distortion measured over 3.84 MHz BW @ f1 – 10 MHz
and f2 + 10 MHz)
Adjacent Channel Power Ratio*
(ACPR measured over BW of 3.84 MHz @ f1 – 5 MHz
and f2 + 5 MHz)
Input Return Loss*
Power Output, 1 dB Compression Point, pulsed 4 µs at 10% duty.
(VDD = 28 V, fC = 2655.0 MHz, pulsed 6 µs at 10% duty)
Output Mismatch Stress
(VDD = 28 V, POUT = 180 W (pulsed 4 µs at 10% duty),
IDQ = 2 x 850 mA, fC = 2655.0 MHz VSWR = 10:1; [all phase angles])
GPS
η
IRL
P1dB
ψ
—
—
—
20
–12
185
—
—
%
W
No degradation in output
power.
* 3GPP W-CDMA, typical P/A ratio of 8.5 dB at 0.01% CCDF, f1 = 2645.0 MHz, and f2 = 2655 MHz. VDD = 28 Vdc, IDQ = 2 x 850 mA, and
POUT = 27 W average. Nominal operating voltage 28 Vdc.
Preliminary Data Sheet
May 2004
AGR26180EF
180 W, 2.535 GHz—2.655 GHz, N-Channel E-Mode, Lateral MOSFET
Test Circuit Illustrations for AGR26180EF
L1
VGG
R5
+
R3
Z1
C5
C1
Z3
IN
PINS:
1A. DRAIN
1B. DRAIN
2A. GATE
2B. GATE
3. SOURCE
R1
C9
C13
Z5
Z7
Z11
2B
C20
Z4 C10 Z6
VGG
2A
C19
Z2
R6
Z8
Z15
C7
C3
C17
Z19 C11 Z21
Z23
3 DUT
C2
OUT
Z20 C12 Z22
Z18
VDD
+
+
R4
Z24
1B
Z12
Z14
R2
C16
1A
Z10 Z12
L2
+
Z17
Z13
Z9
VDD
C14
C6
C15
C8
C4
C18
A. Schematic
Gate
Gnd
Drain
T2
T1
T5
C1
R3
C5
R5
R1L1
C13
C3
C16
C9
2A
C19
2B
C10 C20
3
R2 L2
C17
1A
C11
1B
C12
C15
R6
C7
OT1
C18
C8
C4
C14
C6
R4
C2
T3
T4
T6
Parts List:
■ Microstrip line: Z1, Z29 1.330 in. x 0.066 in.;
Z2, Z27 0.753 in. x 0.112 in.;
Z3 0.145 in. x 0.066 in.; Z4 1.578 in. x 0.066 in.;
Z5, Z6 0.160 in. x 0.066 in.;
Z7, Z8 0.172 in. x 0.066 in.;
Z9, Z10 0.134 in. x 0.171 in.;
Z11, Z12 0.320 in. x 0.600 in.;
Z13, Z14 0.856 in. x 0.043 in.;
Z15, Z16 0.155 in. x 0.645 in.;
Z17, Z18 0.217 in. x 0.750 in.;
Z19, Z20 0.473 in. x 0.088 in.;
Z21, Z22 0.026 in. x 0.293 in.;
Z23, Z24 0.194 in. x 0.066 in.;
Z25 1.718 in. x 0.066 in.; Z26 0.341 in. x 0.066 in.;
Z28 0.150 in. x 0.075 in.
®
■ ATC chip capacitor:
C9, C10, C11, C12: 4.7 pF 100B47_J500;
C3, C14, C15, C16: 5.6 pF 100B5R6J_500;
C19, C20: 0.7 pF 100A0R7J_500.
C27: 47 pF 100A470JW;
C28: 8.2 pF 100B8R2BW.
C4, C5: 12 pF 100B120JW;
®
■ Murata 50 V chip capacitor:
C3, C4: 4.7 µF, GRM55ER7H475KA01;
C5, C6: 2.2 µF, GRM43ER71H225KA01L;
C7, C8: 0.12 µF, LLL31MR71H124MD01.
■ AVX™ 35 V capacitor:
C1, C2, C17, C18: 15 µF TPSD156K035R0300.
■ 1206 size chip resistors:
R1, R2: 4.7 Ω; R3, R4: 560 kΩ; R5, R6 470 Ω.
®
■ Fair-Rite ferrite bead L1, L2: 2512067007Y3.
®
■ Taconic ORCER RF-35: board material,
1 oz. copper, 30 mil thickness, εr = 3.5.
B. Component Layout
Figure 2. Component Layout
AGR26180EF
180 W, 2.535 GHz—2.655 GHz, N-Channel E-Mode, Lateral MOSFET
Preliminary Data Sheet
May 2004
U CT
0.6
90
IN D
0.
8
10
0.1
0.4
20
50
20
10
5.0
4.0
3.0
2.0
1.8
1.6
1.4
1.2
50
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.2
0.2
20
0.4
0.1
)
/ Yo
(-jB
CE
1.
0
IV
CT
DU
IN
0
-110
5
0.38
0.37
0.1
0.11
-100
-70
0.
07
30
40
-1
-1
43
0.
8
0.0
2
0.4
0.4
1
0.4
0.39
F
0.12
9
0.0
(-j
06
Z
X/
2.
1.6
1.4
1.2
1.0
0.9
-90
0.13
0.6
1.8
-75
R
0.7
0.14
-80
0.36
-4
0.15
0.35
0
-4
0
-70
-5
6
4
0.8
5
-3
0.1
0.3
0
-12
5
3
-60
-5
0.3
7
VE
-60
0.1
CA P
AC
I TI
T
5
,O
o)
0.2
-30
32
CE
CO
M
0
-65 .5
18
0.
RE
AC
TA
N
EN
0.
0
-5
-25
0.
PO
N
4
0.
0.4
0.0
-20
31
0.
4
0.6
0
3.
0.3
5
0.4
0.8
-85
AN
PT
CE
US
ES
0
1.
4.0
0.2
19
0.
f1
f5
0
ZL
-4
4
0.
-15
f1
ZS
0.2
8
f5
0.2
2
0.3
0.2
9
0.2
1
-30
6
0.4
4
0.0
0
-15 -80
8
0.
5.0
0.2
-10
0.48
10
0.6
-20
D L OA D <
OW A R
7
HST
0.4
N GT
-170
EL E
V
WA
<Ð
-90
-160
Ð
RESISTANCE COMPONENT (R/Zo), OR CONDUCTANCE COMPONENT (G/Yo)
50
0.49
0.25
0.2
6
0.24
0.27
0.23
0.25
0.24
0.26
0.23
0.27
REFL ECTI ON COEFFI CI EN T I N D EG
REES
L E OF
ANG
I SSI ON COEFFI CI EN T I N
TRA N SM
D EGR
EES
L E OF
ANG
Z0 = 10 Ω
0.0 Ð > W A V EL E
N GTH
S TOW
A RD
0.0
0.49
0.48
± 180
170
Typical Performance Characteristics
MHz (f)
2500 (f1)
2550 (f2)
2600 (f3)
2650 (f4)
2700 (f5)
ZS Ω
(complex source impedance)
6.4 – j8.0
5.8 – j7.6
5.2 – j7.7
4.7 – j8.3
4.5 – j8.4
ZL Ω
(complex optimum load impedance)
3.0 – j7.8
2.9 – j7.0
2.7 – j6.2
2.6 – j5.5
2.5 – j4.7
ZS = Test circuit impedance as measured from gate to gate, balanced configuration.
ZL = Test circuit impedance as measured from drain to drain, balanced configuration.
+
BALANCED
INPUT
MATCHING
NETWORK
2A
1A
+
BALANCED
OUTPUT
MATCHING
NETWORK
3 DUT
– 2B
ZS
–
1B
ZL
PINS: 1A & 1B DRAIN, 2A & 2B GATE, 3 SOURCE
Figure 3. Series Equivalent Balanced Input and Output Impedances
Preliminary Data Sheet
May 2004
AGR26180EF
180 W, 2.535 GHz—2.655 GHz, N-Channel E-Mode, Lateral MOSFET
Typical Performance Characteristics (continued)
35
0
-10
Ƨ (%)
Ƨ (%), G PS (dB)Z
25
-20
IMD
20
-30
ACPR
15
-40
GPS
10
-50
5
0
ACPR (dBc), IM3 (dBc)Z
30
-60
1
-70
100
10
P OUT (W, AVERAGE)Z
Test conditions:
Two-carrier W-CDMA 3GPP, peak-to-average = 8.5 dB @ 0.01% CCDF, f1 = 2590 MHz, f2 = 2600 MHz, VDD = 28 V, IDQ = 1700 mA.
30
0
25
-8
Ƨ (%)
20
-16
RL (dB)
15
-24
GAIN (dB)
10
-32
IMD
5
-40
ACPR (dBc), IM3 (dBc), IRL (dB)Z
Ƨ (%), G PS (dB)Z
Figure 4. Power Gain, Drain Efficiency, ACPR, and IM3 vs. Output Power
ACP
0
2520
2550
2580
2610
2640
-48
2670
MHzZ
Test conditions:
Two-carrier W-CDMA 3GPP, peak-to-average = 8.5 dB @ 0.01% CCDF, f1 = 2590 MHz, f2 = 2600 MHz, VDD = 28 V, IDQ = 1700 mA, POUT = 27 W.
Figure 5. Power Gain, Drain Efficiency, ACPR, IM3, and IRL vs. Frequency
AGR26180EF
180 W, 2.535 GHz—2.655 GHz, N-Channel E-Mode, Lateral MOSFET
Preliminary Data Sheet
May 2004
Typical Performance Characteristics (continued)
60
14
50
GPS
GPS
13
40
5
0
5
0
12
30
5
11
20
0
Ƨ
10
10
Ƨ (%)
15
5
0
9
1
10
POUT (W)
0
1000
100
Test conditions:
28 VDS, IDQ = 1700 mA, 2600 MHz.
0
45
-10
40
Ƨ (%)
-20
IM3
-30
35
30
-40
IM5
25
-50
IM7
20
-60
15
-70
10
-80
5
-90
1
10
100
P OUT (W, PEP)Z
Test conditions:
Two-tone measurement @ 10 MHz tone spacing, VDD = 28 VDC, f1 = 2590 MHz, f2 = 2600 MHz.
Figure 7. IMD vs. POUT
0
1000
Ƨ (%)
IM3, IM5, AND IM7 (dBc)Z
Figure 6. Power Gain and Drain Efficiency vs. Output Power (CW signal data)
Preliminary Data Sheet
May 2004
AGR26180EF
180 W, 2.535 GHz—2.655 GHz, N-Channel E-Mode, Lateral MOSFET
Typical Performance Characteristics (continued)
0
-10
IM3 (dBc)Z
-20
-30
1300 mA
-40
-50
1700 mA
-60
-70
1500 mA
1
1900 mA
10
2100 mA
100
1000
POUT (W, PEP)Z
Test conditions:
Two-tone measurement @ 10 MHz tone spacing, VDD = 28 VDC, f1 = 2590 MHz, f2 = 2600 MHz.
Figure 8. IMD vs. Output Power and I DQ
14
13.5
2100 mA
GAIN (dB)Z
13
1900 mA
12.5
1700 mA
1500 mA
12
1300 mA
11.5
11
10.5
1
10
100
P OUT (W) Z
Figure 9. Power Gain vs. Output Power and IDQ
1000
AGR26180EF
180 W, 2.535 GHz—2.655 GHz, N-Channel E-Mode, Lateral MOSFET
Preliminary Data Sheet
May 2004
Typical Performance Characteristics (continued)
0
IMD (dBc)Z
-10
-20
-30
IM3
-40
IM5
-50
IM7
-60
0.1
1
10
TONE SEPARATION (MHz)Z
Test conditions:
Two-tone measurement @ POUT = 160 W (PEP).
Figure 10. IMD vs. Tone Separation
100
Preliminary Data Sheet
May 2004
AGR26180EF
180 W, 2.535 GHz—2.655 GHz, N-Channel E-Mode, Lateral MOSFET
Package Dimensions
All dimensions are in inches. Tolerances are ±0.005 in. unless specified.
1A
1B
PEAK DEVICES
AGR19K180U
AGR26180XF
XXXXX
YYWWLL XXXXX
ZZZZZZZ
2A
PINS:
1A. DRAIN
1B. DRAIN
2A. GATE
2B. GATE
3. SOURCE
3
2B
Label Notes:
■ M before the part number denotes model program. X before the part number denotes engineering prototype.
■
■
■
■
The last two letters of the part number denote wafer technology and package type.
YYWWLL is the date code including place of manufacture: year year work week (YYWW), LL = location (AL = Allentown, PA; T = Thailand).
XXXXX = five-digit wafer lot number.
ZZZZZZZ = seven-digit assembly lot number on production parts.
ZZZZZZZZZZZZ = 12-digit (five-digit lot, two-digit wafer, and five-digit serial number) on models and engineering prototypes.