ACS760ELF-20B
12 V High-Side Hot-Swap Hall Effect Based Current Monitor
Features and Benefits
Description
▪ Hall-effect current monitor—no external sense resistor required
▪ Analog output voltage (factory trimmed for gain and
offset) proportional to applied current
▪ External high-side FET gate drive
▪ 240V*A Power Fault Protection with user-programmable delay
▪ User programmable Overcurrent Fault Protection with
programmable delay
▪ 1.5 mΩ internal conductor resistance
▪ Short Circuit Protection isolates failed supply from
output in < 2 μs
▪ Active low Fault indicator output signal
▪ External FET failure detection with active low S1 Short
failure indicator output signal
▪ User controlled soft start / hot-swap function
▪ Logic enable input pin
▪ 10.8 to 13.2 V, single-supply operation
▪ 2 kV ESD protection for all pins
The ACS760 combines Allegro® Hall-effect current sense
technology with a hot-swap controller resulting in a more
efficient integrated controller for 12 V applications. By
eliminating the need for a shunt resistor, the I2R losses in the
power path are reduced.
When the ACS760 is externally enabled, and the voltage rail is
above the internal UVLO threshold, the internal charge pump
drives the gate of the external FET. When a fault is detected, the
gate is disabled while simultaneously alerting the application
that a fault has occurred.
The integrated protection in the ACS760 incorporates three
levels of fault protection, which includes a Power Fault with
user-programmable delay, a user-programmable Overcurrent
Fault threshold with programmable delay, and Short Circuit
protection, which disables the gate in less then 2 μs.
Additionally, in the event the external high-side FET fails
short, the ACS760 detects the S1 Short failure and immediately
disables the gate and alerts the host system. Unlike the three
protection faults, cycling the EN pin does not reset the S1 Short
failure. Power to the device must be cycled.
Package: 24 pin QSOP (suffix LF)
Approximate Scale
Typical Application
Backplane
IP
VS_IN
RV1
A
1
CIN
2
3
VS_RET
4
Enable
REN
5
CEN
6
7
VOUT
8
9
RSET
10
11
CG
COCD
12
IP+
IP–
IP+
IP–
IP+
IP–
IP+
IP–
ACS760
IP+
IP–
IP+
IP–
EN
VIOUT
ISET
CG
GATE
GND
FB–
FB+
OCDLY
S1SHORT
OPDLY
FAULT
24
23
22
S1
VLOAD
21
20
19
18
CLOAD
RG
17
3.3 V
16
15
C
14
13
COPD
A
B
C
760ELF20B-DS, Rev. 2
D1
B
RFB
RV1 is required only for inductive loads.
D1 should be a Schottky for inductive loads, to eliminate over-stress of the ACS760.
FB– is tied to GND at the point of load.
RS1
RFAULT
ACS760ELF-20B
12 V High-Side Hot-Swap Hall Effect Based Current Monitor
Selection Guide
Part Number
Package
Packing*
ACS760ELF-20BTR-T
QSOP24 surface mount
*Contact Allegro for additional packing options
2500 pieces/reel
Absolute Maximum Ratings
Characteristic
Rating
Units
VCC
24
V
GATE Drive Output Voltage*
VGATE
32
V
FB+ Forward Voltage*
VFB+
24
V
EN Forward Voltage*
VEN
32
V
All Other Pins Forward Voltage
VIN
8
V
Reverse DC Voltage, All Pins*
VR
–0.5
V
Forward Voltage, IPx pins*
Reverse Transient DC Voltage, All Pins*
Current Sense Output Current Source
Current Sense Output Current Sink
Symbol
Vr
10 μs pulse
IVIOUT(Source)
IVIOUT(Sink)
–5
V
1
mA
1
mA
–40 to 85
ºC
TJ(max)
165
ºC
Tstg
–65 to 170
ºC
Operating Ambient Temperature
TA
Maximum Junction Temperature
Storage Temperature
Notes
Range E
* With respect to GND.
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
2
ACS760ELF-20B
12 V High-Side Hot-Swap Hall Effect Based Current Monitor
Pin-out Diagram
IP+ 1
24 IP–
IP+ 2
23 IP–
IP+ 3
22 IP–
IP+ 4
21 IP–
IP+ 5
20 IP–
IP+ 6
19 IP–
EN 7
18 GATE
VIOUT 8
17 GND
ISET 9
16 FB–
CG 10
15 FB+
OCDLY 11
14 S1SHORT
OPDLY 12
13 FAULT
Terminal List Table
Number
1-6
7
Name
IP+
EN
8
VIOUT
9
ISET
10
CG
11
OCDLY
12
OPDLY
13
FAULT
14
S1SHORT
15
FB+
16
FB-
17
GND
18
GATE
19-24
IP–
Function
Primary sensed current conduction path input; power input pins: connected to VCC
Enable pin. Toggling this pin to the low state after a FAULT condition resets the ACS760.
Analog current sense output. Output voltage on this pin is proportional to the current flowing from the
IP+ pins to the IP– pins.
Terminal for RSET resistor. Sets Fault Current Threshold, IPF, via external resistor, RSET, connected
between this terminal and GND. Factory trimmed 100 μA current source flows out of this pin.
Terminal for CG capacitor. May be used to adjust the turn-on time and soft start control of an external
MOSFET, S1. Voltage on this pin limits inrush current through MOSFET S1. Set via external
capacitance, CG, connected between this pin and GND. This capacitor is charged by an internal 20 μA
current source.
Terminal for external capacitor, COCD, Used to adjust delay for overcurrent shutdown, set via the
external capactior, COCD, connected between this pin and GND.
Terminal for external capacitor, COPD, Used to adjust delay for overpower shutdown, set via the
external capactior, COPD, connected between this pin and GND.
Active low; output signal for short circuit and 240 V*A overload faults; does not trip for S1 short circuit
fault.
Active low; output signal for MOSFET S1 failure.
Input of positive feedback on output voltage. Used to determine 240 V*A threshold by difference
between FB+ and FB– pins.
Input of negative feedback on output voltage. Used to determine 240 V*A threshold by difference
between FB+ and FB– pins. Pulling the FB– pin to 3.3 V, and the OPDLY pin to GND, disables the
240 V*A power fault, which allows the ACS760 to operate purely in Current Mode.
Terminal for ground connection.
Terminal for external MOSFET, S1. Provides output voltage to drive S1. Current through S1 is
controlled at start-up by external capacitance connected between the CG pin and GND.
Primary sensed current conduction path output; power output pins.
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
3
ACS760ELF-20B
12 V High-Side Hot-Swap Hall Effect Based Current Monitor
Functional Block Diagram
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
4
ACS760ELF-20B
12 V High-Side Hot-Swap Hall Effect Based Current Monitor
OPERATING CHARACTERISTICS valid at VCC = 12 V, TA = 0°C to 85°C, unless otherwise noted
Characteristic
Symbol
Test Conditions
GENERAL ELECTRICAL CHARACTERISTICS
Linear Sensing Range
IP
Current flows from IP+ to IP- pins
Primary Conductor Resistance
RPRIMARY TA = 25°C
Supply Voltage
VCC
Voltage applied to IP+ pins
Supply Current
ICC
VUVLOH VCC rising and CG pin current source turns on, EN pin = high
Undervoltage Lockout (UVLO)
VUVLOL VCC falling and CG pin current source turns off, EN pin = high
tUVLOE Enabling, measured from rising VCC > VUVLOH to VGATE > 1 V
UVLO Delay to Chip Enable/ Disable
tUVLOD Disabling, from falling VCC < VUVLOL to VGATE < 1 V
FB+ to FB– Input Resistance
RFB
TA = 25°C
CURRENT SENSE PERFORMANCE CHARACTERISTICS
VIOUT Analog Output Propagation
TA = 25°C, IP = 0 →20 A, capacitance from VIOUT to GND
tPROP
Time
= 100 pF
VIOUT Analog Output 10-90% Rise
TA = 25°C, IP = 0 →20 A, capacitance from VIOUT to GND
tr
Time
= 100 pF
–3
dB, Ip = 10 A peak-to-peak, TA = 25°C, no external device
VIOUT Analog Signal Bandwidth1
f3dB
filter, capacitance from VIOUT to GND = 100 pF
TA = 25°C
Over full ambient operating temperature range
VIOUT Analog Signal Sensitivity
Sens
TA = 25°C
Over full ambient operating temperature range
VIOUT Analog Noise Level
VNOISE(PP) Mean peak-to-peak, TA = 25°C, 50 kHz external device filter
Over full ambient operating temperature range and linear
VIOUT Analog Nonlinearity
ELIN
sensing range
TA = 0 to 55°C
Zero Current Output Voltage
VIOUT(Q)
TA = 0 to 85°C
V
TA = 25°C
OL
Output Voltage Saturation Limits2
VOH
TA = 25°C
TA = 25°C, IP = 20 A
VIOUT Total Error % of IP
ETOT
TA = 0 to 85°C, IP = 20 A
VIOUT DC Output Resistance
RVIOUT IVIOUT = 1 mA
CURRENT FAULT PERFORMANCE CHARACTERISTICS
Load Power Fault Threshold
PF(th)
TA = 25°C, measured from FAULT signal to VGATE < 1 V,
tPFH
2.2 μF capacitance from OPDLY pin to GND, load step from
17 A to 23 A in 100 ns
240 V*A Fault Signal Delay
TA = 25°C, measured from FAULT signal to VGATE < 1 V,
tPFL
OPDLY pin open, load step from 17 A to 23 A in 100 ns
Over full operating ambient temperature range, external
240 V*A Fault Signal Delay Drift
∆tPF
capacitor with ±5% tolerance
Internal –3 dB Filter Frequency for FB+
fFBFILT TA = 25°C
and FB– Pins
IP Fault Switchpoint Tolerance3
EPF
Percentage error of IPF
Measured from FAULT signal to VGATE < 1 V, OCDLY pin
tIPFLmax
open, load step from 17 A to 45 A in 100 ns
4
IPF Fault Signal Delay
Measured from FAULT signal to VGATE < 1 V, 2.2 nF capacitIPFH
tance from OCDLY pin to GND, load step from 17 A to 45 A
in 100 ns
Min.
Typ.
Max.
Units
0
–
–
–
–
7.1
–
–
–
–
1.5
12
10
–
–
500
–
240
55
–
13.2
12
10.5
–
900
2
–
A
mΩ
V
mA
V
V
μs
μs
kΩ
–
2
–
μs
–
5
–
μs
–
50
–
kHz
–
63
–
5.275
–
65
–
5.416
–
20
–
67
–
5.558
–
mV/A
mV/A
mV/G
mV/G
mV
–
±0.5
±2.0
%
0.38
0.37
–
–
–
–
–
–
0.4
0.25
3.6
±1.0
–
1
0.42
0.43
–
–
–
±3.5
–
V
V
V
V
%
%
Ω
222
230
238
W
–
425
–
ms
–
10
12
μs
–15
–
15
%
–
50
–
kHz
–15
–
15
%
–
8
12
μs
–
425
–
μs
Continued on the next page…
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
5
ACS760ELF-20B
12 V High-Side Hot-Swap Hall Effect Based Current Monitor
OPERATING CHARACTERISTICS, continued valid at VCC = 12 V, TA = 0°C to 85°C, unless otherwise noted
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Units
Maximum Short Circuit/Overcurrent
ISC
60
110
160
A
Fault Threshold5
Short Circuit/Overcurrent Fault Gate
Measured from FAULT signal to VGATE < 1 V, Includes tGF
–
2
3
μs
tSC
Delay
VOLTAGE FAULT PERFORMANCE CHARACTERISTICS
Internal Pull Down Resistance Between
REN
TA = 25°C
–
100
–
kΩ
EN and GND
VENH
IC enabled when VEN > VENH
1.93
–
–
V
EN Voltage Threshold6
VENL
IC disabled when VEN < VENL
–
–
1
V
S1 Short Circuit Detection Current7
IS1S
VGATE = 0 V or VGATE = 12 V
0.9
1.5
2.1
A
Measured from disablement of the device to detection of an
S1 Short Circuit Detection Delay
tS1S
–
–
15
μs
S1 fault
VS1SOL IS1SHORT = 3 mA sink current
–
–
0.4
V
S1SHORT Output Voltage
S1SHORT Output Leakage Current
IS1SIH
VS1SHORT = 3.3 V
–
–
5
μA
FAULT Output Voltage
VFAULTOL IFAULT = 3 mA sink current
–
–
0.4
V
FAULT Output Leakage Current
IFAULTIH VFAULT = 3.3 V
–
–
5
μA
GATE DRIVE PERFORMANCE CHARACTERISTICS
Internal Charge Pump Voltage
VCP
TA = 25°C
–
VCC + 10
–
V
Average GATE Drive Current
IGD
VCC = 12 V, TA = 25°C
25
50
–
μA
Charge Pump Switching Frequency
fCP
TA = 25°C
–
1
–
MHz
TA = 25°C, external MOSFET S1 gate capacitance = 5.8 nF,
–
1
–
ms
measured from VGATE = 0 V to 15 V, CG pin open, no output
load capacitance
GATE Rise Time
tGR
TA = 25°C, external MOSFET S1 gate capacitance = 5.8 nF,
measured from VGATE = 0 V to 15 V, 3.75 μF capacitor con–
500
–
ms
nected between CG and GND pins
GATE Sink Resistance
RGsink
–
20
30
Ω
GATE Discharge Current
IGD
VGATE = VCC + 10 V
–
1000
–
mA
GATE Shutdown Delay
tGSD
Measured from fault event to start of GATE pull down
–
200
–
ns
Measured from VGATE = 90% of maximum to VGATE < 1 V,
GATE Maximum Fall Time
tGF
external MOSFET S1 gate capacitance = 5.8 nF. EN pin
–
800
–
ns
switched from high to low, FAULT or S1SHORT signal
TA = 25°C
18
20
22
μA
CG Output Current
ISLEW
1The small signal, ac bandwidth of this device is approximately 90 kHz.
2This test requires currents sufficient to swing the output driver between the fully off state and the saturated state. Assumes that the VIOUT pin is connected to an analog-to-digital converter that saturates at 2.5 V. The VIOUT signal is linear above 2.5 V, however, this test is NOT intended to indicate a
range of linear operation.
3Assumes that a 1% resistor with a flat temperature coefficient is connected between the ISET and GND pins.
4Can exceed t
IPFH(max) delay period via the use of a larger external capacitor. Voltage trip point on the high side of the capacitor is 3.85 V.
5This parameter is internally programmed and cannot be controlled by the end user.
6The FAULT output signal is latched. After a latched fault event, the device will be reset only when either: (a) V
EN drops below VENL, or (b) the power to
the device (applied to the IP+ pins) is toggled off and then back on.
7The voltage on the gate of the external MOSFET S1 does not need to be < 1 V in order for the device to detect an S1 short circuit condition. The
device does detect a faulty S1 when the gate of S1 is shorted to the S1 source or drain terminal.
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
6
ACS760ELF-20B
12 V High-Side Hot-Swap Hall Effect Based Current Monitor
Soft Start and Fault Characteristics
{ [
100 1–
(VIOUT_full-scale amperes –VIOUT(Q) )
2 (VIOUT_half-scale amperes – VIOUT(Q))
[{
Gate turn on rise time, tGR. Set by external capacitance, CG, on
the CG pin, such that CG = 7.5 × tGR , where CG is in μF and tGR
is rise time in seconds. For example, a 3.9 μF capacitor connected
from the CG pin to GND (without an output load) will yield a
rise time of approximately 500 ms: CG ≅ 7.5 × 0.5 s = 3.75 μF,
≅ 3.9 μF (a common capacitor value).
Zero Current Output Voltage, VIOUT(Q). The output of the sensor when the primary current, IP , is 0 A. Variation in VIOUT(Q) can
be attributed to the resolution of the Allegro linear IC quiescent
voltage trim and thermal drift.
When the CG pin is kept open, the ACS760 has a minimum tGR
of 1 ms typical.
VIOUT Total Error, ETOT. The maximum percentage deviation
of the actual output from its ideal value.
IPF fault signal delay, tIPF . This is the delay from high current
level fault sense to the start of turn-off of the external MOSFET
S1 turn-off. Set by external capacitance, COCD, on the OCDLY
pin, such that COCD = 5.17 × trOCD ; where COCD is in μF and
trOCD is rise time in seconds.
When the OCDLY pin is kept open, the IC has a minimum fault
delay, tIPFLmax, of 8 μs maximum.
Load power fault signal delay, tPFL. This is the delay from
maximum power level fault, PF(th), sense to the start of external
MOSFET S1 turn-off. Set by external capacitance, COPD, on the
OPDLY pin, such that COPD = 5.17 × trOPD ; where COPD is in μF
and trOPD is rise time in seconds.
The IC has a minimum fault delay when the OPDLY pin kept
open of 10 μs typical.
IPF fault current setting, IPF . The IPF upper trip level may be
set by using a resistor between the ISET pin and GND, such that
RSET = 104 (0.4 + 0.065 × IPF), where IPF is in A and RSET in Ω.
Accuracy Characteristics
Sensitivity, Sens. The change in sensor output in response to a
1 A change through the primary conductor. Sens is the product of
the magnetic circuit sensitivity (G/A) and the linear IC amplifier
gain (mV/G). The linear IC amplifier gain is trimmed at Allegro
final test to optimize the sensitivity (mV/A) for the full-scale current range of the device.
Noise, VNOISE(PP). The product of the linear IC amplifier gain
(mV/G) and the noise floor for the Allegro Hall effect linear IC.
Dividing the noise (mV) by the sensitivity (mV/A) provides the
smallest current that the device is able to resolve.
Nonlinearity, ELIN. The linearity of the VIOUT signal is the
degree to which the voltage output from the sensor varies in
direct proportion to the primary sensed current, through its fullscale amplitude. Nonlinearity reveals the maximum deviation in
the slope of the device transfer function compared to the slope of
the ideal transfer curve for this transducer. The following equation is used to derive the linearity:
Dynamic Response Characteristics
Propagation delay, tPROP. The time required for the sensor
output to reflect a change in the primary current signal. Propagation delay is attributed to inductive loading within the linear IC
package, as well as in the inductive loop formed by the primary
conductor geometry. Propagation delay can be considered as a
fixed time offset and may be compensated.
I (%)
Primary Current
90
Transducer Output
0
Propagation Time, tPROP
t
Response time, tRESPONSE. The time interval between a) when
the primary current signal reaches 90% of its final value, and b)
when the sensor reaches 90% of its output corresponding to the
applied current.
I (%)
Primary Current
90
Transducer Output
0
Response Time, tRESPONSE
t
Rise time (tr). The time interval between a) when the sensor
reaches 10% of its full scale value, and b) when it reaches 90%
of its full scale value. The rise time to a step response is used to
derive the bandwidth of the current sensor, in which ƒ(–3 dB) =
0.35 / tr. Both tr and tRESPONSE are detrimentally affected by eddy
current losses observed in the conductive IC ground plane.
I (%)
Primary Current
90
Transducer Output
10
0
Rise Time, tr
t
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
7
ACS760ELF-20B
12 V High-Side Hot-Swap Hall Effect Based Current Monitor
240 V*A Fault Operation
The timing diagram in figure 1 shows characteristic operation
of the ACS760 when the power consumed from the 12 V system
bus exceeds a 240 V*A or 240 W level. The system power supply
bus reaches the nominal steady state level of 12 V before the EN
pin (Enable pin, active high) of the ACS760 transitions to the
high state at time tEN1. Note that, when the EN pin is in the low
state, the GATE pin is actively pulled low. However, as shown
in the timing diagram, the voltage on the GATE pin increases
with a positive slope after the EN pin transitions to the high state.
The ramp rate of the GATE pin is controlled by the value of the
capacitor connected to the CG pin.
At a certain GATE voltage, current begins to flow through the
external protection MOSFET, S1, and this current increases as the
GATE voltage increases. The voltage at the VIOUT pin, which is
the current sensor output voltage of the ACS760, proportionally
tracks the current that flows through the MOSFET.
In the timing diagram, the system is in normal, steady state operation up until the time tINIT_F. At tINIT_F , the current load on the
12 V power supply increases from 19.2 to 22 A and the ACS760
internally registers a 240 V*A fault condition. At this time, the
voltage on the OPDLY pin increases with a constant slope. (This
slope is controlled by the value of the capacitor connected to the
OPDLY pin). This voltage continues to increase with a constant
slope until either:
• The OPDLY pin voltage reaches a threshold of 3.85 V (if this
occurs, the FAULT signal is latched in the low state), or
• The power consumption of the system falls below 240 V*A (at
which time the OPDLY pin voltage is pulled to ground)
A 240 V*A fault event is detected at t240VA_F. At this time, the
FAULT signal transitions to the low state and the GATE pin is
pulled to ground. The FAULT signal is latched and the chip will
pull down the GATE voltage until the EN pin of the ACS760
transitions to the low state and then back to the high state.
As shown in the timing diagram, certain ACS760 signals (the
FAULT signal and the OPDLY pin voltage) are reset when the EN
pin transitions to the low state. These signals are reset in order to
guarantee normal device operation (soft start and fault monitoring) when the EN signal transitions back to the high state.
Figure 1. Timing Diagram for 240 V*A Fault
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
8
ACS760ELF-20B
12 V High-Side Hot-Swap Hall Effect Based Current Monitor
Soft Short Circuit Fault Operation
The timing diagram in figure 2 shows the characteristic operation of the ACS760 when the current load on the 12 V system bus
jumps from the 19 to 20 A level to the 40 A level. The 40 A load
is typically indicative of a soft short circuit on the ILOAD side of
the external MOSFET.
In figure 2, the system power supply bus reaches the nominal
steady state level of 12 V before the EN pin (Enable pin, active
high) of the ACS760 transitions to the high state at time tEN1.
Note that when the EN pin is in the low state, the GATE pin is
actively pulled low. However, as shown in the timing diagram,
the voltage on the GATE pin increases with a positive slope after
the EN pin transitions to the high state. The ramp rate of the
GATE pin is controlled by the value of the capacitor connected to
the CG pin.
At a certain GATE voltage, current begins to flow through the
external protection MOSFET, S1, and this current increases as the
GATE voltage increases. The voltage at the VIOUT pin, which is
the current sensor output voltage of the ACS760, proportionally
tracks the current that flows through the MOSFET.
In the timing diagram the system is in normal, steady state
operation up until the time tINIT_F. At tINIT_F the current load
on the 12 V power supply increases from 19.2 A to 40 A and the
ACS760 internally registers both a 240 V*A fault condition and
an IPF fault condition. In this example, the ISET voltage was set
at 3.0 V, which corresponds to a 40 A fault threshold. At tINIT_F,
the voltage on the OPDLY and OCDLY pins increases with a
constant slope. The slope of the voltage on the two delay pins is
controlled by the value of the capacitor connected to each pin.
In this case the capacitor on the OCDLY pin is smaller than the
capacitor on the OPDLY pin and the voltage on the OCDLY pin
ramps much faster than the voltage on the OPDLY pin (both pins
are connected to separate 20 μA current sources). The voltages on
each delay pin continues to increase with a constant slope until
either:
• Either the OPDLY or the OCDLY pin voltages reach a threshold
of 3.85 V (if this occurs, the FAULT signal is latched in the low
state), or
• The current load of the system falls below 20 A for the OPDLY
pin and 40 A for the OCDLY pin
In figure 2 a short circuit fault event is detected at t40A_F. At
this time, the FAULT signal transitions to the low state and the
GATE pin is pulled to ground. The FAULT state is latched and
the chip will pull down the GATE voltage until the EN pin of the
ACS760 transitions to the low state and then back to the high
state. As shown in the timing diagram, certain ACS760 signals
(the FAULT signal and the OCDLY pin voltage) are reset when
the EN pin transitions to the low state. These signals are reset in
order to guarantee normal device operation (soft start and fault
monitoring) when the EN signal transitions back to the high state.
Figure 2. Timing Diagram for 30 to 40 A Load Fault
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
9
ACS760ELF-20B
12 V High-Side Hot-Swap Hall Effect Based Current Monitor
Hard Short Circuit (50 mΩ from VLOAD to GND)
Fault Operation
The timing diagram below specifically shows characteristic
operation of the ACS760 when the device is powered on (via the
EN pin) and a 50 mΩ short circuit is present from load side of the
external MOSFET, S1, to ground.
ISC , is greater than 100 A, then the OCDLY pin will reach the
3.85 V threshold before the current through the external MOSFET exceeds ISC. This is the case depicted in the panel A. The
fault event is detected at tGATE_LOW. At this time. the FAULT
signal transitions to the low state and the GATE pin is pulled to
ground.
In figure 3 the system power supply bus reaches the nominal
steady state level of 12 V before the EN pin of the ACS760 transitions to the high state at time tEN1. The voltage on the GATE
pin increases with a positive slope after the EN pin transitions to
the high state. The ramp rate of the GATE pin is controlled by the
value of the capacitor connected to the CG pin. In the example
shown below a small capacitor is connected to the CG pin and the
pin ramps to 5.5 V in < 10 μs.
In the event that a large capacitor is connected to the OCDLY pin,
the ACS760 will not pull down the gate of the external MOSFET until the current flowing through the MOSFET exceeds ISC
(shown in panel B, under the assumption that ISC equals 130 A).
The device pulls down the MOSFET GATE approximately 2 μs
after the load current exceeds this threshold. If a large capacitor
is connected to the OCDLY pin a significant current (> 40 A but
< 160 A) may flow through the MOSFET for tens of microseconds before the Short Circuit Fault Threshold trips. These tens
of microseconds elapse as the GATE charges and the load current
increases, finally exceeding the short circuit threshold.
In panel A of figure 3, the device is enabled into a 50 mΩ short
circuit. Therefore, as the GATE voltage increases the current
through the external MOSFET increases at a rapid rate. In this
example case it is assumed that there is no capacitor on the
OCDLY pin. When the current through the MOSFET exceeds the
threshold set by the RSET resistor, the voltage on the OCDLY pin
rises quickly beginning at t40A_F. As the voltage on the OCDLY
pin rises, so does the voltage on the CG pin and the current
through the external MOSFET. If there is no capacitor on the
OCDLY pin, and if the ACS760 Short Circuit Fault Threshold,
(A)
The FAULT signal is latched and the chip will pull down the
GATE voltage until the EN pin of the ACS760 transitions to the
low state and then back to the high state. Certain ACS760 signals
(soft start and fault monitoring) are reset when the EN pin transitions to the low state. These signals are reset in order to guarantee
normal device operation when the EN signal transitions to the
high state.
(B)
Figure 3. (A) Timing Diagram for a 50 mΩ Short Circuit from VLOAD to GND; (B) Timing Diagram for a 50 mΩ Short Circuit from VLOAD to GND, capacitor
COCD with high rating connected.
10
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
ACS760ELF-20B
12 V High-Side Hot-Swap Hall Effect Based Current Monitor
S1 Short Fault Operation
The timing diagram in figure 4 shows the characteristic operation
of the ACS760 when the power consumed from the 12 V system
bus exceeds a 240 V*A or 240 W level. For the operation during a
240 V*A fault condition, refer to figure 1. That section describes
the operation of the ACS760 until the time t240VA_F. Figure 4
depicts a 240 V*A fault, but continues on to demonstrate the ability of the ACS760 to detect damage and improper operation of
the external MOSFET in an S1 short circuit event.
At t240VA_F the FAULT signal transitions to the low state and the
ACS760 pulls down the voltage on the GATE pin. During normal
,
operation, when the GATE pin is at 0 V, the current through the
S1 MOSFET (and therefore through the ACS760) equals approximately 0 A. However, in the case depicted in figure 4, current
through the S1 MOSFET flows even though the GATE pin is
pulled low. If a FAULT has occurred and more than 2.1 A flow
through the ACS760, then the S1SHORT signal transitions to the
low state. When the S1SHORT signal is low, that indicates to the
system that the ACS760 cannot turn off the external MOSFET
(for example, when a short circuit exists between the source and
the drain of the MOSFET). In the case depicted, the system shuts
down the 12 V power supply after the S1SHORT signal transitions to the low state.
Note that, in some cases, the GATE of the S1 MOSFET may be
shorted to the source or drain of the MOSFET. In this case the
ACS760 may not be able to pull down the gate of the S1 MOSFET. However, in this case the ACS760 will still register an S1
Short even if the gate potential is equal to or greater than 12 V.
If the ACS760 is disabled (EN pin in the low state) and greater
than 2.1 A flows through the ACS760, then the device will register an S1 Short condition and the S1SHORT pin will transition
to the low state. The voltage on the GATE pin is not used as a
determining factor when sensing an S1 Short condition.
The S1SHORT signal will not reset to a high state until power
to the device is cycled. Toggling the EN pin does not reset the
latched S1 Short state.
Determining the Root Cause of an ACS760 Fault Event
The following truth table provides system debugging information
in the event of a fault event during use of the ACS760. Note that
for all of the fault conditions listed, it is possible to monitor the
voltages of various ACS760 output pins and determine the cause
of the ACS760 FAULT event.
Figure 4. Timing Diagram for S1 Short
Fault Condition Truth Table
Pin Logic State
FAULT Pin
OPDLY Pin
OCDLY Pin
Probable Root Cause
Low
High
Low
240 V*A system power level, PF(th), exceeded
Low
Don’t Care
High
IP Fault Current Threshold, IPF, exceeded
Low
Low
Low
Short Circuit Fault Threshold, ISC, exceeded
11
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
ACS760ELF-20B
12 V High-Side Hot-Swap Hall Effect Based Current Monitor
Fault Condition Characteristics
GATE
GATE
INPUT CURRENT 10 mV/A
INPUT CURRENT 10 mV/A
OPDLY
OCDLY
FAULT
FAULT
Figure 5. 240 V*A fault: with VCC = 12 V and ACS760 enabled, apply load
Figure 6. IPF event: with VCC = 12 V and ACS760 enabled, apply load
ENABLE
VIOUT
GATE
IPOUT
Figure 7. Hot-swap with 1 μF capacitor from CG pin to GND, resistive
load approximately 0.17 Ω. capacitive load approximately 3300 μF; CG
capacitor limits inrush current to 720 mA during hot swap event (15 A
current probe used)
12
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
ACS760ELF-20B
12 V High-Side Hot-Swap Hall Effect Based Current Monitor
GATE
VIN
VIOUT
ENABLE
Figure 8. Power-up: with the enable jumper on, apply VCC
GATE
GATE
VIN
VIN
VIOUT
VIOUT
ENABLE
ENABLE
Figure 9. Power-up: with VCC on, apply the enable jumper (enables
ACS760)
Figure 10. Power-down: with enable jumper on, remove supply (disables
ACS760)
GATE
VIN
GATE
VIN
VIOUT
VIOUT
ENABLE
ENABLE
Figure 11. Power-up to power-down (a): remove enable jumper (disables
ACS760, but VCC and VIOUT stay high (see figure 12)
Figure 12. Power-up to power-down (b): with ACS760 disabled (see
figure 11), remove supply (VCC and VIOUT brought low)
13
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
ACS760ELF-20B
12 V High-Side Hot-Swap Hall Effect Based Current Monitor
Application Information: Current Mode Operation
The ACS760 has the ability to operate in pure Current Mode.
If the Allegro ACS760 detects power in excess of 240 V*A,
the FAULT output of the device transitions from a logic high to
a logic low level and the integrated gate driver circuitry pulls
the gate of an external MOSFET to GND. The delay between
the detection of an excess power condition and gate shutdown
is set by an external capacitor on the OPDLY pin to GND. The
ACS760, however, has the ability to override the Power Mode
fault condition to operate in pure Current Mode.
Pulling the OPDLY pin to GND, disables the 240 V*A power
fault to allow the ACS760 to operate in pure Current Mode. The
user may then set the current fault threshold by adjusting the
resistor value from the ISET pin to GND. If the current exceeds
the set threshold, the FAULT output of the device trips and
the gate of the external MOSFET is pulled to GND. The delay
between the detection of a soft short circuit condition and gate
shutdown is set by the capacitor on the OCDLY pin. In Current
Mode Operation, the ACS760 has the ability to detect a S1 Short
and Hard Short.
14
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
ACS760ELF-20B
12 V High-Side Hot-Swap Hall Effect Based Current Monitor
Package LF, 24-pin QSOP
8.74 .344
8.55 .337
24
8º
0º
0.25 .010
0.19 .007
Preliminary dimensions, for reference only
Dimensions in millimeters
U.S. Customary dimensions (in.) in brackets
(reference JEDEC MO-137 AE, except case length and terminal width and pitch)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
3.99 .157
3.81 .150
6.20 .244
5.79 .228
A
1.27 .050
0.40 .016
A Terminal #1 mark area
B Reference pad layout (reference IPC SOP63P600X175-24M);
adjust as necessary to meet application process requirements
1
2
0.254 .010
REF
24X
SEATING PLANE
GAUGE PLANE
0.10 [.004] C
0.30 .012
0.20 .008
1.75 .069
1.35 .053
0.635 .025
0.25 .010
0.10 .004
22X0.20±0.05 .008±.002
MIN
2.30 .091
NOM
Text 1
Text 2
Text 3
Package Branding
Two alternative patterns are used
ACS760T
RLCPPP
YYWWA
ACS
760
T
R
LC
PPP
YY
WW
A
5.00 .197
NOM
B
0.635 .025
NOM
0.40 .016
MAX
Allegro Current Sensor
Device family number
Indicator of 100% matte tin leadframe plating
Operating ambient temperature range code
Package type designator
Primary sensed current
Date code: Calendar year (last two digits)
Date code: Calendar week
Date code: Shift code
ACS760T
RLCPPP
L...L
YYWW
ACS
760
T
R
LC
PPP
L...L
YY
WW
Allegro Current Sensor
Device family number
Indicator of 100% matte tin leadframe plating
Operating ambient temperature range code
Package type designator
Primary sensed current
Lot code
Date code: Calendar year (last two digits)
Date code: Calendar week
Copyright ©2006, 2007, Allegro MicroSystems, Inc.
The products described herein are manufactured under one or more of the following U.S. patents: 5,045,920; 5,264,783; 5,442,283; 5,389,889;
5,581,179; 5,517,112; 5,619,137; 5,621,319; 5,650,719; 5,686,894; 5,694,038; 5,729,130; 5,917,320; and other patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use;
nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
15
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com