APW7068 Synchronous Buck PWM and Linear Controller with 0.8V Reference Out Voltage Features General Description • Two Regulated Voltages and REF_OUT The APW7068 integrates synchronous buck - Synchronous Buck Converter PWM, linear controller, and 0.8V Reference Out Voltage, - Linear Regulator as well as the monitoring and protection functions - REF_OUT = 0.8V±1% with 3mA source current into a single package. The fixed 300KHz switching • • frequency synchronous PWM controller drives Single 12V Power Supply Required dual N-channel MOSFETs, which provides one controlled Excellent Both Output Voltage Regulation power output with over-voltage and over-current - 0.8V Internal Reference protections. Linear controller drives an external - ±1% Over Line Voltage and Temperature • • • • N-channel MOSFET with under-voltage protection. Integrated Soft-Start for PWM and Linear Outputs The APW7068 provides excellent regulation for 300KHz Fixed Switching Frequency output load variation. An internal 0.8V temperature- Voltage Mode PWM Control Design and Up to compensated reference voltage is designed to meet 89%(Typ.) Duty Cycle the requirement of low output voltage applications. Under-Voltage Protection Monitoring Linear The APW7068 with excellent protection functions: Output • • • • POR, OCP, OVP and UVP. The Power-On Reset Over-Voltage Protection Monitoring PWM Output (POR) circuit can monitor VCC12 supply voltage Over-Current Protection for PWM Output exceeds its threshold voltage while the controller is - Sense Low-side MOSFET’s RDS(ON) running, and a built-in digital soft-start provides both SOP-14, QSOP-16 and QFN-16 packages outputs with controlled rising voltage. The Over-Current Protection (OCP) monitors the output current by using Lead Free Available (RoHS Compliant) the voltage drop across the lower MOSFET’s RDS(ON), comparing with the voltage of OCSET pin. When the output current reaches the trip point, the controller will Applications shutdown the IC directly, and latch the converter’s • the voltage of FBL pin for short-circuit protection. When output. The Under-Voltage Protection (UVP) monitors Graphic Cards the VFBL is less than 50% of VREF, the controller will shutdown the IC directly. The Over-Voltage Protection (OVP) monitors the voltage of FB. When the VFB is over 135% of V REF, the controller will make Lowside gate signal fully turn on until the fault events are removed. ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.2 - Jun., 2006 1 www.anpec.com.tw APW7068 BOOT 1 16 UGATE FS_DIS 2 13 PHASE FS_DIS 2 15 PHASE COMP 3 12 PGND COMP 3 14 PGND FB 4 11 LGATE FB 4 13 LGATE DRIVE 5 10 OCSET DRIVE 5 12 OCSET FBL 6 9 REF_OUT FBL 6 11 REF_OUT GND 7 8 VCC12 GND 7 10 VCC12 GND 8 9 1 FB 2 DRIVE 3 FBL 4 VCC12 BOOT UGATE PHASE 15 14 13 Metal GND Pad (Bottom) 5 AGND SOP-14 TOP VIEW COMP 16 QSOP-16 TOP VIEW 6 7 8 VCC12 14 UGATE VCC12 1 DGND BOOT FS_DIS Pinouts 12 PGND 11 LGATE 10 OCSET 9 REF_OUT QFN-16 TOP VIEW Ordering and Marking Information APW7068 Lead Free Code Handling Code Temp. Range Package Code APW7068 K : APW7068 XXXXX Package Code K : SOP - 14 M : QSOP - 16 QA : QFN - 16 Temp. Range E : -20 to 70 °C Handling Code TU : Tube TR : Tape & Reel TY : Tray (for QFN only) Lead Free Code L : Lead Free Device Blank : Original Device XXXXX - Date Code APW7068 M : APW7068 XXXXX XXXXX - Date Code APW7068 Q : APW7068 XXXXX XXXXX - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS and compatible with both SnPb and lead-free soldering operations. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J STD-020C for MSL classification at lead-free peak reflow temperature. Copyright ANPEC Electronics Corp. Rev. A.2 - Jun., 2006 2 www.anpec.com.tw APW7068 Block Diagram OCSET VCC12 IOCSET 40uA REF_OUT Reference Buffer Regulator Power-On Reset GND VREF (0.8V) 135%VREF X1.35 UGATE O.C.P Comparator 10V O.V.P Comparator BOOT Soft Start and Fault Logic PHASE Sense Low Side Gate Control LGATE PGND Error Amp 1 PWM Comparator U.V.P Comparator FBL 10V :2 50%VREF DRIVE VREF Error Amp 2 Oscillator Sawtooth Wave (300KHz) FB COMP VREF FS_DIS Absolute Maximum Ratings Symbol Parameter Rating -0.3 to +16 Unit V -0.3 to +16 V <400ns pulse width >400ns pulse width -5 to BOOT+5 -0.3 to BOOT+0.3 V LGATE to PGND <400ns pulse width >400ns pulse width -5 to VCC12+5 -0.3 to VCC12+0.3 V PHASE to GND <400ns pulse width >400ns pulse width -5 to +21 -0.3 to 16 V DRIVE to GND 12 V FB, FBL, COMP, FB, FBL, COMP, FS_DIS to GND FS_DIS -0.3 to 7 V VCC12 VCC12 to GND BOOT BOOT to PHASE UGATE to PHASE UGATE LGATE PHASE DRIVE Copyright ANPEC Electronics Corp. Rev. A.2 - Jun., 2006 3 www.anpec.com.tw APW7068 Absolute Maximum Ratings (Cont.) Symbol Parameter PGND TJ Rating Unit PGND to GND -0.3 to +0.3 V Junction Temperature Range -20 to +150 -65 ~ 150 °C °C TSTG Storage Temperature TSDR Soldering Temperature (10 Seconds) 300 °C Minimum ESD Rating ±2 KV VESD NOTE1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. NOTE2: The device is ESD sensitive. Handling precautions are recommended. Recommended Operating Conditions Symbol VCC12 VIN1 Parameter IC Supply Voltage Rating 10.8 to 13.2 Unit V Converter Input Voltage 2.9 to 13.2 V V VOUT1 Converter Output Voltage 0.9 to 5 IOUT1 Converter Output Current 0 to 30 A Linear Output Current 0 to 3 A IOUT2 TA Ambient Temperature Range -20 to 70 °C TJ Junction Temperature Range -20 to 125 °C Electrical Characteristics Unless otherwise specified, these specifications apply over VCC12=12V, and TA =-20~70°C. Typical values are at TA=25°C. Symbol Parameter Test Conditions APW7068 Min Typ Max Unit INPUT SUPPLY CURRENT ICC12 VCC12 Supply Current (Shutdown mode) UGATE, LGATE and DRIVE open; FS_DIS=GND 4 6 mA VCC12 Supply Current UGATE, LGATE and DRIVE open 8 12 mA POWER-ON RESET Rising VCC12 Threshold 7.7 7.9 8.1 V Falling VCC12 Threshold 7.2 7.4 7.6 V +15 % 345 KHz OSCILLATOR Accuracy -15 FOSC Oscillator Frequency 255 VOSC Ramp Amplitude Duty Maximum Duty Cycle Copyright ANPEC Electronics Corp. Rev. A.2 - Jun., 2006 (nominal 1.2V to 2.7V) (NOTE3) 4 300 1.5 V 89 % www.anpec.com.tw APW7068 Electrical Characteristics (Cont.) Unless otherwise specified, these specifications apply over VCC12=12V, and TA =-20~70°C. Typical values are at TA=25°C. Symbol Parameter Test Conditions APW7068 Min Typ Max Unit REFERENCE VREF Reference Voltage for Error Amp1 and Amp2 Reference Voltage Tolerance 0.792 0.80 0.808 -1 V +1 % PWM Load Regulation IOUT1=0 to 10A 1 % Linear Load Regulation IOUT2=0 to 3A 1 % PWM ERROR AMPLIFIER Gain GBWP SR Open Loop Gain RL=10k, CL=10pF (NOTE3) 93 dB Open Loop Bandwidth RL=10k, CL=10pF (NOTE3) 20 MHz Slew Rate RL=10k, CL=10pF (NOTE3) FB Input Current VFB=0.8V 8 0.1 V/us 1 uA VCOMP COMP High Voltage 5 V VCOMP COMP Low Voltage 0 V ICOMP COMP Source Current COMP=2V 12 mA ICOMP COMP Sink Current COMP=2V 12 mA BOOT=12V, UGATE-PHASE = 2V 2.5 A 2 A 2.5 A 3.5 A GATE DRIVERS IUGATE Upper Gate Source Current IUGATE Upper Gate Sink Current ILGATE Lower Gate Source Current ILGATE Lower Gate Sink Current RUGATE Upper Gate Source Impedance BOOT=12V, IUGATE=0.1A 2.25 3.375 Ω RUGATE Upper Gate Sink Impedance 0.7 1.05 Ω RLGATE Lower Gate Source Impedance VCC12=12V, ILGATE=0.1A 2.25 3.375 Ω RLGATE Lower Gate Sink Impedance 0.4 Ω TD VCC12=12V, LGATE=2V BOOT=12V, IUGATE=0.1A VCC12=12V, ILGATE=0.1A Dead Time 0.6 20 nS LINEAR REGULATOR Gain GBWP SR Open Loop Gain RL=10k, CL=10pF (NOTE3) 70 dB Open Loop Bandwidth RL=10k, CL=10pF (NOTE3) 19 MHz Slew Rate RL=10k, CL=10pF (NOTE3) 6 V/us FBL Input Current VFBL=0.8V 0.1 1 uA VDRIVE DRIVE High Voltage VDRIVE DRIVE Low Voltage 0 V IDRIVE DRIVE Source Current DRIVE=5V 4 mA IDRIVE DRIVE Sink Current DRIVE=5V 3 mA Copyright ANPEC Electronics Corp. Rev. A.2 - Jun., 2006 10 5 V www.anpec.com.tw APW7068 Electrical Characteristics (Cont.) Unless otherwise specified, these specifications apply over VCC12=12V, and TA =-20~70°C. Typical values are at TA=25°C. Symbol Parameter APW7068 Test Conditions Min Typ Unit Max PROTECTION VFB-OV FB Over Voltage Protection Trip Point Percent of VREF 135 % VFBL-UV FBL Under Voltage Protection Trip Point Percent of VREF 50 % IOCSET OCSET Current Source 36 40 44 uA SOFT START TSS Internal Soft-Start Interval (NOTE3) FOSC=300kHz 8.5 ms 0.792 0.800 0.808 V REF_OUT VREF_OUT Output Voltage Offset Voltage -8 IREF_OUT Source Current +8 mV 1.5 3 mA Sink Current 0.25 0.5 mA Output Capacitance 0.4 1 uF 2.2 NOTE3: Guaranteed by design. Typical Application Circuit C1 2.2nF Q3 CIN1 ON/OFF 470uFx2 2N7002 R2 VIN1 12V Q1 C2 APM2509 0.01uF 3.9K L C4 R1 VOUT1 VOUT1 1uH 0.1uF 1.2V 1.5K R3 C3 22Ω 22nF VIN2 BOOT UGATE 14 2 FS_DIS PHASE 13 3 COMP 4 FB LGATE 11 5 DRIVE OCSET 10 6 FBL REF_OUT 9 7 GND 1 RGND1 COUT1 3K 3.3V PGND 12 C6 Q2 CIN2 470uF Q4 APM3055 C5 R5 R4 VCC12 470uFx2 2.2nF APM2506 R6 2.2Ω 8 VOUT2 2.5V APW7068 2.5K COUT2 RGND2 470uF 1.17K C8 R7 1uF 12V R8 2.2Ω C7 1uF * C5, R5 for specific application Copyright ANPEC Electronics Corp. Rev. A.2 - Jun., 2006 6 www.anpec.com.tw APW7068 Function Pin Descriptions VCC12 LGATE Power supply input pin. Connect a nominal 12V power supply to this pin. The power-on reset function monitors the input voltage at this pin. It is recommended that a decoupling capacitor (1 to 10µF) be connected to GND for noise decoupling. This pin is the gate driver for the lower MOSFET of PWM output. DRIVE This pin drives the gate of an external N-channel MOSFET for linear regulator. It is also used to set the compensation for some specific applications,for example, with low values of output capacitance and ESR. BOOT This pin provides the bootstrap voltage to the upper gate driver for driving the N-channel MOSFET. An external capacitor from PHASE to BOOT, an internal diode, and the power supply valtage VCC12, generates the bootstrap voltage for the upper gate diver (UGATE). FBL This pin is the inverting input of the linear regulator error amplifier. It is used to set the output voltage. This pin is also monitored for under-voltage protection. When the FBL voltage is under 50% of reference voltage (0.4V), both outputs will be shutdown immediately. PHASE This pin is the return path for the upper gate driver. Connect this pin to the upper MOSFET source, and connect a capacitor to BOOT for the bootstrap voltage. This pin is also used to monitor the voltage drop across the lower MOSFET for over-current protection. OCSET Connect a resistor (Rocset) from this pin to GND, an internal 40uA current source will flow through this resistor and create a voltage drop. When VCC12 reaches the POR rising threshold voltage, the voltage drop of Rocset will be memoried and compared with the voltage across the lower MOSFET. The threshold of the over current limit is therefore given by: GND This pin is the signal ground pin. Connect the GND pin to a good ground plane. PGND This pin is the power ground pin for the lower gate driver. It should be tied to GND pin on the board. ILIMIT = COMP This pin is the output of PWM error amplifier. It is used to set the compensation components. IOCSET × ROCSET RDS(ON)(LOW − Side) REF_OUT This pin provides a buffed voltage, which is from internal reference voltage. It is recommended that a 1uF capacitor is connected to ground for stability. FB This pin is the inverting input of the PWM error amplifier. It is used to set the output voltage and the compensation components. This pin is also monitored for over-voltage protection. When the FB voltage is over 135% of reference voltage, the controller will make Low-side gate signal fully turn on until the fault events are removed. FS_DIS This pin provides shutdown function. Use an open drain logic signal to pull this pin low to disable both outputs, leave open to enable both outputs. UGATE This pin is the gate driver for the upper MOSFET of PWM output. Copyright ANPEC Electronics Corp. Rev. A.2 - Jun., 2006 7 www.anpec.com.tw APW7068 Typical Characteristics Power Off Power On VCC12=12V, Vin1=12V,Vin2=3.3V VCC12=12V, Vin1=12V,Vin2=3.3V Vo1=1.2V,Vo2=2.5V, L=1uH Vo1=1.2V,Vo2=2.5V, L=1uH CH1 CH1 CH2 CH2 CH3 CH3 CH1: VCC12 (10V/div) CH2: Vo1 (1V/div) CH3: Vo2 (2V/div) Time: 10ms/div CH1: VCC12 (10V/div) CH2: Vo1 (1V/div) CH3: Vo2 (2V/div) Time: 10ms/div EN Shutdown(FS_DIS=GND) VCC12=12V, Vin1=12V,Vin2=3.3V VCC12=12V, Vin1=12V,Vin2=3.3V Vo1=1.2V,Vo2=2.5V,L=1uH Vo1=1.2V,Vo2=2.5V,L=1uH CH1 CH1 CH2 CH2 CH3 CH3 CH4 CH4 CH1: FS_DIS (1V/div) CH2: Drive (5V/div) CH3: Vo1 (1V/div) CH4: Vo2 (2V/div) Time: 10ms/div Copyright ANPEC Electronics Corp. Rev. A.2 - Jun., 2006 CH1: FS_DIS (1V/div) CH2: Drive (5V/div) CH3: Vo1 (1V/div) CH4: Vo2 (2V/div) Time: 10ms/div 8 www.anpec.com.tw APW7068 Typical Characteristics (Cont.) UGATE Falling UGATE Rising Vcc12=12V, Vin1=12V, Vo1=1.2V Vcc12=12V, Vin1=12V, Vo1=1.2V CH1 CH1 CH2 CH2 CH3 CH3 CH1: Ug (20V/div) CH2: Phase (10V/div) CH3: Lg (10V/div) Time: 50ns/div CH1: Ug (20V/div) CH2: Phase (10V/div) CH3: Lg (10V/div) Time: 50ns/div OVP_PWM Controller (FB > 135% VREF) UVP_Linear Regulator (FBL< 50% VREF) VCC12=12V, Vin2=3.3V Vo2=2.5V, Io2=3A Vcc12=12V, Vin1=12V Vo1=1.2V, Vo2=2.5V,L=1uH CH1 CH1 CH2 CH2 CH3 CH3 CH4 CH1: VCC (20V/div) CH2: LG (10V/div) CH3: Vo1 (500mV/div) CH4: Vo2 (2V/div) Time: 10ms/div Copyright ANPEC Electronics Corp. Rev. A.2 - Jun., 2006 CH1: FBL (1V/div) CH2: Drive (5V/div) CH3: Vo2 (2V/div) Time: 100us/div 9 www.anpec.com.tw APW7068 Typical Characteristics (Cont.) Load Transient Response(PWM Controller) - VCC12=12V, Vin1=12V, Vo1=2V, Fosc=300KHz - Io1 slew rate= ± 10 A/us Io1=0Aà10Aà0A Io1=0Aà10A Io1=10Aà0A CH1 CH1 CH1 CH2 CH2 CH2 CH3 CH3 CH3 CH1: Vo1 (100mV/div,AC) CH2: Ug (20V/div) CH3: Io1(10A/div) CH1: Vo1 (100mV/div,AC) CH2: Ug (20V/div) CH3: Io1(10A/div) CH1: Vo1 (100mV/div,AC) CH2: Ug (20V/div) CH3: Io1(10A/div) Time: 20us/div Time: 50us/div Time: 20us/div Load Transient Response(Linear Regulator) - VCC12=12V, Vin2=3.3V, Vo2=2.5V - Io2 slew rate= ± 3A/us Io2=0Aà3Aà0A Io2=0Aà3A Io2=3Aà0A CH1 CH1 CH1 CH2 CH2 CH2 CH1: Vo2 (100mV/div,AC) CH2: Io2(2A/div) CH1: Vo2 (100mV/div,AC) CH2: Io2(2A/div) CH1: Vo2 (100mV/div,AC) CH2: Io2(2A/div) Time: 1us/div Time: 10us/div Time: 1us/div Copyright ANPEC Electronics Corp. Rev. A.2 - Jun., 2006 10 www.anpec.com.tw APW7068 Typical Characteristics (Cont.) Short Test after Power Ready Over Current Protection VCC12=12V, Vin1=12V, Vo1=1.2V,Vin2=3.3V, Vo2=2.5V, L=1uH, COUT=470uFx2 Rocset=1KΩ , Rds(on)=4mΩ VCC12=12V, Vin1=12V, Vo1=1.2V,Vin2=3.3V, Vo2=2.5V, L=1uH, COUT=470uFx2 Rocset=1KΩ , Rds(on)=4mΩ CH1 CH1 CH2 CH2 CH3 CH3 CH4 CH4 CH1: Vo1 (1V/div) CH2: Drive (5V/div) CH3: Ug (20V/div) CH4: IL (10A/div) Time: 50us/div CH1: Vo1 (1V/div) CH2: Drive (5V/div) CH3: Ug (20V/div) CH4: IL (10A/div) Time: 50us/div Short Test before Power On VREF vs. Junction Temperature 0.804 VCC12=12V, Vin1=12V,Vin2=3.3V Vo1=1.2V,Vo2=2.5V,L=1uH COUT=470uFx2 0.8035 Reference Voltage(V) CH1 CH2 CH3 0.803 0.8025 0.802 VREF 0.8015 0.801 CH4 0.8005 -40 CH1: VCC12 (10V/div) CH2: Vo1 (1V/div) CH3: Ug (20V/div) CH4: IL (10A/div) Time: 2ms/div Copyright ANPEC Electronics Corp. Rev. A.2 - Jun., 2006 -20 0 20 40 60 80 100 120 Junction Temperature (°C ) 11 www.anpec.com.tw APW7068 Typical Characteristics (Cont.) UGATE Source Current vs. UGATE Voltage UGATE Sink Current vs. UGATE Voltage 3.5 VBOOT=12V 2.5 3 PHASE=0V UGATE Sink Current (A) UGATE Source Current (A) 3 2 1.5 1 0.5 VBOOT=12V PHASE=0V 2.5 2 1.5 1 0.5 0 0 0 2 4 6 8 10 12 0 0.5 1 2 2.5 3 UGATE Voltage (V) UGATE Voltage (V) LGATE Source Current vs. LGATE Voltage LGATE Sink Current vs. LGATE Voltage 7 3 6 2.5 VCC=12V VCC=12V LGATE Sink Current (A) LGATE Source Current (A) 1.5 2 1.5 1 0.5 5 4 3 2 1 0 0 0 2 4 6 8 10 12 0 LGATE Voltage (V) Copyright ANPEC Electronics Corp. Rev. A.2 - Jun., 2006 1 2 3 4 LGATE Voltage (V) 12 www.anpec.com.tw APW7068 Function Descriptions Power On Reset (POR) Voltage(V) The Power-On Reset (POR) function of APW7068 continually monitors the input supply voltage (VCC12), VCC12 ensures the supply voltage exceed its rising POR threshold voltage. The POR function initiates soft-start POR interval operation while VCC12 voltages exceed their POR threshold and inhibits operation under disabled VOUT1 VOUT2 status. Soft-Start Figure 1. shows the soft-start interval. When VCC12 t0 reaches the rising POR threshold voltage, the internal reference voltage is controlled to follow a voltage pro- t1 t2 Time Figure 1. Soft-Start Interval portional to the soft-start voltage. The soft-start inter- Voltage(V) val is variable by the oscillator frequency. The formu- FB lation is given by: T SS = ∆ (t 2 − t1 ) = 1 × 2 560 F OSC FBL 20mV 32/Fosc Figure 2. shows more detail of the FB and FBL voltage ramps. The FB and FBL voltage soft-start ramps are 32/Fosc 20mV formed with many small steps of voltage. The voltage of one step is about 20mV in FB and FBL, and the period of one step is about 64/FOSC. This method pro- t3 vides a controlled voltage rise and prevents the large Time t4 Figure 2. The Controlled Stepped FB and FBL peak current to charge output capacitor. The FB volt- Voltage during Soft-Start age compares the FBL voltage to shift to an earlier time the establishment as Figure2. The voltage estabilishment Over-Current Protection time difference for FB and FBL is variable by the Connect a resistor (Rocset) from this pin to GND, an oscillator. The formulation is given by: internal 40uA current source will flow through this resistor and create a voltage drop, which will be compared with the voltage across the lower MOSFET. ∆(t4 − t3) = 1 1 × 640 = × TSS FOSC 4 When the voltage across the lower MOSFET exceeds the voltage drop across the ROCSET, an over-current condition is detected and the controller will shutdown the IC directly, and the converter's output is latched. Copyright ANPEC Electronics Corp. Rev. A.2 - Jun., 2006 13 www.anpec.com.tw APW7068 Function Descriptions Over-Current Protection (Cont.) voltage is over 135% of the reference voltage, the The threshold of the over current limit is therefore controller will make Low-Side gate signal fully turn on given by: until the fault events are removed. ILIMIT = Under Voltage Protection IOCSET × ROCSET RDS(ON)(LOW − Side) The FBL pin is monitored during converter operation by its own Under Voltage(UV) comparator. If For the over-current is never occurred in the normal the FBL voltage drop below 50% of the reference operating load range; the variation of all parameters in voltage (50% of 0.8V = 0.4V), a fault signal is inter- the above equation should be determined. nally generated, and the device turns off both high- ·The MOSFET’s RDS(ON) is varied by temperature and side and low-side MOSFET and the converter’s out- gate to source voltage, the user should determine the put is latched to be floating. The controller will shut- maximum RDS(ON) in manufacturer’s datasheet. down the IC directly. · The minimum IOCSET (36uA) and minimum ROCSET Shutdown and Enable should be used in the above equation. · Note that the ILIMIT is the current flow through the Pulling the FS_DIS voltage to GND by an open drain lower MOSFET; ILIMIT must be greater than maximum transistor, shown in typical application circuit, output current add the half of inductor ripple current. shutdown the APW7068 PWM controller. In shutdown mode, the UGATE and LGATE turn off and pull to PHASE and GND respectively. Over Voltage Protection The FB pin is monitored during converter operation by its own Over Voltage(OV) comparator. If the FB Application Information Output Voltage Selection The output voltage of PWM converter can be programmed The linear regulator output voltage VOUT2 is also set by with a resistive divider. Use 1% or better resistors for means of an external resistor divider. The FBL pin is the resistive divider is recommended. The FB pin is the inverter input of the error amplifier, and the reference the inverter input of the error amplifier, and the reference voltage is 0.8V. The output voltage is determined by: voltage is 0.8V. The output voltage is determined by: R4 VOUT2 = 0.8 × 1 + R GND2 R1 VOUT1 = 0.8 × 1 + R GND1 Where R4 is the resistor connected from VOUT2 to Where R1 is the resistor connected from VOUT1 to FB FBL and RGND2 is the resistor connected from FBL to and RGND1 is the resistor connected from FB to GND. GND. Copyright ANPEC Electronics Corp. Rev. A.2 - Jun., 2006 14 www.anpec.com.tw APW7068 Application Information (Cont.) Linear Regulator Input/Output Capacitor Selection loop. A compensation network among COMP, FB and The input capacitor is chosen based on its voltage VOUT1 should be added. The compensation network is shown in Fig. 9. The output LC filter consists of the rating. Under load transient condition, the input output inductor and output capacitors. The transfer capacitor will momentarily supply the required transient function of the LC filter is given by: current. The output capacitor for the linear regulator is chosen to minimize any droop during load transient GAINLC = condition. In addition, the capacitor is chosen based on its voltage rating. 1 + s × ESR × COUT1 s × L × COUT1 + s × ESR × COUT1 + 1 2 The poles and zero of this transfer functions are: Linear Regulator Input/Output MOSFET Selection The maximum DRIVE voltage is about 10V when FLC = VCC12 is equal 12V. Since this pin drives an external N-channel MOSFET, therefore the maximum output voltage of the linear regulator is dependent upon the 1 2 × π × L × C OUT1 FESR = VGS. V OUT2MAX = 10 - VGS 1 2 × π × ESR × C OUT1 The FLC is the double poles of the LC filter, and FESR is the zero introduced by the ESR of the output capacitor. Another criterion is its efficiency of heat removal. The power dissipated by the MOSFET is given by: PHASE L OUTPUT1 Pd = IOUT2 x (VIN – V OUT2 ) Where IOUT2 is the maximum load current, VOUT2 is the COUT1 nominal output voltage. ESR In some applications, heatsink might be required to help maintain the junction temperature of the MOSFET Figure 6. The Output LC Filter below its maximum rating. Linear Regulator Compensation Selection FLC The linear regulator is stable over all loads current. -40dB/dec However, the transient response can be further enhanced GAIN (dB) by connecting a RC network between the FBL and DRIVE pin. Depending on the output capacitance and load current of the application, the value of this RC network is then varied. FESR -20dB/dec PWM Compensation The output LC filter of a step down converter introduces Frequency(Hz) a double pole, which contributes with -40dB/decade Figure 7. The LC Filter GAIN and Frequency gain slope and 180 degrees phase shift in the control Copyright ANPEC Electronics Corp. Rev. A.2 - Jun., 2006 15 www.anpec.com.tw APW7068 Application Information (Cont.) PWM Compensation (Cont.) C1 The PWM modulator is shown in Figure 8. The input R3 is the output of the error amplifier and the output is the R1 modulator is given by: V COMP FB Figure 9. Compensation Network VIN The closed loop gain of the converter can be written Driver as: PWM Comparator ΔVOSC C2 V REF VIN1 ∆VOSC OSC R2 V OUT1 PHASE node. The transfer function of the PWM GAINPWM = C3 GAINLC X GAINPWM X GAINAMP PHASE Output of Error Amplifier Figure 10. shows the asymptotic plot of the closed loop converter gain, and the following guidelines will help to design the compensation network. Using the Driver below guidelines should give a compensation similar Figure 8. The PWM Modulator to the curve plotted. A stable closed loop has a -20dB/ The compensation network is shown in Figure 9. It decade slope and a phase margin greater than 45 provides a close loop transfer function with the highest degree. zero crossover frequency and sufficient phase margin. 1.Choose a value for R1, usually between 1K and 5K. The transfer function of error amplifier is given by: GAINAMP = VCOMP VOUT1 2.Select the desired zero crossover frequency FO: 1 1 // R2 + sC1 sC2 = 1 R1// R3 + sC3 (1/5 ~ 1/10) X FS >FO>FESR Use the following equation to calculate R2: 1 1 s + × s + ( R2 × C2 R1 + R3 ) × C3 R1 + R3 = × C1 + C2 1 R1 × R3 × C1 s s + × s + R2 × C1 × C2 R3 × C3 R2 = 3.Place the first zero FZ1 before the output LC filter double pole frequency FLC. FZ1 = 0.75 X FLC The poles and zeros of the transfer function are: 1 F Z1 = 2 × π × R2 × C2 1 FZ2 = 2 × π × (R1 + R3 ) × C3 1 FP1 = C1 × C2 2 × π × R2 × C1 + C2 FP2 = Calculate the C2 by the equation: C2 = 1 2 × π × R2 × FLC × 0.75 4.Set the pole at the ESR zero frequency FESR: FP1 = FESR Calculate the C1 by the equation: 1 2 × π × R3 × C3 Copyright ANPEC Electronics Corp. Rev. A.2 - Jun., 2006 ∆VOSC FO × × R1 VIN FLC C1 = 16 C2 2 × π × R2 × C2 × FESR − 1 www.anpec.com.tw APW7068 Application Information (Cont.) PWM Compensation (Cont.) and ripple voltage can be approximated by: 5.Set the second pole FP2 at the half of the switching IRIPPLE = frequency and also set the second zero FZ2 at the output LC filter double pole FLC. The compensation VIN1 − VOUT1 VOUT1 × FS × L VIN1 ∆VOUT1 = IRIPPLE × ESR gain should not exceed the error amplifier open loop where Fs is the switching frequency of the regulator. gain, check the compensation gain at FP2 with the Although increase of the inductor value and frequency capabilities of the error amplifier. reduces the ripple current and voltage, a tradeoff will FP2 = 0.5 X FS exist between the inductor’s ripple current and the regulator load transient response time. FZ2 = FLC Combine the two equations will get the following A smaller inductor will give the regulator a faster load component calculations: transient response at the expense of higher ripple R3 = current. Increasing the switching frequency (FS) also R1 FS −1 2 × FLC reduces the ripple current and voltage, but it will increase the switching loss of the MOSFET and the 1 C3 = π × R3 × FS power dissipation of the converter. The maximum ripple current occurs at the maximum input voltage. A good starting point is to choose the ripple current to be approximately 30% of the maximum output current. F Z1 F Z2 F P1 Once the inductance value has been chosen, select F P2 an inductor that is capable of carrying the required GAIN (dB) peak current without going into saturation. In some 20log (R2/R1) 20log (VIN /ΔV OSC ) types of inductors, especially core that is made of Compensation Gain ferrite, the ripple current will increase abruptly when it saturates. This will result in a larger output ripple voltage. Output Capacitor Selection F LC F ESR PWM & Filter Gain Converter Gain Higher capacitor value and lower ESR reduce the output ripple and the load transient drop. Therefore, selecting high performance low ESR capacitors is Frequency(Hz) intended for switching regulator applications. In some applications, multiple capacitors have to be parallel to Figure 10. Converter Gain and Frequency achieve the desired ESR value. A small decoupling Output Inductor Selection capacitor in parallel for bypassing the noise is also The inductor value determines the inductor ripple recommended, and the voltage rating of the output current and affects the load transient response. Higher capacitors also must be considered. If tantalum inductor value reduces the inductor’s ripple current and capacitors are used, make sure they are surge tested induces lower output ripple voltage. The ripple current Copyright ANPEC Electronics Corp. Rev. A.2 - Jun., 2006 17 www.anpec.com.tw APW7068 Application Information (Cont.) Output Capacitor Selection (Cont.) capacitor 1uF can be connected between the drain of by the manufactures. If in doubt, consult the capacitors upper MOSFET and the source of lower MOSFET. manufacturer. MOSFET Selection Input Capacitor Selection The selection of the N-channel power MOSFETs are The input capacitor is chosen based on the voltage determined by the RDS(ON), reverse transfer capacitance rating and the RMS current rating. For reliable (CRSS) and maximum output current requirement. There operation, select the capacitor voltage rating to be at are two components of loss in the MOSFETs: least 1.3 times higher than the maximum input voltage. conduction loss and transition loss. For the upper The maximum RMS current rating requirement is and lower MOSFET, the losses are approximately approximately IOUT1/2, where IOUT1 is the load current. given by the following: During power up, the input capacitors have to handle PUPPER = IOUT1 (1+ TC)(RDS(ON))D + (0.5)( IOUT1)(VIN1)( tSW)FS large amount of surge current. If tantalum capacitors are used, make sure they are surge tested by the PLOWER = IOUT1 (1+ TC)(RDS(ON))(1-D) manufactures. If in doubt, consult the capacitors Where IOUT1 is the load current manufacturer. For high frequency decoupling, a ceramic TC is the temperature dependency of RDS(ON) capacitor 1uF can be connected between the drain of FS is the switching frequency upper MOSFET and the source of lower MOSFET. applications, multiple capacitors have to be parallel to tSW is the switching interval D is the duty cycle achieve the desired ESR value. A small decoupling capacitor in parallel for bypassing the noise is also Note that both MOSFETs have conduction loss while recommended, and the voltage rating of the output the upper MOSFET include an additional transition capacitors also must be considered. If tantalum loss. The switching internal, tSW , is a function of the capacitors are used, make sure they are surge tested reverse transfer capacitance C RSS. The (1+TC) term is by the manufactures. If in doubt, consult the capacitors to factor in the temperature dependency of the RDS(ON) manufacturer. and can be extracted from the “RDS(ON) vs Temperature” curve of the power MOSFET. Input Capacitor Selection Layout Considerations The input capacitor is chosen based on the voltage In any high switching frequency converter, a correct rating and the RMS current rating. For reliable layout is important to ensure proper operation of the operation, select the capacitor voltage rating to be at regulator. With power devices switching at 300KHz or above, the resulting current transient will cause volt- least 1.3 times higher than the maximum input voltage. The maximum RMS current rating requirement is age spike across the interconnecting impedance and approximately IOUT1/2, where IOUT1 is the load current. parasitic circuit elements. As an example, consider During power up, the input capacitors have to handle the turn-off transition of the PWM MOSFET. Before large amount of surge current. If tantalum capacitors turn-off, the MOSFET is carrying the full load current. are used, make sure they are surge tested by the During turn-off, current stops flowing in the MOSFET manufactures. If in doubt, consult the capacitors and is free-wheeling by the lower MOSFET and para- manufacturer. For high frequency decoupling, a ceramic Copyright ANPEC Electronics Corp. Rev. A.2 - Jun., 2006 sitic diode. Any parasitic inductance of the circuit gen18 www.anpec.com.tw APW7068 Application Information (Cont.) Layout Considerations (Cont.) the upper MOSFET; the output capacitor should be erates a large voltage spike during the switching near the loads. The input capacitor GND should interval. In general, using short, wide printed circuit be close to the output capacitor GND and the lower traces should minimize interconnecting imped- MOSFET GND. ances and the magnitude of voltage spike. And signal - The drain of the MOSFETs (VIN1 and PHASE nodes) and power grounds are to be kept separate till com- should be a large plane for heat sinking. bined using ground plane construction or single point grounding. Figure 11. illustrates the layout, with bold APW7068 lines indicating high current paths; these traces must VIN1 be short and wide. Components along the bold lines VCC12 VIN2 should be placed lose together. Below is a checklist BOOT for your layout: - The metal plate of the bottom of the packages DRIVE UGATE FBL PHASE VOUT2 (QFN-16) must be soldered to the PCB and con- L O A D nected to the GND plane on the backside through L O A D LGATE REF_OUT VOUT1 several thermal vias. - Keep the switching nodes (UGATE, LGATE and Figure 11. Layout Guidelines PHASE) away from sensitive small signal nodes since these nodes are fast moving signals. Therefore, keep traces to these nodes as short as possible. - The traces from the gate drivers to the MOSFETs (UG, LG, DRIVE) should be short and wide. - Place the source of the high-side MOSFET and the drain of the low-side MOSFET as close as possible. Minimizing the impedance with wide layout plane between the two pads reduces the voltage bounce of the node. - Decoupling capacitor, compensation component, the resistor dividers, boot capacitors, and REF_OUT capacitors should be close their pins. (For example, place the decoupling ceramic capacitor near the drain of the high-side MOSFET as close as possible. The bulk capacitors are also placed near the drain). - The input capacitor should be near the drain of Copyright ANPEC Electronics Corp. Rev. A.2 - Jun., 2006 19 www.anpec.com.tw APW7068 Package Information 0.015 x 45 E H SOP – 14 (150mil) C D A Dim A A1 B C D E e H L θ° B 0.010 e GAUGE PLANE SEATING PLANE A1 Millimeters Min. 1.477 0.102 0.331 0.191 8.558 3.82 Inches Max. 1.732 0.255 0.509 0.2496 8.762 3.999 Min. 0.058 0.004 0.013 0.0075 0.336 0.150 1.274 5.808 0.382 0° Copyright ANPEC Electronics Corp. Rev. A.2 - Jun., 2006 L Max. 0.068 0.010 0.020 0.0098 0.344 0.157 0.050 6.215 1.274 8° 20 0.228 0.015 0° 0.244 0.050 8° www.anpec.com.tw APW7068 Package Information QSOP-16 D E GAUGE PLANE E1 1 2 3 A e b L Millimeters Dim A A1 b D E E1 e L φ1 1 A1 Min. 1.35 0.10 0.20 4.80 5.79 3.81 Inches Max. 1.75 0.25 0.30 5.00 6.20 3.99 Min. 0.053 0.004 0.008 0.189 0.228 0.150 0.635 TYP. 0.41 0° Copyright ANPEC Electronics Corp. Rev. A.2 - Jun., 2006 Max. 0.069 0.010 0.012 0.197 0.244 0.157 0.025 TYP. 1.27 8° 0.016 0° 21 0.050 8° www.anpec.com.tw APW7068 Packaging Information QFN-16 e b E E2 L D D2 A2 A A A1 A2 A3 D E b D2 E2 e L A1 A3 Dim Millimeters Min. 0.76 0.00 0.57 Inches Max. 0.84 0.04 0.63 Min. 0.030 0.00 0.022 0.20 REF. 3.90 3.90 0.25 2.05 2.05 0.008 REF. 4.10 4.10 0.35 2.15 2.15 0.154 0.154 0.010 0.081 0.081 0.60 0.002 0.650 BSC 0.50 Copyright ANPEC Electronics Corp. Rev. A.2 - Jun., 2006 Max. 0.033 0.0015 0.025 0.161 0.161 0.014 0.085 0.085 0.0257BSC 22 0.024 www.anpec.com.tw APW7068 Physical Specifications Terminal Material Lead Solderability Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb), 100%Sn Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3. Reflow Condition (IR/Convection or VPR Reflow) tp TP Critical Zone T L to T P Temperature Ramp-up TL tL Tsmax Tsmin Ramp-down ts Preheat 25 t 25 °C to Peak Tim e Classification Reflow Profiles Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (TL) - Time (tL) Peak/Classificatioon Temperature (Tp) Time within 5°C of actual Peak Temperature (tp) Ramp-down Rate Sn-Pb Eutectic Assembly Pb-Free Assembly 3°C/second max. 3°C/second max. 100°C 150°C 60-120 seconds 150°C 200°C 60-180 seconds 183°C 60-150 seconds 217°C 60-150 seconds See table 1 See table 2 10-30 seconds 20-40 seconds 6°C/second max. 6°C/second max. 6 minutes max. 8 minutes max. Time 25°C to Peak Temperature Notes: All temperatures refer to topside of the package. Measured on the body surface. Copyright ANPEC Electronics Corp. Rev. A.2 - Jun., 2006 23 www.anpec.com.tw APW7068 Classification Reflow Profiles(Cont.) Table 1. SnPb Entectic Process – Package Peak Reflow Temperatures 3 3 Package Thickness Volum e m m Volume mm <350 ≥350 <2.5 m m 240 +0/-5°C 225 +0/-5°C ≥2.5 m m 225 +0/-5°C 225 +0/-5°C Table 2. Pb-free Process – Package Classification Reflow Temperatures 3 3 3 Package Thickness Volume mm Volume mm Volume mm <350 350-2000 >2000 <1.6 m m 260 +0°C* 260 +0°C* 260 +0°C* 1.6 m m – 2.5 m m 260 +0°C* 250 +0°C* 245 +0°C* ≥2.5 m m 250 +0°C* 245 +0°C* 245 +0°C* *Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0°C. For example 260°C+0°C) at the rated MSL level. Reliability Test Program Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B,A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Description 245°C, 5 SEC 1000 Hrs Bias @125°C 168 Hrs, 100%RH, 121°C -65°C~150°C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms, 1 tr > 100mA Carrier Tape & Reel Dimensions t D P Po E P1 Bo F W Ko Ao Copyright ANPEC Electronics Corp. Rev. A.2 - Jun., 2006 D1 24 www.anpec.com.tw APW7068 Carrier Tape & Reel Dimensions(Cont.) T2 J C A B T1 Application SOP-14 (150mil) A B 330REF 100REF F D 7.5 Application QSOP- 16 C 13.0 + 0.5 - 0.2 D1 φ0.50 + 0.1 φ1.50 (MIN) A B 330 ± 1 62 +1.5 F D 5.5± 1 1.55 +0.1 C J T1 2 ± 0.5 16.5REF Po P1 Ao Ko t 4.0 2.0 6.5 2.10 0.3±0.05 J T1 T2 W P E 12.4 ± 0.2 2 ± 0.2 12± 0. 3 8± 0.1 1.75±0.1 P1 Ao Bo Ko t 6.4 ± 0.1 5.2± 0. 1 12.75+ 0.15 2 ± 0.5 D1 Po 1.55+ 0.25 4.0 ± 0.1 2.0 ± 0.1 T2 W 2.5 ± 025 16.0 ± 0.3 P E 8 1.75 2.1± 0.1 0.3±0.013 (mm) 4x4 Shipping Tray Copyright ANPEC Electronics Corp. Rev. A.2 - Jun., 2006 25 www.anpec.com.tw APW7068 4x4 Shipping Tray (Cont.) Cover Tape Dimensions Application SOP- 14 QSOP- 16 Carrier Width 24 12 Cover Tape Width 21.3 9.3 Devices Per Reel 2500 2500 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 7F, No. 137, Lane 235, Pac Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, R. O. C. Tel : 886-2-89191368 Fax : 886-2-89191369 Copyright ANPEC Electronics Corp. Rev. A.2 - Jun., 2006 26 www.anpec.com.tw