NIKO-SEM P8006EDG P-Channel Logic Level Enhancement TO-252 Lead-Free Mode Field Effect Transistor D PRODUCT SUMMARY V(BR)DSS RDS(ON) ID -55V 80mΩ -8A 1. GATE 2. DRAIN 3. SOURCE G S ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS SYMBOL LIMITS UNITS Drain-Source Voltage VDS -55 V Gate-Source Voltage VGS ±20 V TC = 25 °C Continuous Drain Current TC = 70 °C Pulsed Drain Current -7 ID 1 -6 IDM TC = 25 °C Power Dissipation 28 PD TC = 70 °C Operating Junction & Storage Temperature Range 1 Lead Temperature ( /16” from case for 10 sec.) A -30 W 18 Tj, Tstg -55 to 150 TL 275 °C THERMAL RESISTANCE RATINGS THERMAL RESISTANCE SYMBOL TYPICAL MAXIMUM UNITS Junction-to-Case RθJc 3 °C / W Junction-to-Ambient RθJA 75 °C / W 1 Pulse width limited by maximum junction temperature. Duty cycle ≤ 1% 2 ELECTRICAL CHARACTERISTICS (TC = 25 °C, Unless Otherwise Noted) PARAMETER SYMBOL TEST CONDITIONS LIMITS UNIT MIN TYP MAX STATIC Drain-Source Breakdown Voltage V(BR)DSS VGS = 0V, ID = -250µA -55 VGS(th) VDS = VGS, ID = -250µA -1 Gate-Body Leakage IGSS VDS = 0V, VGS = ±20V Zero Gate Voltage Drain Current IDSS Gate Threshold Voltage On-State Drain Current1 ID(ON) V -1.5 -2.5 ±250 nA VDS = -44V, VGS = 0V 1 VDS = -36V, VGS = 0V, TJ = 125 °C 10 VDS = -5V, VGS = -10V -32 µA A AUG-19-2004 1 NIKO-SEM P8006EDG P-Channel Logic Level Enhancement TO-252 Lead-Free Mode Field Effect Transistor Drain-Source On-State Resistance1 Forward Transconductance1 RDS(ON) gfs VGS = -4.5V, ID = -6A 90 150 VGS = -10V, ID = -7A 60 80 VDS = -10V, ID = -7A 9 mΩ S DYNAMIC Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss 40 Qg 15 Total Gate Charge 2 Gate-Source Charge 2 Gate-Drain Charge2 Turn-On Delay Time 2 Rise Time2 Turn-Off Delay Time2 Fall Time2 760 VGS = 0V, VDS = -30V, f = 1MHz pF 90 Qgs VDS = 0.5V(BR)DSS, VGS = -10V, 2.5 Qgd ID = -7A 3.0 td(on) nC 7 14 tr VDS = -20V, RL = 1Ω 10 20 td(off) ID ≅ -1A, VGS = -10V, RGS = 6Ω 19 34 12 22 tf nS SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TC = 25 °C) Continuous Current IS -1.3 Pulsed Current ISM -2.6 Forward Voltage1 VSD IF = IS, VGS = 0V Reverse Recovery Time trr IF = -7 A, dlF/dt = 100A / µS Reverse Recovery Charge Qrr 3 -1 A V 15.5 nS 7.9 nC Pulse test : Pulse Width ≤ 300 µsec, Duty Cycle ≤ 2％. Independent of operating temperature. 3 Pulse width limited by maximum junction temperature. 1 2 REMARK: THE PRODUCT MARKED WITH “P8006EDG”, DATE CODE or LOT # Orders for parts with Lead-Free plating can be placed using the PXXXXXXG parts name. AUG-19-2004 2 NIKO-SEM P-Channel Logic Level Enhancement P8006EDG TO-252 Lead-Free Mode Field Effect Transistor TYPICAL PERFORMANCE CHARACTERISTICS Body Diode Forward Voltage Variation with Source Current and Temperature 100 V GS = 0V -Is - Reverse Drain Current(A) 10 1 T A = 125° C 0.1 25° C -55° C 0.01 0.001 0 0.2 0.6 0.8 1.0 0.4 -VSD - Body Diode Forward Voltage(V) 1.2 1.4 AUG-19-2004 3 NIKO-SEM P-Channel Logic Level Enhancement Mode Field Effect Transistor P8006EDG TO-252 Lead-Free AUG-19-2004 4 NIKO-SEM P8006EDG P-Channel Logic Level Enhancement TO-252 Lead-Free Mode Field Effect Transistor TO-252 (DPAK) MECHANICAL DATA mm mm Dimension Dimension Min. Typ. Max. Min. Typ. Max. A 9.35 10.4 H 0.89 2.03 B 2.2 2.4 I 6.35 6.80 C 0.45 0.6 J 5.2 5.5 D 0.89 1.5 K 0.6 1 E 0.45 0.69 L 0.5 0.9 F 0.03 0.23 M 3.96 G 5.2 6.2 N 4.57 5.18 G M 2 1 J I 3 L H D C E F B A K AUG-19-2004 5