P8503BMG N-Channel Logic Level Enhancement Mode Field Effect Transistor (Preliminary) NIKO-SEM SOT-23 Lead Free D PRODUCT SUMMARY V(BR)DSS RDS(ON) ID 25 85mΩ 3A 1. GATE 2. DRAIN 3. SOURCE G S ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS Gate-Source Voltage TC = 25 °C Continuous Drain Current SYMBOL LIMITS UNITS VGS ±20 V 3 ID TC = 100 °C Pulsed Drain Current 2 1 IDM TC = 25 °C Power Dissipation A 20 0.6 PD TC = 100 °C W 0.5 Operating Junction & Storage Temperature Range Lead Temperature (1/16” from case for 10 sec.) Tj, Tstg -55 to 150 TL 275 °C THERMAL RESISTANCE RATINGS THERMAL RESISTANCE SYMBOL TYPICAL MAXIMUM Junction-to-Case RθJC 65 Junction-to-Ambient RθJA 230 UNITS °C / W 1 Pulse width limited by maximum junction temperature. Duty cycle ≤ 1% 2 ELECTRICAL CHARACTERISTICS (TC = 25 °C, Unless Otherwise Noted) PARAMETER SYMBOL TEST CONDITIONS LIMITS UNIT MIN TYP MAX STATIC Drain-Source Breakdown Voltage V(BR)DSS VGS = 0V, ID = 250µA 25 VGS(th) VDS = VGS, ID = 250µA 0.8 Gate-Body Leakage IGSS VDS = 0V, VGS = ±20V ±100 Zero Gate Voltage Drain Current IDSS VDS = 20V, VGS = 0V 1 VDS = 20V, VGS = 0V, TJ = 125 °C 10 Gate Threshold Voltage On-State Drain Current 1 Drain-Source On-State Resistance1 ID(ON) RDS(ON) VDS = 10V, VGS = 10V V 1.2 2.5 3 µA A VGS = 4.5V, ID = 1.5A 70 115 VGS = 10V, ID = 3A 48 85 1 nA mΩ Nov-03-2004 N-Channel Logic Level Enhancement Mode Field Effect Transistor (Preliminary) NIKO-SEM Forward Transconductance1 gfs P8503BMG SOT-23 Lead Free VDS = 15V, ID = 3A 16 S DYNAMIC Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss 60 Total Gate Charge Qg 15 Gate-Source Charge2 Qgs VDS = 0.5V (BR)DSS, VGS = 10V, 2.0 Gate-Drain Charge2 Qgd ID = 3A 7.0 2 2 Turn-On Delay Time 450 VGS = 0V, VDS = 15V, f = 1MHz td(on) tr VDS = 15V, RL = 1Ω 6.0 Turn-Off Delay Time2 td(off) ID ≅ 3A, VGS = 10V, RGS = 2.5Ω 20 Fall Time2 nC 6.0 2 Rise Time pF 200 tf nS 5.0 SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TC = 25 °C) Continuous Current IS 2.3 Pulsed Current 3 ISM 4.6 Forward Voltage1 VSD IF = IS, VGS = 0V 1.5 A V Pulse test : Pulse Width ≤ 300 µsec, Duty Cycle ≤ 2%. Independent of operating temperature. 3 Pulse width limited by maximum junction temperature. 1 2 REMARK: THE PRODUCT MARKED WITH “10YWW”, DATE CODE or LOT # Orders for parts with Lead-Free plating can be placed using the PXXXXXXXG parts name 2 Nov-03-2004 P8503BMG N-Channel Logic Level Enhancement Mode Field Effect Transistor (Preliminary) NIKO-SEM SOT-23 Lead Free SOT-23 (M3) MECHANICAL DATA mm mm Dimension Dimension Min. Typ. Max. Min. Typ. Max. 0.15 0.25 A 0.85 1.15 H 0.1 B 2.4 3 I 0.37 C 1.4 1.6 1.8 J D 2.7 2.9 3.1 K E 1 1.1 1.3 L F 0 0.1 M G 0.35 0.5 N H 2 C 1 3 B A I D E G F 3 Nov-03-2004