P06P03LDG P-Channel Logic Level Enhancement NIKO-SEM Mode Field Effect Transistor TO-252 Lead-Free D PRODUCT SUMMARY V(BR)DSS RDS(ON) ID -30 45mΩ -12A 1. GATE 2. DRAIN 3. SOURCE G S ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS SYMBOL LIMITS UNITS Drain-Source Voltage VDS -30 V Gate-Source Voltage VGS ±20 V TC = 25 °C Continuous Drain Current TC = 70 °C Pulsed Drain Current -12 ID 1 -10 IDM TC = 25 °C Power Dissipation -30 48 PD TC = 70 °C Operating Junction & Storage Temperature Range A W 20 Tj, Tstg -55 to 150 °C THERMAL RESISTANCE RATINGS THERMAL RESISTANCE SYMBOL TYPICAL MAXIMUM UNITS Junction-to-Case RθJc 3 °C / W Junction-to-Ambient RθJA 75 °C / W 1 Pulse width limited by maximum junction temperature. Duty cycle ≤ 1% ELECTRICAL CHARACTERISTICS (TC = 25 °C, Unless Otherwise Noted) 2 PARAMETER SYMBOL TEST CONDITIONS LIMITS UNIT MIN TYP MAX STATIC Drain-Source Breakdown Voltage V(BR)DSS VGS = 0V, ID = -250µA -30 VGS(th) VDS = VGS, ID = -250µA -1 Gate-Body Leakage IGSS VDS = 0V, VGS = ±20V Zero Gate Voltage Drain Current IDSS Gate Threshold Voltage On-State Drain Current1 ID(ON) Drain-Source On-State Resistance1 RDS(ON) Forward Transconductance1 gfs V -1.5 -3.0 ±250 nA VDS = -24V, VGS = 0V 1 VDS = -20V, VGS = 0V, TJ = 125 °C 10 VDS = -5V, VGS = -10V -30 µA A VGS = -4.5V, ID =- 10A 60 75 VGS = -10V, ID = -12A 37 45 VDS = -10V, ID = -12A 16 mΩ S AUG-17-2004 1 P-Channel Logic Level Enhancement NIKO-SEM P06P03LDG Mode Field Effect Transistor TO-252 Lead-Free DYNAMIC Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss 70 Qg 10 Total Gate Charge 2 Gate-Source Charge2 Gate-Drain Charge 2 Turn-On Delay Time Rise Time 2 2 Turn-Off Delay Time 2 Fall Time2 530 VGS = 0V, VDS = -15V, f = 1MHz pF 135 Qgs VDS = 0.5V(BR)DSS, VGS = -10V, 2.2 Qgd ID = -12A 2 td(on) 14 nC 5.7 tr VDS = -15V, RL = 1Ω 10 td(off) ID ≅ -1A, VGS = -10V, RGS = 6Ω 18 tf nS 5 SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TC = 25 °C) Continuous Current IS -12 Pulsed Current3 ISM -30 Forward Voltage1 VSD IF = -1A, VGS = 0V Reverse Recovery Time trr IF = -5A, dlF/dt = 100A / µS Reverse Recovery Charge Qrr -1.2 A V 15.5 nS 7.9 nC Pulse test : Pulse Width ≤ 300 µsec, Duty Cycle ≤ 2％. Independent of operating temperature. 3 Pulse width limited by maximum junction temperature. 1 2 REMARK: THE PRODUCT MARKED WITH “P06P03LDG”, DATE CODE or LOT # Orders for parts with Lead-Free plating can be placed using the PXXXXXXXG parts name AUG-17-2004 2 NIKO-SEM P-Channel Logic Level Enhancement Mode Field Effect Transistor P06P03LDG TO-252 Lead-Free Typical Characteristics AUG-17-2004 3 NIKO-SEM P-Channel Logic Level Enhancement Mode Field Effect Transistor P06P03LDG TO-252 Lead-Free AUG-17-2004 4 P-Channel Logic Level Enhancement NIKO-SEM P06P03LDG Mode Field Effect Transistor TO-252 Lead-Free TO-252 (DPAK) MECHANICAL DATA mm mm Dimension Dimension Min. Typ. Max. Min. Typ. Max. A 9.35 10.4 H 0.89 2.03 B 2.2 2.4 I 6.35 6.80 C 0.45 0.6 J 5.2 5.5 D 0.89 1.5 K 0.6 1 E 0.45 0.69 L 0.5 0.9 F 0.03 0.23 M 3.96 G 5.2 6.2 N 4.57 5.18 G M 2 1 J I 3 L H D C E F B A K AUG-17-2004 5