P3057LCG N-Channel Logic Level Enhancement Mode Field Effect Transistor NIKO-SEM SOT-89 Lead-Free 3 D RDS(ON) ID 25 50mΩ 6A 1. GATE 2. DRAIN 3. SOURCE G 1 V(BR)DSS 2 PRODUCT SUMMARY S ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS Gate-Source Voltage TC = 25 °C Continuous Drain Current Pulsed Drain Current SYMBOL LIMITS UNITS VGS ±20 V 6 ID TC = 100 °C 1 4 IDM TC = 25 °C Power Dissipation 20 3 PD TC = 100 °C Operating Junction & Storage Temperature Range 1 Lead Temperature ( /16” from case for 10 sec.) A W 1.2 Tj, Tstg -55 to 150 TL 275 °C THERMAL RESISTANCE RATINGS THERMAL RESISTANCE SYMBOL TYPICAL MAXIMUM Junction-to-Case RθJC 18 Junction-to-Ambient RθJA 160 UNITS °C / W 1 Pulse width limited by maximum junction temperature. Duty cycle ≤ 1% 2 ELECTRICAL CHARACTERISTICS (TC = 25 °C, Unless Otherwise Noted) PARAMETER SYMBOL TEST CONDITIONS LIMITS UNIT MIN TYP MAX STATIC Drain-Source Breakdown Voltage V(BR)DSS VGS = 0V, ID = 250µA 25 VGS(th) VDS = VGS, ID = 250µA 0.8 Gate-Body Leakage IGSS VDS = 0V, VGS = ±20V Zero Gate Voltage Drain Current IDSS On-State Drain Current1 ID(ON) Drain-Source On-State Resistance1 RDS(ON) Gate Threshold Voltage Forward Transconductance1 1.2 2.5 ±250 nA VDS = 20V, VGS = 0V 25 VDS = 20V, VGS = 0V, TJ = 125 °C 250 VDS = 10V, VGS = 10V gfs 1 V 6 µA A VGS = 4.5V, ID = 3A 70 115 VGS = 10V, ID = 6A 48 85 VDS = 15V, ID = 6A 16 mΩ S Jun-29-2004 N-Channel Logic Level Enhancement Mode Field Effect Transistor NIKO-SEM P3057LCG SOT-89 Lead-Free DYNAMIC Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss 60 Qg 15 Total Gate Charge 2 Gate-Source Charge Gate-Drain Charge 2 2 Turn-On Delay Time 2 Rise Time2 Turn-Off Delay Time2 Fall Time2 450 VGS = 0V, VDS = 15V, f = 1MHz Qgs VDS = 0.5V(BR)DSS, VGS = 10V, 2.0 Qgd ID = 6A 7.0 td(on) pF 200 nC 6.0 tr VDS = 15V, RL = 1Ω 6.0 td(off) ID ≅ 12A, VGS = 10V, RGS = 2.5Ω 20 tf nS 5.0 SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TC = 25 °C) Continuous Current IS 2.3 Pulsed Current3 ISM 4 Forward Voltage1 VSD IF = IS, VGS = 0V 1.5 A V 1 Pulse test : Pulse Width ≤ 300 µsec, Duty Cycle ≤ 2%. Independent of operating temperature. 3 Pulse width limited by maximum junction temperature. 2 REMARK: THE PRODUCT MARKED WITH “P3057G”, DATE CODE or LOT # Orders for parts with Lead-Free plating can be placed using the PXXXXXXG parts name. 2 Jun-29-2004 NIKO-SEM N-Channel Logic Level Enhancement Mode Field Effect Transistor 3 P3057LCG SOT-89 Lead-Free Jun-29-2004 N-Channel Logic Level Enhancement Mode Field Effect Transistor NIKO-SEM P3057LCG SOT-89 Lead-Free SOT-89 MECHANICAL DATA Dimension mm Min. Typ. Max. A 4.3 4.5 4.7 B 1.6 1.7 C 0.4 D Dimension mm Min. Typ. Max. H 1.4 1.5 1.6 1.8 I 2.8 3.0 3.2 0.5 0.6 J 1.3 1.5 1.7 2.4 2.5 2.6 K 3.8 4.2 4.6 E 0.8 1.2 1.4 L 0.3 0.4 0.5 F 0.4 0.45 0.5 M G 0.4 0.5 0.6 N 4 Jun-29-2004