P7502CMG N-Channel Logic Level Enhancement Mode Field Effect Transistor NIKO-SEM SOT-23 Lead-Free D PRODUCT SUMMARY V(BR)DSS RDS(ON) ID 20 75mΩ 3A 1. GATE 2. DRAIN 3. SOURCE G S ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS Gate-Source Voltage TC = 25 °C Continuous Drain Current LIMITS UNITS VGS ±12 V 3 ID TC = 100 °C Pulsed Drain Current SYMBOL 1 2 IDM TC = 25 °C Power Dissipation 20 0.6 PD TC = 100 °C Operating Junction & Storage Temperature Range 1 Lead Temperature ( /16” from case for 10 sec.) A W 0.5 Tj, Tstg -55 to 150 TL 275 °C THERMAL RESISTANCE RATINGS THERMAL RESISTANCE SYMBOL TYPICAL MAXIMUM Junction-to-Case RθJC 65 Junction-to-Ambient RθJA 230 UNITS °C / W 1 Pulse width limited by maximum junction temperature. Duty cycle ≤ 1% 2 ELECTRICAL CHARACTERISTICS (TC = 25 °C, Unless Otherwise Noted) PARAMETER SYMBOL TEST CONDITIONS LIMITS UNIT MIN TYP MAX STATIC Drain-Source Breakdown Voltage V(BR)DSS VGS = 0V, ID = 250µA VGS(th) VDS = VGS, ID = 250µA Gate-Body Leakage IGSS VDS = 0V, VGS = ±12V Zero Gate Voltage Drain Current IDSS Gate Threshold Voltage On-State Drain Current1 ID(ON) Drain-Source On-State Resistance1 RDS(ON) Forward Transconductance1 20 V 0.45 0.75 1.2 ±100 nA VDS = 16V, VGS = 0V 1 VDS = 16V, VGS = 0V, TJ = 125 °C 10 VDS = 10V, VGS = 10V 3 A VGS = 2.5V, ID = 1.5A 70 105 VGS = 4.5V, ID = 3A 50 75 VDS = 15V, ID = 3A 16 gfs 1 µA mΩ S AUG-04-2004 N-Channel Logic Level Enhancement Mode Field Effect Transistor NIKO-SEM P7502CMG SOT-23 Lead-Free DYNAMIC Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss 60 Qg 15 Total Gate Charge 2 Gate-Source Charge Gate-Drain Charge 2 2 Turn-On Delay Time 2 Rise Time2 Turn-Off Delay Time Fall Time2 2 450 VGS = 0V, VDS = 15V, f = 1MHz Qgs VDS = 0.5V(BR)DSS, VGS = 10V, 2.0 Qgd ID = 3A 7.0 td(on) pF 200 nC 6.0 tr VDS = 15V, 6.0 td(off) ID ≅ 1A, VGS = 10V, RGS = 2.5Ω 20 tf nS 5.0 SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TC = 25 °C) Continuous Current IS 2.3 Pulsed Current ISM 4.6 Forward Voltage1 VSD 3 IF = IS, VGS = 0V 1.5 A V Pulse test : Pulse Width ≤ 300 µsec, Duty Cycle ≤ 2%. Independent of operating temperature. 3 Pulse width limited by maximum junction temperature. 1 2 REMARK: THE PRODUCT MARKED WITH “11YWW”, DATE CODE or LOT # Orders for parts with Lead-Free plating can be placed using the PXXXXXXG parts name 2 AUG-04-2004 P7502CMG N-Channel Logic Level Enhancement Mode Field Effect Transistor SOT-23 Lead-Free Body Diode Forward Voltage Variation with Source Current and Temperature 100 VGS= 0V 10 Is - Reverse Drain Current(A) NIKO-SEM T = 125° C 1 25° C 0.1 -55° C 0.01 0.001 0.0001 0 3 0.2 0.4 0.8 0.6 VSD - Body Diode Forward Voltage(V) 1.0 1.2 AUG-04-2004 NIKO-SEM N-Channel Logic Level Enhancement Mode Field Effect Transistor 4 P7502CMG SOT-23 Lead-Free AUG-04-2004 N-Channel Logic Level Enhancement Mode Field Effect Transistor NIKO-SEM P7502CMG SOT-23 Lead-Free SOT-23 (M3) MECHANICAL DATA mm mm Dimension Dimension Min. Typ. A Max. 0.95 Min. Typ. Max. H 0.10 0.15 0.25 0.37 B 2.60 2.80 3.00 I C 1.40 1.60 1.80 J D 2.70 2.90 3.10 K E 1.00 1.10 1.30 L F 0.00 0.10 M G 0.35 0.5 N 0.4 H 2 C 1 B 3 A I D E F G 5 AUG-04-2004