74F525 Programmable Counter General Description Features The ’F525 is a multi-function 28-pin device. It consists of a 16-bit count-down counter, logic to control the counter, logic to control the state of the outputs and a PLA to decode the particular function selected by the user. The list of highspeed timing applications include: Y Y Y Y Y Y Y Commercial Package Number Baud rate generator Digitally programmed monostable Variable system frequency generator Digital filter variable sampling rate 16-bit data path External trigger Extremely accurate one shot w/pulse widths from 50 ns to 3.27 ms @ CP e 40 MHz Package Description 74F525QC (Note 1) V28A 28-Lead Molded Plastic Leaded Chip Carrier 74F525SC (Note 1) M28B 28-Lead (0.300× Wide) Molded Small Outline, JEDEC 74F525PC N28B 28-Lead (0.600× Wide) Molded Dual-In-Line Package Note 1: Devices also available in 13× reel. Use suffix e SCX and QCX. Connection Diagrams Pin Assignment DIP and SOIC Pin Assignment for PCC TL/F/9547 – 3 TL/F/9547 – 2 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/9547 RRD-B30M105/Printed in U. S. A. 74F525 Programmable Counter August 1995 Logic Symbol TL/F/9547 – 1 Unit Loading/Fan Out 74F Pin Names Q Q/2 M0 – M2 MR CP D0 – D15 WE XTR XTAL Description U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL Ouput (Primarily indicates when the counter has reached zero) Output (Divides Q by 2) Status Inputs Master Reset Clock Pulse Data Inputs Write Enable Input External Trigger Input Crystal Output 50/33.3 b 1 mA/20 mA 50/33.3 1.0/1.0 1.0/1.0 1.0/2.0 1.0/1.0 1.0/1.0 1.0/2.0 1.0/1.0 b 1 mA/20 mA 20 mA/b0.6 mA 20 mA/b0.6 mA 20 mA/b1.2 mA 20 mA/b0.6 mA 20 mA/b0.6 mA 20 mA/b1.2 mA 20 mA/b0.6 mA Functional Description Q, normally LOW, is brought HIGH and Q/2 toggles state. Taking XTR HIGH at any time enables the data in the data latches to be loaded into the counter on the rising edge of CP and clears Q. See Figure 1 . The multi-function aspect of the device consists of eight different modes of operation. An explanation of the operation of the device in each of the modes follows. However, there is one operation that is independent of the selected mode: the loading of data. Data is latched into a set of data latches when WE is brought from a LOW to a HIGH state. The latches are transparent when WE is held LOW. Operation Notes: 1. Device should be reset before operation. 2. The XTR input acts as a select line for the clock. 3. With XTR low, the clock goes into the counter. 4. With XTR high, the clock loads the counter. 5. In mode 4 and 5, during counting, the counter cannot be reloaded. XTR high freezes the count. 6. Mode 7 is the only auto-reload mode, all other modes require and XTR pulse to begin. 7. Loading 0 into the latches idles the device. MODE 0: Interval Timer with Level Output While XTR is HIGH, the data in the data latches is loaded into the counter upon the next positive edge of CP. The negative edge of XTR enables the count-down to begin with the next positive edge of CP. When the count reaches zero, MODE 1: Interval Timer with Inverted Level Output The operation is exactly the same as in Mode 0 except that Q is normally HIGH and goes LOW when the count reaches zero. Q/2 toggles on the negative-edge of Q. See Figure 1 . MODE 2: Interval Timer with Pulse Output While XTR is HIGH, the data in the data latches is loaded into the counter upon the next positive edge of CP. The negative edge of XTR enables the count-down to begin with the next positive edge of CP. When the count reaches zero, Q, normally LOW, is brought HIGH for a single period of CP. Q/2 toggles state on the positive edge of Q. Taking XTR HIGH at any time causes the data in the data latches to be loaded into the counter on the rising edge of CP and clears Q. See Figure 2 . MODE 3: Interval Timer with Inverted Pulse Output The operation is exactly the same as in Mode 2 except that Q is normally HIGH and goes LOW for a single period of CP. Q/2 toggles on the negative edge of Q. See Figure 2 . 2 Functional Description (Continued) MODE 6: Retriggerable Synchronous One-Shot Function Table M2 M1 M0 Function 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 When XTR is HIGH, the data in the data latches is loaded into the counter upon the positive edge of CP. The negative edge of XTR enables the count-down to begin with the next positive edge of CP, wehre Q, normally LOW, is then brought HIGH and the counter is decremented when the count reaches zero, Q is brought LOW, and Q/2 is toggled. Bringing XTR HIGH during the count-down will allow the data in the data latches to be loaded into the counter with the next positive edge of CP, but will not affect Q. See Figure 4 . NOTE that the pulse width of Q will be N-1 clock cycles, where N is the number loaded into the counter. N e 1 should not be used as this may cause unpredictable results. MODE 7: Frequency Generator When XTR is HIGH, the data in the data latches is loaded into the counter upon the positive edge of CP. The negative edge of XTR enables the count-down to begin with the next positive edge of CP. When the count reaches zero, Q, normally LOW, is brought HIGH for a single period of CP and Q/2 is toggled. The same clock edge that brings Q HIGH, also loads the data in the data latches into the counter. The counter will start to count on the next positive edge of CP. This mode will run continuously after an initial XTR until stopped by MR. Taking XTR HIGH at any time causes the data in the data latches to be loaded into the counter and Q output to be cleared with the next positive edge of CP. See Figure 5 . MODE 4: Interval Timer, Pulse Output with Count Hold While XTR is HIGH, the data in the data latches is loaded into the counter upon the next positive edge of CP. The negative edge of XTR enables the count-down to begin with the next positive edge of CP. When the count reaches zero, Q, normally low, is brought HIGH for a single period of CP. Q/2 toggles state on the positive edge of Q. Taking XTR HIGH before the counters reach zero, stops the count-down from the point where it was held. Data cannot be reloaded into the counter until a count of zero is reached. See Figure 3. MODE 5: Interval Timer, Inverted Pulse Output with Count Hold The operation is exactly the same as Mode 4 except that Q is normally HIGH and goes LOW for a single period of CP. Q/2 toggles on the negative-edge of Q. See Figure 3 . Block Diagram TL/F/9547 – 4 3 Timing Diagrams TL/F/9547 – 5 j With XTR HIGH, the rising edge of CP loads data from the latches to the counter. k With XTR LOW, the rising edge of CP begins count-down cycle. l When the count reaches zero, Q goes HIGH, and Q/2 toggles state. m The next occurrence of XTR clears Q. FIGURE 1. MODE 0 and MODE 1 (Inverse Output of Mode 0) Mn e 000, 001 TL/F/9547 – 6 j With XTR HIGH, the rising edge of CP loads data from the latches to the counter. k With XTR LOW, the rising edge of CP begins the count-down cycle. l When the count reaches zero, Q goes HIGH for one period of CP, and Q/2 toggles state. FIGURE 2. MODE 2 and MODE 3 (Inverse Output of Mode 2) Mn e 010, 011 TL/F/9547 – 7 FIGURE 3. MODE 4 and MODE 5 Mn e 100, 101 j With XTR HIGH, the rising edge of CP loads data from the latches into the counter. k With XTR LOW, the rising edge of CP begins the count-down. l With XTR HIGH, during count-down, the rising edge of CP does nothing. m When the count reaches zero, Q goes HIGH for one clock cycle and Q/2 toggles state. Note: Once the count reaches zero, the counter can be reloaded with XTR HIGH. 4 Timing Diagrams (Continued) TL/F/9547 – 8 FIGURE 4. MODE 6 Mn e 110 j With XTR HIGH, the rising edge of CP loads data from the latches to the counter. k With XTR LOW, the rising edge of CP begins the count, and Q goes HIGH. l When the count reaches zero, Q goes LOW, and Q/2 toggles state. Bringing XTR HIGH before count reaches zero will reload the counter, but not affect Q. Notes: Loading N e 0 halts counter; loading N e 1 will result in undefined operation. Pulse width e (2/CP) * (N b 1) TL/F/9547 – 9 FIGURE 5. MODE 7 Mn e 111 j With XTR HIGH, the rising edge of CP, loads data from the latches to the counter. k On the falling edge of XTR, the rising edge of CP begins count-down. l When count reaches zero, Q goes HIGH for one period of CP, and Q/2 toggles on the Q rising edge. m On the rising edge of CP on which Q goes LOW, the counters are reloaded. n Count-down begins again. 5 Absolute Maximum Ratings (Note 1) Recommended Operating Conditions b 65§ C to a 150§ C Storage Temperature Ambient Temperature under Bias b 55§ C to a 125§ C Junction Temperature under Bias Plastic b 55§ C to a 175§ C b 55§ C to a 150§ C VCC Pin Potential to Ground Pin Free Air Ambient Temperature Commercial 0§ C to a 70§ C Supply Voltage Commercial a 4.5V to a 5.5V b 0.5V to a 7.0V b 0.5V to a 7.0V Input Voltage (Note 2) b 30 mA to a 5.0 mA Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC e 0V) b 0.5V to VCC Standard Output b 0.5V to a 5.5V TRI-STATEÉ Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol 74F Parameter Min VIH Input HIGH Voltage VIL Input LOW Voltage Typ Units VCC Conditions Max 2.0 V Recognized as a HIGH Signal 0.8 V Recognized as a LOW Signal b 1.2 V Min IIN e b18 mA V Min IOH e b1 mA IOH e b1 mA VCD Input Clamp Diode Voltage VOH Output HIGH Voltage 74F 10% VCC 74F 5% VCC VOL Output LOW Voltage 74F 10% VCC 0.5 V Min IOL e 20 mA IIH Input HIGH Current 74F 5.0 mA Max VIN e 2.7V IBVI Input HIGH Current Breakdown Test 74F 7.0 mA Max VIN e 7.0V ICEX Output HIGH Leakage Current 74F 50 mA Max VOUT e VCC VID Input Leakage Test 74F V 0.0 IID e 1.9 mA All Other Pins Grounded IOD Output Leakage Circuit Current 74F 3.75 mA 0.0 VIOD e 150 mV All Other Pins Grounded IIL Input LOW Current b 0.6 b 1.2 mA Max VIN e 0.5V (D0 – D15) VIN e 0.5V (CP, XTR) IOS Output Short-Circuit Current b 150 mA Max VOUT e 0V ICCH Power Supply Current 106 160 mA Max VO e HIGH ICCL Power Supply Current 106 160 mA Max VO e LOW 2.5 2.7 4.75 b 60 6 AC Electrical Characteristics Symbol Parameter 74F 74F TA e a 25§ C VCC e a 5.0V CL e 50 pF TA, VCC e Com CL e 50 pF Max Min Units Min Typ fmax Maximum Clock Frequency 50 60 Max tPLH tPHL Propagation Delay CP to Q 9.0 8.0 16.0 12.0 20.5 15.5 8.0 7.0 22.5 17.5 ns tPLH tPHL Propagation Delay CP to Q/2 9.0 10.0 15.5 15.5 20.0 20.0 8.0 9.0 22.0 22.0 ns tPLH tPHL Propagation Delay XTR to Q 8.5 6.0 12.0 10.5 15.5 13.5 7.5 5.0 17.5 15.0 ns tPLH tPHL Propagation Delay MR to Q 11.5 9.0 16.5 12.5 21.0 16.0 10.5 8.0 23.0 18.0 ns tPLH tPHL Propagation Delay MRto Q/2 8.0 7.0 14.0 10.5 17.5 13.5 7.0 6.0 19.5 15.0 ns tPLH tPHL Propagation Delay Mn to Q 10.0 10.5 15.0 17.0 19.0 21.5 9.0 9.5 21.0 23.5 ns 40 MHz AC Operating Requirements Symbol Parameter 74F 74F TA e a 25§ C VCC e a 5.0V TA, VCC e Com Min Max Min Units Max ts(H) ts(L) Setup Time, HIGH or LOW Dn to WE 2.0 4.0 2.5 4.5 ns th(H) th(L) Hold Time, HIGH or LOW Dn to WE 0 2.0 0 2.5 ns ts(H) ts(L) Setup Time, HIGH or LOW Dn to CP 9.0 10.5 10.0 12.0 ns th(H) th(L) Hold Time, HIGH or LOW Dn to CP 0 0 0 0 ns ts(H) ts(L) Setup Time, HIGH or LOW XTR to CP 7.0 8.0 8.0 9.0 ns th(H) Hold Time, HIGH or LOW XTR to CP 0 0 ns ts(H) ts(L) Setup Time, HIGH or LOW Mode to CP 33.5 33.5 35.5 35.5 ns tw(H) XTR Pulse Width, HIGH 11.5 13.0 ns tw(L) MR Pulse Width, LOW 7.0 8.0 ns tw(L) WE Pulse Width, LOW 4.5 5.0 ns tw(H) tw(L) CP Pulse Width HIGH or LOW 3.5 9.5 4.0 10.5 ns trec Recovery Time MR to CP 5.0 6.0 ns trec Recovery Time Mode to CP 30.0 32.0 ns 7 Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows: 74F 525 S C X Temperature Range Family 74F e Commercial Special Variations X e Devices shipped in 13× reel Device Type Temperature Range C e Commercial (0§ C to a 70§ C) Package Code Q e Plastic Chip Carrier (PCC) S e Small Outline (SOIC) P e Plastic DIP 8 Physical Dimensions inches (millimeters) 28-Lead (0.300× Wide) Molded Small Outline Package, JEDEC (S) NS Package Number M28B 28-Lead (0.600× Wide) Molded Dual-In-Line Package, (P) NS Package Number N28B 9 74F525 Programmable Counter Physical Dimensions inches (millimeters) (Continued) 28-Lead Molded Plastic Leaded Chip Carrier (Q) NS Package Number V28A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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