LOW input to CD sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH General Description The ’F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop (refer to ’F74 data sheet) by connecting the J and K inputs. Asynchronous Inputs: LOW input to SD sets Q to HIGH level Ordering Code: Features n Guaranteed 4000V minimum ESD protection. See Section 0 Commercial Military Package Package Description Number 74F109PC N16E 16-Lead (0.300" Wide) Molded Dual-in-Line J16A 16-Lead Ceramic Dual-in-Line 74F109SC (Note 1) M16A 16-Lead (0.150" Wide) Molded Small Outline, JEDEC 74F109SJ (Note 1) M16D 16-Lead (0.300" Wide) Molded Small Outline, EIAJ 54F109FM (Note 2) W16A 16-Lead Cerpack 54F109LM (Note 2) E20A 16-Lead Ceramic Leadless Chip Carrier, Type C 54F109DM (Note 2) Note 1: Devices also available in 13" reel. Use suffix = SCX and SJX. Note 2: Military grade device with environmental and burn-in processing. Use suffix = DMQB, FMQB and LMQB. 54F/74F109 54F/74F109 Dual JK Positive Edge-Triggered Flip-Flop 54F/74F109 Dual JK Positive Edge-Triggered Flip-Flop November 1994 DSXXX Logic Symbols IEEE/IEC DS009471-3 DS009471-4 DS009471-6 FAST ® and TRI-STATE ® are registered trademarks of National Semiconductor Corporation. © 1997 National Semiconductor Corporation www.national.com DS009471 PrintDate=1997/08/28 PrintTime=11:45:22 10182 ds009471 Rev. No. 1 cmserv Proof 1 1 Connection Diagrams Pin Assignment for DIP, SOIC and Flatpak Pin Assignment for LCC DS009471-1 DS009471-2 Unit Loading/Fan Out See Section 0 for U.L. definitions DSXXX 54F/74F Pin Names Description U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL 20 µA/−0.6 mA J1, J2, K1, K2 Data Inputs 1.0/1.0 CP1, CP2 Clock Pulse Inputs (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA CD1, CD2 Direct Clear Inputs (Active LOW) 1.0/3.0 20 µA/−1.8 mA SD1, SD2 Direct Set Inputs (Active LOW) 1.0/3.0 20 µA/−1.8 mA Q1, Q2, Q1, Q2 Outputs 50/33.3 −1 mA/20 mA Truth Table Inputs Outputs SD CD CP J K Q L H X X X H L H L X X X L H Q L L X X X H H H H N l l L H H H N h l H H N l h Q0 H H N h h H L H H L X X Q0 Q0 Toggle Q0 H (h) = HIGH Voltage Level L (l) = LOW Voltage Level N = LOW-to-HIGH Transition X = Immaterial Q0 (Q0) = Before LOW-to-HIGH Transition of Clock Lower case letters indicate the state of the referenced output one setup time prior to the LOW-to-HIGH clock transition. www.national.com 2 PrintDate=1997/08/28 PrintTime=11:45:23 10182 ds009471 Rev. No. 1 cmserv Proof 2 Logic Diagram (One Half Shown) DS009471-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 PrintDate=1997/08/28 PrintTime=11:45:24 10182 ds009471 Rev. No. 1 www.national.com cmserv Proof 3 Absolute Maximum Ratings Current Applied to Output in LOW State (Max) ESD Last Passing Voltage (Min) (Note 3) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Plastic VCC Pin Potential to Ground Pin Input Voltage (Note 4) Input Current (Note 4) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output TRI-STATE ® Output −65˚C −55˚C −55˚C −55˚C to to to to twice the rated IOL (mA) 4000V Recommended Operating Conditions +150˚C +125˚C +175˚C +150˚C Free Air Ambient Temperature Military Commercial Supply Voltage Military Commercial −0.5V to +7.0V −0.5V to +7.0V −30 mA to +5.0 mA −55˚C to +125˚C 0˚C to +70˚C +4.5V to +5.5V +4.5V to +5.5V Note 3: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. −0.5V to VCC −0.5V to +5.5V Note 4: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol Parameter 54F/74F Min VIH Input HIGH Voltage VIL Input LOW Voltage VCD Input Clamp Diode Voltage VOH Output HIGH 54F 10% VCC 2.5 Voltage 74F 10% VCC 2.5 74F 5% VCC 2.7 VOL IIH IBVI ICEX VID Typ Units VCC 2.0 V Recognized as a HIGH Signal 0.8 V −1.2 V Min Recognized as a LOW Signal IIN = −18 mA V Min V Min µA Max IOL = 20 mA IOL = 20 mA VIN = 2.7V µA Max VIN = 7.0V µA Max VOUT = VCC V 0.0 IID = 1.9 µA Output LOW 54F 10% VCC 0.5 Voltage 74F 10% VCC 0.5 Input HIGH 54F 20.0 Current 74F 5.0 Input HIGH Current 54F 100 Breakdown Test 74F 7.0 Output HIGH 54F 250 Leakage Current 74F 50 Input Leakage 74F 4.75 Test IOD Output Leakage 74F Input LOW Current IOS Output Short-Circuit Current ICC Power Supply Current −60 11.7 IOH = −1 mA IOH = −1 mA IOH = −1 mA 3.75 µA 0.0 All Other Pins Grounded VIOD = 150 mV −0.6 mA Max All Other Pins Grounded VIN = 0.5V (Jn, Kn) Circuit Current IIL Conditions Max −1.8 mA Max −150 mA Max VIN = 0.5V (CDn, SDn) VOUT = 0V 17.0 mA Max CP = 0V AC Electrical Characteristics See Section 0 for Waveforms and Load Configurations Symbol DSXXX 74F TA = +25˚C VCC = +5.0V Parameter 54F TA, VCC = Mil CL = 50 pF 74F TA, VCC = Com CL = 50 pF Fig. Units No. MHz kk-kk CL = 50 pF fmax Maximum Clock Frequency www.national.com Min Typ 100 125 Max Min Max 70 Min 90 Max DSXXX 4 PrintDate=1997/08/28 PrintTime=11:45:27 10182 ds009471 Rev. No. 1 cmserv Proof 4 AC Electrical Characteristics (Continued) See Section 0 for Waveforms and Load Configurations Symbol DSXXX 74F TA = +25˚C VCC = +5.0V Parameter 54F TA, VCC = Mil CL = 50 pF 74F TA, VCC = Com CL = 50 pF Fig. Units No. ns kk-kk DSXXX ns kk-kk DSXXX CL = 50 pF Min Typ Max Min Max Min Max tPLH Propagation Delay 3.8 5.3 7.0 3.8 9.0 3.8 8.0 tPHL CPn to Qn or Qn 4.4 6.2 8.0 4.4 10.5 4.4 9.2 tPLH Propagation Delay 3.2 5.2 7.0 3.2 9.0 3.2 8.0 tPHL CDn or SDn to 3.5 7.0 9.0 3.5 11.5 3.5 10.5 Qn or Qn AC Operating Requirements See Section 0 for Waveforms Symbol Parameter DSXXX 74F TA = +25˚C VCC = +5.0V 54F TA, VCC = Mil Min Min 74F TA, VCC = Com Units Fig. No. Max Max Min ts(H) Setup Time, HIGH or LOW 3.0 3.0 3.0 ts(L) Jn or Kn to CPn 3.0 4.0 3.0 th(H) Hold Time, HIGH or LOW 1.0 1.0 1.0 Max ns kk-kk DSXXX ns kk-kk DSXXX th(L) Jn or Kn to CPn 1.0 1.0 1.0 tw(H) CPn Pulse Width 4.0 4.0 4.0 tw(L) HIGH or LOW 5.0 5.0 5.0 tw(L) CDn or SDn Pulse Width, 4.0 4.0 4.0 ns kk-kk DSXXX 2.0 2.0 2.0 ns kk-kk DSXXX LOW trec Recovery Time CDn or SDn to CP Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows: Book Extract End DS009471-7 5 PrintDate=1997/08/28 PrintTime=11:45:30 10182 ds009471 Rev. No. 1 www.national.com cmserv Proof 5 THIS PAGE IS IGNORED IN THE DATABOOK 6 PrintDate=1997/08/28 PrintTime=11:45:31 10182 ds009471 Rev. No. 1 cmserv Proof 6 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Ceramic Leadless Chip Carrier (L) NS Package Number E20A 16-Lead Ceramic Dual-In-Line Package (D) NS Package Number J16A 7 PrintDate=1997/08/28 PrintTime=11:45:32 10182 ds009471 Rev. No. 1 www.national.com cmserv Proof 7 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead (0.150" Wide) Molded Small Outline Package, JEDEC (S) NS Package Number M16A 16-Lead (0.300" Wide) Molded Small Outline Package, EIAJ (SJ) NS Package Number M16D www.national.com 8 PrintDate=1997/08/28 PrintTime=11:45:32 10182 ds009471 Rev. No. 1 cmserv Proof 8 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead (0.300" Wide) Molded Dual-In-Line Package (P) NS Package Number N16E 16-Lead Ceramic Flatpak (F) NS Package Number W16A 9 PrintDate=1997/08/28 PrintTime=11:45:33 10182 ds009471 Rev. No. 1 www.national.com cmserv Proof 9 9 54F/74F109 Dual JK Positive Edge-Triggered Flip-Flop LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: [email protected] www.national.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 National Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Centre, 5 Canton Rd. Tsimshatsui, Kowloon Hong Kong Tel: (852) 2737-1600 Fax: (852) 2736-9960 National Semiconductor Japan Ltd. Tel: 81-3-5620-6175 Fax: 81-3-5620-6179 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. PrintDate=1997/08/28 PrintTime=11:45:33 10182 ds009471 Rev. No. 1 cmserv Proof 10