IS61WV12816DALL/DALS IS61WV12816DBLL/DBLS IS64WV12816DBLL/DBLS 128K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM FEATURES HIGH SPEED: (IS61/64WV12816DALL/DBLL) • High-speed access time: 8, 10, 12, 20 ns • Low Active Power: 135 mW (typical) • Low Standby Power: 12 μW (typical) CMOS standby LOW POWER: (IS61/64WV12816DALS/DBLS) • High-speed access time: 25, 35 ns • Low Active Power: 55 mW (typical) • Low Standby Power: 12 μW (typical) CMOS standby • Single power supply — VDD 1.65V to 2.2V (IS61WV12816DAxx) — VDD 2.4V to 3.6V (IS61/64WV12816DBxx) • Fully static operation: no clock or refresh required • Three state outputs • Data control for upper and lower bytes • Industrial and Automotive temperature support • Lead-free available JULY 2011 DESCRIPTION The ISSI IS61WV12816DAxx/DBxx and IS64WV12816DBxx are high-speed, 2,097,152-bit static RAMs organized as 131,072 words by 16 bits. It is fabricated using ISSI's highperformance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS61WV12816DAxx/DBxx and IS64WV12816DBxx are packaged in the JEDEC standard 44-pin TSOP Type II and 48-pin Mini BGA (6mm x 8mm). FUNCTIONAL BLOCK DIAGRAM A0-A16 DECODER 128K x 16 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O VDD GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte CE OE WE CONTROL CIRCUIT UB LB Copyright © 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com Rev. D 06/21/2011 1 IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS TRUTH TABLE I/O PIN Mode Not Selected Output Disabled Read Write WE CE OE LB UB I/O0-I/O7 I/O8-I/O15 VDD Current X H X H H H L L L H L L L L L L L L X H X L L L X X X X X H L H L L H L X X H H L L H L L High-Z High-Z High-Z DOUT High-Z DOUT DIN High-Z DIN High-Z High-Z High-Z High-Z DOUT DOUT High-Z DIN DIN ISB1, ISB2 ICC PIN CONFIGURATION 44-Pin TSOP (Type II) (T) A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VDD GND I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 ICC ICC PIN DESCRIPTIONS 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VDD I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC A0-A16 Address Inputs I/O0-I/O15 Data Inputs/Outputs CE Chip Enable Input OE Output Enable Input WE Write Enable Input LB Lower-byte Control (I/O0-I/O7) UB Upper-byte Control (I/O8-I/O15) NC No Connection VDD Power GND Ground Integrated Silicon Solution, Inc. — www.issi.com Rev. D 06/21/2011 IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS PIN CONFIGURATION 1 48-Pin mini BGA (B) 1 2 3 4 5 6 PIN DESCRIPTIONS A0-A16 Address Inputs I/O0-I/O15 Data Inputs/Outputs CE Chip Enable Input A LB OE A0 A1 A2 NC OE Output Enable Input B I/O8 UB A3 A4 CE I/O0 WE Write Enable Input C I/O9 I/O10 A5 A6 I/O1 I/O2 LB Lower-byte Control (I/O0-I/O7) D GND I/O11 NC A7 I/O3 VDD UB Upper-byte Control (I/O8-I/O15) E VDD I/O12 NC A16 I/O4 GND NC No Connection F I/O14 I/O13 A14 A15 I/O5 I/O6 VDD Power G I/O15 NC A12 A13 WE I/O7 GND Ground H NC A8 A9 A10 A11 NC 2 3 4 5 6 7 8 9 10 11 12 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 06/21/2011 3 IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS DC ELECTRICAL CHARACTERISTICS (Over Operating Range) VDD = 3.3V + 5% Symbol Parameter Test Conditions Min. Max. Unit VOH Output HIGH Voltage VDD = Min., IOH = –4.0 mA 2.4 — V VOL Output LOW Voltage VDD = Min., IOL = 8.0 mA — 0.4 V VIH Input HIGH Voltage VIL Input LOW Voltage(1) 2 VDD + 0.3 V –0.3 0.8 V ILI Input Leakage GND ≤ VIN ≤ VDD –1 1 µA ILO Output Leakage GND ≤ VOUT ≤ VDD, Outputs Disabled –1 1 µA Min. Max. Unit Note: 1. VIL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested. VIH (max.) = VDD + 0.3V DC; VIH (max.) = VDD + 2.0V AC (pulse width < 10 ns). Not 100% tested. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) VDD = 2.4V-3.6V Symbol Parameter Test Conditions VOH Output HIGH Voltage VDD = Min., IOH = –1.0 mA 1.8 — V VOL Output LOW Voltage VDD = Min., IOL = 1.0 mA — 0.4 V VIH Input HIGH Voltage 2.0 VDD + 0.3 V VIL Input LOW Voltage(1) –0.3 0.8 V ILI Input Leakage GND ≤ VIN ≤ VDD –1 1 µA ILO Output Leakage GND ≤ VOUT ≤ VDD, Outputs Disabled –1 1 µA Note: 1. VIL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested. VIH (max.) = VDD + 0.3V DC; VIH (max.) = VDD + 2.0V AC (pulse width < 10 ns). Not 100% tested. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) VDD = 1.65V-2.2V Symbol Parameter Test Conditions VDD Min. Max. Unit VOH Output HIGH Voltage IOH = -0.1 mA 1.65-2.2V 1.4 — V VOL Output LOW Voltage IOL = 0.1 mA 1.65-2.2V — 0.2 V VIH VIL(1) Input HIGH Voltage 1.65-2.2V 1.4 VDD + 0.2 V Input LOW Voltage 1.65-2.2V –0.2 0.4 V ILI Input Leakage GND ≤ VIN ≤ VDD –1 1 µA ILO Output Leakage GND ≤ VOUT ≤ VDD, Outputs Disabled –1 1 µA Note: 1. VIL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested. VIH (max.) = VDD + 0.3V DC; VIH (max.) = VDD + 2.0V AC (pulse width < 10 ns). Not 100% tested. 4 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 06/21/2011 IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS AC TEST CONDITIONS Parameter See Figures 1 and 2 Unit (3.3V + 5%) 0.4V to VDD - 0.3V 1V/ ns VDD + 0.05 2 See Figures 1 and 2 See Figures 1 and 2 R1 ( Ω ) 1909 317 13500 R2 ( Ω ) 1105 351 10800 VTM (V) 3.0V 3.3V 1.8V Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level (VRef) Output Load Unit (2.4V-3.6V) 0.4V to VDD - 0.3V 1V/ ns VDD /2 1 Unit (1.65V-2.2V) 0.4V to VDD - 0.3V 1V/ ns 0.9V 2 3 4 AC TEST LOADS 5 R1 ZO = 50Ω VTM 50Ω VDD/2 OUTPUT 6 OUTPUT 30 pF Including jig and scope Figure 1. 5 pF Including jig and scope R2 7 Figure 2. 8 9 10 11 12 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 06/21/2011 5 IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM VDD TSTG PT Parameter Terminal Voltage with Respect to GND VDD Relates to GND Storage Temperature Power Dissipation Value –0.5 to VDD + 0.5 –0.3 to 4.0 –65 to +150 1.0 Unit V V °C W Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE(1,2) Symbol Parameter CIN Input Capacitance CI/O Input/Output Capacitance Conditions Max. Unit VIN = 0V 6 pF VOUT = 0V 8 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 3.3V. 6 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 06/21/2011 IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS HIGH SPEED (IS61WV12816DALL/DBLL) OPERATING RANGE (VDD) (IS61WV12816DALL) Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C Automotive –40°C to +125°C VDD 1.65V-2.2V 1.65V-2.2V 1.65V-2.2V 1 Speed 20ns 20ns 20ns 2 OPERATING RANGE (VDD) (IS61WV12816DBLL)(1) Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C VDD (8 nS)1 3.3V + 5% 3.3V + 5% 3 VDD (10 nS)1 2.4V-3.6V 2.4V-3.6V 4 Note: 1. When operated in the range of 2.4V-3.6V, the device meets 10ns. When operated in the range of 3.3V + 5%, the device meets 8ns. 5 OPERATING RANGE (VDD) (IS64WV12816DBLL)(2,3) Range Automotive Ambient Temperature –40°C to +125°C 2 VDD (10 nS) 3.3V + 5% VDD (12 nS) 2.4V-3.6V 2 6 Note: 2. When operated in the range of 2.4V-3.6V, the device meets 12ns. When operated in the range of 3.3V + 5%, the device meets 10ns. 3. If the device is operated in the temperature range of -40oC to +85oC, the device meets 10ns. 7 (1) POWER SUPPLY CHARACTERISTICS (Over Operating Range) Symbol Parameter ICC VDD Dynamic Operating Supply Current -8 Min. Max. Test Conditions VDD = Max., Com. IOUT = 0 mA, f = fMAX Ind. CE = VIL Auto.(3) VIN ≥ VDD – 0.3V, or typ.(2) VIN ≤ 0.4V — — — 65 70 — -10 Min. Max. — — — 60 65 75 -12 Min. Max. — — — 45 -20 Min. Max. 55 55 60 — — — 40 45 50 mA 9 45 ICC1 Operating Supply Current VDD = Max., IOUT = 0 mA, f = 0 CE = VIL VIN ≥ VDD – 0.3V, or VIN ≤ 0.4V Com. Ind. Auto. — — — 2 2 — — — — 2 2 2 — — — 2 2 2 — — — 2 2 2 mA ISB2 CMOS Standby Current (CMOS Inputs) VDD = Max., CE ≥ VDD – 0.2V, VIN ≥ VDD – 0.2V, or VIN ≤ 0.2V, f = 0 Com. Ind. Auto. typ.(2) — — — 50 70 — — — — 50 70 100 — — — 50 70 100 — — — 50 70 100 μA 4 8 Unit 10 11 4 12 Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at VDD = 3.0V, TA = 25oC and not 100% tested. 3. For Automotive grade at 15ns, typ. Icc = 38mA, not 100% tested. Integrated Silicon Solution, Inc. — www.issi.com Rev. D 06/21/2011 7 IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS LOW POWER (IS61WV12816DALS/DBLS) OPERATING RANGE (VDD) (IS61WV12816DALS) Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C Automotive –40°C to +125°C VDD 1.65V-2.2V 1.65V-2.2V 1.65V-2.2V Speed 45ns 45ns 55ns OPERATING RANGE (VDD) (IS61WV12816DBLS) Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C VDD (35 nS) 2.4V-3.6V 2.4V-3.6V OPERATING RANGE (VDD) (IS64WV12816DBLS) Range Automotive Ambient Temperature –40°C to +125°C VDD (35 nS) 2.4V-3.6V POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter ICC VDD Dynamic Operating Supply Current -25 Min. Max. Test Conditions VDD = Max., IOUT = 0 mA, f = fMAX CE = VIL VIN ≥ VDD – 0.3V, or VIN ≤ 0.4V Com. Ind. Auto. typ.(2) — — — -35 Min. Max. -45 Min. Max. Unit 20 25 40 — — — 20 25 35 — — — 18 20 30 mA 18 ICC1 Operating Supply Current VDD = Max., IOUT = 0 mA, f = 0 CE = VIL VIN ≥ VDD – 0.3V, or VIN ≤ 0.4V Com. Ind. Auto. — — — 2 2 2 — — — 2 2 2 — — — 2 2 2 mA ISB2 CMOS Standby Current (CMOS Inputs) VDD = Max., CE ≥ VDD – 0.2V, VIN ≥ VDD – 0.2V, or VIN ≤ 0.2V, f = 0 Com. Ind. Auto. typ.(2) — — — 40 50 75 — — — 40 50 75 — — — 40 50 75 μA 4 Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at VDD = 3.0V, TA = 25oC and not 100% tested. 8 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 06/21/2011 IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol tRC tAA tOHA tACE tDOE tHZOE(2) tLZOE(2) tHZCE(2 tLZCE(2) tBA tHZB(2) tLZB(2) tPU tPD Parameter -8 Min. Max. -10 Min. Max. Min. -12 Max. 1 Unit Read Cycle Time 8 — 10 — 12 — ns Address Access Time — 8 — 10 — 12 ns Output Hold Time 2.0 — 2.0 — 3 — ns CE Access Time — 8 — 10 — 12 ns OE Access Time — 5.5 — 6.0 — 6.0 ns OE to High-Z Output — 3 — 4 — 6 ns OE to Low-Z Output 0 — 0 — 0 — ns CE to High-Z Output 0 3 0 4 0 6 ns CE to Low-Z Output 3 — 3 — 3 — ns LB, UB Access Time — 5.5 — 6.5 — 6.5 ns LB, UB to High-Z Output 0 5.5 0 6.5 0 6.5 ns LB, UB to Low-Z Output 0 — 0 — 0 — ns Power Up Time 0 — 0 — 0 — ns Power Down Time — 8 — 10 — 10 ns 2 3 4 5 6 Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. 7 8 9 10 11 12 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 06/21/2011 9 IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) -20 ns Min. Max. -25 ns Min. Max. -35 ns Min. Max. -45 ns Min. Max. Symbol Parameter Unit tRC Read Cycle Time 20 — 25 — 35 — 45 — ns tAA Address Access Time — 20 — 25 — 35 — 45 ns tOHA Output Hold Time 2.5 — 6 — 8 — 10 — ns tACE CE Access Time — 20 — 25 — 35 — 45 ns tDOE OE Access Time — 8 — 12 — 15 — 20 ns tHZOE(2) OE to High-Z Output 0 8 0 8 0 10 0 15 ns tLZOE(2) OE to Low-Z Output 0 — 0 — 0 — 0 — ns (2 tHZCE CE to High-Z Output 0 8 0 8 0 10 0 15 ns (2) tLZCE CE to Low-Z Output 3 — 10 — 10 — 10 — ns tBA LB, UB Access Time — 8 — 25 — 35 — 45 ns tHZB LB, UB to High-Z Output 0 8 0 8 0 10 0 15 ns tLZB LB, UB to Low-Z Output 0 — 0 — 0 — 0 — ns Notes: 1. Test conditions assume signal transition times of 1.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to VDD-0.3V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. Not 100% tested. 10 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 06/21/2011 IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS AC WAVEFORMS 1 READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL) t RC 2 ADDRESS t AA t OHA t OHA DOUT 3 DATA VALID PREVIOUS DATA VALID READ1.eps 4 5 READ CYCLE NO. 2(1,3) tRC 6 ADDRESS tAA tOHA OE 7 tHZOE tDOE tLZOE CE tACE tHZCE tLZCE 8 LB, UB DOUT VDD Supply Current HIGH-Z tBA tLZB tHZB tRC DATA VALID tPU 50% tPD 9 ICC 50% ISB UB_CEDR2.eps 10 Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE, UB, or LB = VIL. 3. Address is valid prior to or coincident with CE LOW transition. 11 12 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 06/21/2011 11 IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) -8 Symbol Parameter Min. Max. -10 Min. Max. Min. -12 Max. Unit tWC Write Cycle Time 8 — 10 — 12 — ns tSCE CE to Write End 6.5 — 8 — 9 — ns tAW Address Setup Time to Write End 6.5 — 8 — 9 — ns tHA Address Hold from Write End 0 — 0 — 0 — ns tSA Address Setup Time 0 — 0 — 0 — ns tPWB LB, UB Valid to End of Write 6.5 — 8 — 9 — ns tPWE1 WE Pulse Width 6.5 — 8 — 9 — ns tPWE2 WE Pulse Width (OE = LOW) 8.0 — 10 — 11 — ns tSD Data Setup to Write End 5 — 6 — 9 — ns tHD Data Hold from Write End 0 — 0 — 0 — ns tHZWE(2) WE LOW to High-Z Output — 3.5 — 5 — 6 ns tLZWE WE HIGH to Low-Z Output 2 — 2 — 3 — ns (2) Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. Shaded area product in development 12 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 06/21/2011 IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range) -20 ns Min. Max. -25 ns Min. Max. -35 ns Min. Max. -45ns Min. Max. Symbol Parameter tWC Write Cycle Time 20 — 25 — 35 — 45 — ns tSCE CE to Write End 12 — 18 — 25 — 35 — ns tAW Address Setup Time to Write End 12 — 15 — 25 — 35 — ns tHA Address Hold from Write End 0 — 0 — 0 — 0 — ns tSA Address Setup Time 0 — 0 — 0 — 0 — ns tPWB LB, UB Valid to End of Write 12 — 18 — 30 — 35 — ns tPWE1 WE Pulse Width (OE = HIGH) 12 — 18 — 30 — 35 — ns tPWE2 WE Pulse Width (OE = LOW) 17 — 20 — 30 — 35 — ns tSD Data Setup to Write End 9 — 12 — 15 — 20 — ns tHD Data Hold from Write End 0 — 0 — 0 — 0 — ns tHZWE(3) WE LOW to High-Z Output — 9 — 12 — 20 — 20 ns tLZWE WE HIGH to Low-Z Output 3 — 5 — 5 — 5 — ns (3) Unit 1 2 3 4 5 Notes: 1. Test conditions for IS61WV6416LL assume signal transition times of 1.5ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to VDD-0.3V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 6 7 8 9 10 11 12 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 06/21/2011 13 IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS AC WAVEFORMS WRITE CYCLE NO. 1 (CE Controlled, OE is HIGH or LOW) (1 ) t WC VALID ADDRESS ADDRESS t SA t SCE t HA CE t AW t PWE1 t PWE2 WE t PBW UB, LB t HZWE DOUT t LZWE HIGH-Z DATA UNDEFINED t SD t HD DATAIN VALID DIN UB_CEWR1.eps Notes: 1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least one of the LB and UB inputs being in the LOW state. 2. WRITE = (CE) [ (LB) = (UB) ] (WE). WRITE CYCLE NO. 2 (WE Controlled. OE is HIGH During Write Cycle) (1,2) t WC ADDRESS VALID ADDRESS t HA OE CE LOW t AW t PWE1 WE t SA t PBW UB, LB t HZWE DOUT DATA UNDEFINED t LZWE HIGH-Z t SD DIN t HD DATAIN VALID UB_CEWR2.eps 14 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 06/21/2011 IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS AC WAVEFORMS 1 WRITE CYCLE NO. 3 (WE Controlled. OE is LOW During Write Cycle) (1) t WC ADDRESS 2 VALID ADDRESS OE LOW CE LOW t HA 3 t AW t PWE2 WE t SA t PBW 4 UB, LB t HZWE DOUT t LZWE HIGH-Z DATA UNDEFINED t SD t HD 5 DATAIN VALID DIN UB_CEWR3.eps 6 WRITE CYCLE NO. 4 (LB, UB Controlled, Back-to-Back Write) (1,3) t WC ADDRESS 7 t WC ADDRESS 1 ADDRESS 2 8 OE t SA CE LOW t HA t SA WE UB, LB t PBW t PBW WORD 1 WORD 2 t HZWE DOUT 10 t LZWE HIGH-Z DATA UNDEFINED t HD t SD DIN 9 t HA DATAIN VALID t HD t SD DATAIN VALID 11 UB_CEWR4.eps Notes: 1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be in valid states to initiate a Write, but any can be deasserted to terminate the Write. The t SA, t HA, t SD, and t HD timing is referenced to the rising or falling edge of the signal that terminates the Write. 2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state. 3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function. Integrated Silicon Solution, Inc. — www.issi.com Rev. D 06/21/2011 15 12 IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS HIGH SPEED (IS61WV12816DALL/DBLL) DATA RETENTION SWITCHING CHARACTERISTICS (2.4V-3.6V) Min. Typ.(1) Max. Unit 2.0 — 3.6 V — — 10 — 50 70 100 μA See Data Retention Waveform 0 — — ns See Data Retention Waveform tRC — — ns Min. Typ.(1) Max. Unit 1.2 — 3.6 V — — — 10 — — 50 70 100 μA Symbol Parameter Test Condition Options VDR VDD for Data Retention See Data Retention Waveform IDR Data Retention Current VDD = 2.0V, CE ≥ VDD – 0.2V tSDR tRDR Data Retention Setup Time Recovery Time Com. Ind. Auto. Note 1: Typical values are measured at VDD = 3.0V, TA = 25 C and not 100% tested. O DATA RETENTION SWITCHING CHARACTERISTICS (1.65V-2.2V) Symbol Parameter Test Condition Options VDR VDD for Data Retention See Data Retention Waveform IDR Data Retention Current VDD = 1.2V, CE ≥ VDD – 0.2V tSDR tRDR Data Retention Setup Time See Data Retention Waveform 0 — — ns Recovery Time See Data Retention Waveform tRC — — ns Com. Ind. Auto. Note 1: Typical values are measured at VDD = 1.8V, TA = 25 C and not 100% tested. O DATA RETENTION WAVEFORM (CE Controlled) tSDR Data Retention Mode tRDR VDD VDR CE GND 16 CE ≥ VDD - 0.2V Integrated Silicon Solution, Inc. — www.issi.com Rev. D 06/21/2011 IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS LOW POWER (IS61WV12816DALS/DBLS) DATA RETENTION SWITCHING CHARACTERISTICS (2.4V-3.6V) 1 Min. Typ.(1) Max. Unit 2.0 — 3.6 V — — 20 — 40 50 75 μA 2 See Data Retention Waveform 0 — — ns See Data Retention Waveform tRC — — ns 3 Symbol Parameter Test Condition Options VDR VDD for Data Retention See Data Retention Waveform IDR Data Retention Current VDD = 2.0V, CE ≥ VDD – 0.2V tSDR tRDR Data Retention Setup Time Recovery Time Com. Ind. Auto. Note 1: Typical values are measured at VDD = 3.0V, TA = 25 C and not 100% tested. O 4 DATA RETENTION SWITCHING CHARACTERISTICS (1.65V-2.2V) Min. Typ.(1) Max. Unit 1.2 — 3.6 V — — — 20 — — 40 50 75 μA See Data Retention Waveform 0 — — ns See Data Retention Waveform tRC — — ns Symbol Parameter Test Condition Options VDR VDD for Data Retention See Data Retention Waveform IDR Data Retention Current VDD = 1.2V, CE ≥ VDD – 0.2V tSDR tRDR Data Retention Setup Time Recovery Time Com. Ind. Auto. 5 6 Note 1: Typical values are measured at VDD = 1.8V, TA = 25 C and not 100% tested. 7 O 8 DATA RETENTION WAVEFORM (CE Controlled) tSDR Data Retention Mode 9 tRDR VDD 10 VDR CE GND 11 CE ≥ VDD - 0.2V 12 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 06/21/2011 17 IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS ORDERING INFORMATION (HIGH SPEED) Commercial Range: 0°C to +70°C Voltage Range: 2.4V to 3.6V Speed (ns) 1 10 (8 ) Order Part No. Package IS61WV12816DBLL-10TL TSOP (Type II), Lead-free Note: 1. Speed = 8ns for VDD = 3.3V + 5%. Speed = 10ns for VDD = 2.4V to 3.6V. Industrial Range: -40°C to +85°C Voltage Range: 2.4V to 3.6V Speed (ns) 1 10 (8 ) Order Part No. Package IS61WV12816DBLL-10BI IS61WV12816DBLL-10BLI IS61WV12816DBLL-10TI IS61WV12816DBLL-10TLI 48 mini BGA (6mm x 8mm) 48 mini BGA (6mm x 8mm), Lead-free TSOP (Type II) TSOP (Type II), Lead-free Note: 1. Speed = 8ns for VDD = 3.3V + 5%. Speed = 10ns for VDD = 2.4V to 3.6V. Industrial Range: -40°C to +85°C Voltage Range: 1.65V to 2.2V Speed (ns) 20 Order Part No. Package IS61WV12816DALL-20BI IS61WV12816DALL-20TI 48 mini BGA (6mm x 8mm) TSOP (Type II) Automotive Range: -40°C to +125°C Voltage Range: 2.4V to 3.6V Speed (ns) 2,3 12 (10 ) Order Part No. Package IS64WV12816DBLL-12BA3 IS64WV12816DBLL-12BLA3 IS64WV12816DBLL-12CTA3 IS64WV12816DBLL-12CTLA3 48 mini BGA (6mm x 8mm) 48 mini BGA (6mm x 8mm), Lead-free TSOP (Type II), Copper Leadframe TSOP (Type II), Lead-free, Copper Leadframe Note: 2. Speed = 10ns for VDD = 3.3V + 5%. Speed = 12ns for VDD = 2.4V to 3.6V. 3. Speed = 10ns for VDD = 2.4V to 3.6V and temperature = -40oC to +85oC. 18 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 06/21/2011 IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS ORDERING INFORMATION (LOW POWER - IN EVALUATION) Industrial Range: -40°C to +85°C Voltage Range: 2.4V to 3.6V Speed (ns) 35 Order Part No. 1 Package 2 IS61WV12816DBLS-35TLI TSOP (Type II), Lead-free 3 4 5 6 7 8 9 10 11 12 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 06/21/2011 19 20 08/12/2008 Package Outline 1. CONTROLLING DIMENSION : MM . 2. Reference document : JEDEC MO-207 NOTE : IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS Integrated Silicon Solution, Inc. — www.issi.com Rev. D 06/21/2011 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 06/21/2011 Package Outline 06/04/2008 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION. 2. DIMENSION D AND E1 DO NOT INCLUDE MOLD PROTRUSION. 1. CONTROLLING DIMENSION : MM NOTE : IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS 1 2 3 4 5 6 7 8 9 10 11 12 21