DATA SHEET MOS INTEGRATED CIRCUIT µPD4701A INCREMENTAL ENCODER COUNTER DESCRIPTION The µPD4701A is a counter for an X, Y 2-axis incremental encoder. When a two-phase encoder signal is input for the X and Y axes, direction discrimination and computation is performed, and count data is output in 8-bit parallel form. In addition, a 3-contact-point input buffer is incorporated, which is useful for applications which use a pointing device such as a mouse or track-ball. The CPU checks the switch input flag or count flag and reads the 12-bit count data in two operations, one for the lower byte and one for the upper byte. The key input flag is output together with the count data in the upper byte. FEATURES • X, Y 2-axis incremental encoder counter • Counter input (Schmitt-triggered input) X axis: XA, XB 2-phase signal 4-multiplication count method used Y axis: YA, YB 2-phase signal • Counters: 12-bit binary up/down counters (2 sets, X & Y) Reset value: 000H • Count data output: 8-bit parallel latch output × 2 (including key input flag) • On-chip 3-contact-point key input buffer circuit • CMOS • Single +5 V power supply PIN CONFIGURATION (Top View) PIN NAMES XA, YA : A-phase inputs XB, YB : B-phase inputs LEFT Key inputs MIDDLE RIGHT CS : Chip Select X/Y : X/Y Counter Select U/L : Upper/Lower Byte Select D0 to 7 : Data outputs CF : Count flag SF : Count flag Document No. IC-3303 (1st edition) (O. D. No. IC-6947A) Date Published March 1997 P Printed in Japan RESET X Counter RESET Y reset inputs XA 1 24 VDD XB 2 23 D7 RESET X 3 22 D6 YA 4 21 D5 YB 5 20 D4 RESET Y 6 19 D3 RIGHT 7 18 D2 LEFT 8 17 D1 MIDDLE 9 16 D0 SF 10 15 CS CF 11 14 X/Y VSS 12 13 U/L © 1993 µPD4701A ORDERING INFORMATION Part Number Package µPD4701AC 24-pin plastic DIP (600 mil) µPD4701AGT 24-pin plastic SOP (375 mil) BLOCK DIAGRAM Phase Determination and Edge Detection XA XB X-Axis Up/Down Counter CS RESET X X/Y U/L Data Multiplexer & Latch D0-7 RESET Y Phase Determination and Edge Detection YA YB CF Switch Flag Circuit SF Y-Axis Up/Down Counter RIGHT Button Input Circuit LEFT Count Flag Circuit MIDDLE DATA MULTIPLEXER/LATCH BLOCK X-Axis Counter X/Y U/L 12-Bit Latch STB Y-Axis Counter 12-Bit Latch 8 8 Data Multiplexer 8 3-State Buffer D0 - 7 STB OE 4 Button Input 4-Bit Latch STB CS To Count Flag Circuit 2 µPD4701A PIN FUNCTIONS CPU interface block Mouse interface block Pin Name Input/Output Function CS Input Chip Select input. “L” input activates outputs D0 to 7. “H” input sets outputs D0 to 7 to high impedance. Output data is latched on the fall edge of CS. “L” must be maintained during a count data read. X/Y Input Counter Select input. “L” input selects the X counter, and “H” input selects the Y counter. U/L Input Byte Select input. “L” input selects the lower byte and “H” input selects the upper byte, controlling data output. RESET X RESET Y Input Counter reset inputs. RESET X input resets the X counter, and RESET Y input resets the Y counter. Both are active-“H”. D0 to 7 Output (3-state) Bus for data output to the CPU. Outputs the byte data selected by the X/Y and U/L inputs. The data latched on the fall of CS is output. CF Output Counter flag output. Set (= “L” output) when the X or Y counter changes while CS = “H”. Reset (= “H” output) on the fall of CS. While CS = “L”, count flag output is disabled and the “H” level is output. SF Output Switch flag output. Becomes active (= “L” output) when the RIGHT, LEFT or MIDDLE switch input is “L”. XA , XB Input (Schmitt input) X counter 2-phase signal input pins YA , YB Input (Schmitt input) Y counter 2-phase signal input pins RIGHT LEFT MIDDLE Input (Schmitt input) Key switch input pins. Key switch input are read as the high-order 4 bits of the X counter and Y counter upper byte as the internal status. Upper Byte SF R M C11 C10 C9 C8 Power supply block L Key Input Status Count Data VDD +5 V power supply connection pin VSS Ground pin 3 µPD4701A DESCRIPTION OF OPERATIONS 1. COUNT OPERATION The µPD4701A executes an up-count and down-count by means of A & B 2-phase signals in the 12-bit up-down counter. An up-count is performed when the A-phase signals (XA, YA) are phase-advanced, and a down-count is performed when the B-phase signals (XB, YB) are phase-advanced. The edge of each signal is a count source. (4multiplication count method: see Fig. 1.) Fig. 1 Count Operation Timing Chart Forward (Up-Count) Reverse (Down-Count) (X, Y)A Input Count Operation 1 2 3 4 5 4 3 2 1 0 (X, Y)B Input This count operation is executed independently for the X axis (XA, XB) and Y axis (YA, YB). This operation is initialized by reset input (RESET X, RESET Y) only. In an up-count, the next value after FFFH is 000H, and in a down-count, the next value after 000H is FFFH. 2. OPERATION OF COUNT FLAG, CF The count flag, CF, indicates that a count source (either XA, B or YA, B edge input) has occurred while the CS signal is “H”, and is an active-low output. CF is reset (→ “H”) by CS signal “L” input. While CS = “L”, count flag output is disabled and the “H” level is output. Fig. 2 Count Flag Output Timing Chart XA, B YA, B CF CS Count Flag Output Disabled in these Periods 4 µPD4701A 3. SWITCH INPUT OPERATION The µPD4701A can process up to 3 contact points as switch inputs (active-“L” input). Switch input is read as part of the count data upper byte together with the switch flag status as an internal status (see Fig. 3). These are all active“H” outputs. The switch flag status, SF, is equivalent to the switch flag output, SF, described below. Fig. 3 Data Output Format Bit No. Upper Byte 7 6 5 4 3 2 1 0 SF L R M C11 C10 C9 C8 Bit No. Lower Byte 7 6 5 4 3 2 1 0 C7 C6 C5 C4 C3 C2 C1 C0 SF : L: R: M: C11 - 0 : Switch Flag Left Switch Right Switch Middle Switch Count Data (12 bit ) 4. OPERATION OF SWITCH FLAG, SF The switch flag, SF, becomes active (active-“L” output) when the RIGHT, LEFT or MIDDLE switch input is “L”. SF can also be read as the switch flag status together with the count data. 5. DATA READ OPERATION The CPU reads the count data and switch input status by controlling CS, X/Y and U/L. The relation between these is shown in Table 1. (At this time, the data latched on the falling edge of CS is output. If X/Y or U/L is switched while CS is still “L”, the data at the point at which CS changes from “H” to “L” is read. When CS is set to “H”, new data is read into the latch, and the new data is confirmed on the next fall of CS. Table 1 Data Output Table CS X/Y U/L D7 0 0 0 X 0 0 1 SF 0 1 0 Y 0 1 1 SF 1 × × C7 C7 D6 X C6 L Y C6 L D5 X C5 R Y C5 R D4 X C4 M Y C4 M D3 X X C11 Y Y C3 C3 C11 D2 X C1 X C0 C10 X C9 X C8 C2 Y C1 Y C0 C10 Y C9 Y C8 Y Y D0 C2 X X D1 FLOATING 5 µPD4701A 6. CONNECTION TO CPU SYSTEM An example of connection to a CPU system is shown in Fig. 4. Fig. 4 Example of Connection to CPU System RESET Output Port Mouse X Y A2 - An and IORD or MRD CS X/Y A1 A0 XA XB U/L YA CPU System YB D0 - 7 µ PD4701A DB0 - 7 INT FLAG SF RIGHT MIDDLE CF LEFT Mouse I/F µPD4701A Pin Name X/Y U/L CS D0 to 7 SF, CF RESET X RESET Y Description Connected to address line A1. Connected to address line A0. Connects address lines A2 to An and the signal resulting from decoding IORD in the I/O address mode or MRD in the memory address mode, or an output port. The low level must be maintained during a count data read. Connected to the data bus. When these are used as interrupt signals, they are connected to the CPU INT pin. These are connected to a CPU output port or reset signal. The above connections enable the CPU to read the X counter, Y counter and switch input status. The application circuits and their parameters are for reference only and are not intended for use in actual design-ins. 6 µPD4701A An example of a µPD4701A data read is shown in Fig. 5. Fig. 5 Example of µPD4701A Data Read Start Count value latch Count reset CS = 0 RESET X = 1 RESET Y = 1 X counter low byte read X/Y = 0 U/L = 0 X counter high byte & switch status read X/Y = 0 U/L = 1 Y counter low byte read X/Y = 1 U/L = 0 Y counter high byte & switch status read X/Y = 1 U/L = 1 Data bus high impedance CS = 1 End * CS must be kept at “0” during the read. 7 µPD4701A 7. APPLICATION AREAS Two-phase incremental signals are used for detection and measurement of a vector quantity (a quantity that has direction and magnitude), and are widely employed in measuring instruments such as micrometers and linear scales, control systems for digital servo motors, X-Y tables, etc., head position control for printers, magnetic disks, etc., robot arm position control, and so on. The µPD4701A incorporates the direction judgment circuit and count pulse generator required for 2-phase incremental signal processing, up/down counters for counting these pulses, and a data latch to hold the read data, in IC form, enabling an X, Y 2-axis incremental signal processing system to be implemented easily. In addition, a 3 switch-input buffer is incorporated, enabling this device to be widely used in man-machine interface and centronics interface application areas. 8. OPERATING PRECAUTIONS 1) As the µPD4701A incorporates two sets of 12-bit counters, large transient currents flow during a count operation. Adecoupling capacitor of around 0.1 µF should therefore be inserted between VDD and VSS of the µPD4701A. +5V VDD Tantalum electrolytic, laminated ceramic, or similar capacitor of around 0.1 µF (Should be mounted right next to the IC.) VSS µPD4701A 2) If a pulse shorter than the signal phase difference time tSAB (350 ns) is input to the A/B phase inputs (XA, XB, YA, YB) this will result in a miscount. Therefore, if pulses shorter than tSAB are to be input because of encoder bounds, etc., a filter should be attached to the A/B phase inputs. PW A or B Phase B or A Phase If PW ≥ tSAB (350 ns), the count value remains the same before and after pulse input. (UP count → DOWN count or DOWN count → UP count is implemented, and therefore the result is equivalent to no change in the count value. 8 µPD4701A ABSOLUTE MAXIMUM RATINGS (Ta = 25 °C, VSS = 0 V) PARAMETER SYMBOL RATING UNIT VDD –0.5 to +7.0 V Input voltage VI –1.0 to VDD + 1.0 V Output voltage VO –0.5 to VDD + 0.5 V Operating temperature Topt –40 to +85 °C Storage temperature Tstg –65 to +150 °C Permissible loss PD 500 mW Supply voltage DC CHARACTERISTICS (Ta = –40 to +85 °C, VDD = +5 V ±10 %) PARAMETER RATING SYMBOL MIN. UNIT TEST CONDITIONS MAX. Input voltage high VIL Input voltage low VIH 2.6 V XA, XB, YA, YB and LEFT, RIGHT, MIDDLE VIH 2.2 V Other than the above V IOL = 12 mA V IOH = –4 mA 50 µA VI = VDD, VSS VI = VDD, VSS Output voltage low VOL Output voltage high VOH Static consumption current IDD Input current 3-state output leak current Dynamic consumption current Hysteresis voltage 0.8 0.45 VDD – 0.8 V II –1.0 1.0 µA IOFF –10 10 µA 2 mA IDD dyn VH 0.25 V fIN = 500 kHz XA, XB, YA, YB and LEFT, RIGHT, MIDDLE 9 µPD4701A AC CHARACTERISTICS (Ta = –40 to +85 °C, VDD = +5 V ± 10 %) PARAMETER RATING SYMBOL MIN. UNIT XA , XB Input cycle tCYAB 2 µs YA , YB High-level pulse width tPWABH 900 ns Low-level pulse width tPWABL 900 ns tSAB 350 ns Signal phase difference time fin = 500 kHz R, L High-level pulse width tPWSWH 30 µs Switch OFF M Low-level pulse width tPWSWL 30 µs Switch ON SF Setting delay time tDSFL 50 ns Switch ON Reset delay time tDSFH 50 ns Switch OFF Pulse width tPWRS 100 ns Count enable time tSCTEN 0 ns From RESETX, Y ↓ Count clear time tDCTCL 100 ns From RESETX, Y ↑ Flag setting time tDABCF 120 ns From XA, B, YA, B Flag reset time tDCSCF 100 ns From CS ↓ RESET W, Y CF tSCT 0 ns From CF ↓ CF enable time tSCSCF 140 ns From CF ↓ CF disable time tHABCS 140 ns From XA, B, YA, Pulse width tPWCS 200 ns X/Y Address setup time tSACS 0 ns To CS ↓ U/L Address hold time tHCSAB 0 ns From CS ↑ D0 to 7 Output delay time tDCSD 150 ns From CS ↓ Output delay time tDAD 100 ns From X/Y, U/L Floating time tFCSD 50 ns From CS ↑ Count setting time CS AC TEST INPUT WAVEFORM 2.6 V 1.5 V Test Point 1.5 V 0.45 V AC test : The input is driven by 2.6 V for logic “1”, and 0.45 V for logic “0”. Timing measurement is performed at 1.5 V for both logic “1” and logic “0”. 10 TEST CONDITIONS MAX. B µPD4701A Fig. 6 Two-Phase Signal & Switch Signal Input Timing tCYAB XA, YA XB, YB tPWABH tSAB tPWABL tSAB tSAB tSAB tPWSWL tPWSWH RIGHT LEFT MIDDLE Fig. 7 Count Flag Output Timing tPWRS RESET X, Y tSCTEN XA, B YA, B tSAB tDABCF tDCSCF CF tDCTCL tSCSCF tHABCS CS tSCT tPWCS 11 µPD4701A Fig. 8 Data Output Timing CS tSACS tHCSA X/Y U/L tDCSD tDAD tFCSD D0 - 7 Fig. 9 Switch Flag Signal Output Timing RIGHT LEFT MIDDLE tDSFL SF 12 tDSFH µPD4701A RECOMMENDED SOLDERING CONDITIONS The following conditions (see table below) must be met when soldering this product. Please consult with our sales offices in case other soldering process is used, or in case soldering is done under different conditions. TYPES OF SURFACE MOUNT DEVICE µPD4701AGT Soldering process Soldering conditions Symbol Infrared ray reflow Peak package’s surface temperature: 235 °C or below, Reflow time: 30 seconds or below (210 °C or higher), Number of reflow process: 2, Exposure limit*: None IR35-00-2 VPS Peak package’s surface temperature: 215 °C or below, Reflow time: 40 seconds or below (200 °C or higher), Number of reflow process: 2, Exposure limit*: None VP15-00-2 Wave soldering Solder temperature: 260 °C or below, Flow time: 10 seconds or below, Number of flow process: 1, Exposure limit*: None WS60-00-1 Partial heating method Terminal temperature: 300 °C or below, Flow time: 10 seconds or below, Exposure limit*: None * Exposure limit before soldering after dry-pack package is opened. Storage conditions: 25 °C and relative humidity at 65 % or less. Note Do not apply more than a single process at once, except for “Partial heating method”. TYPE OF THROUGH HOLE MOUNT DEVICE µPD4701AC Soldering process Wave soldering Soldering conditions Symbol Solder temperature: 260 °C or below, Flow time: 10 seconds or below 13 µPD4701A 24PIN PLASTIC DIP (600 mil) 24 13 1 12 A K I L J H F C G D N M B NOTES 1) Each lead centerline is located within 0.25 mm (0.01 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" to center of leads when formed parallel. R M ITEM MILLIMETERS INCHES A 33.02 MAX. 1.300 MAX. B C 2.54 MAX. 2.54 (T.P.) 0.100 MAX. 0.100 (T.P.) D 0.50±0.10 0.020 +0.004 –0.005 F 1.2 MIN. 0.047 MIN. G H 3.5±0.3 0.51 MIN. 0.138±0.012 0.020 MIN. I J 4.31 MAX. 5.72 MAX. 0.170 MAX. 0.226 MAX. K 15.24 (T.P.) 0.600 (T.P.) L 13.2 0.520 M 0.25 +0.10 –0.05 0.010 +0.004 –0.003 N 0.25 0.01 R 0~15° 0~15° P24C-100-600-1 14 µPD4701A 24 PIN PLASTIC SOP (375 mil) 24 13 3° +7° –3° detail of lead end 1 12 A H J E K F G I D L B C N M M NOTE Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition. P24GT-50-375B-1 ITEM MILLIMETERS INCHES A 15.71 MAX. 0.619 MAX. B 0.87 MAX. 0.035 MAX. C 1.27 (T.P.) 0.050 (T.P.) D 0.40+0.10 –0.05 0.016+0.004 –0.003 E 0.125 ± 0.075 0.005 ± 0.003 F 2.9 MAX. 0.115 MAX. G 2.50 ± 0.2 0.098+0.009 –0.008 H 10.3 ± 0.3 0.406+0.012 –0.013 I 7.2 ± 0.2 0.283+0.009 –0.008 J 1.6 ± 0.2 0.063 ± 0.008 K 0.15+0.10 –0.05 0.006+0.004 –0.002 L 0.8 ± 0.2 0.031+0.009 –0.008 M 0.12 0.005 N 0.10 0.004 15 µPD4701A [MEMO] No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". 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Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5 2