RT8223A/B High Efficiency, Main Power Supply Controller for Notebook Computers General Description Features The RT8223A/B dual step-down, switch-mode powersupply controller generates logic-supply voltages in battery-powered systems. The RT8223A/B includes two pulse-width modulation (PWM) controllers fixed at 5V/ 3.3V or adjustable from 2V to 5.5V. This device also features 2 linear regulators providing fixed 5V and 3.3V outputs. The linear regulator each provides up to 70mA output current with automatic linear-regulator bootstrapping to the PWM outputs. The RT8223A/B includes on-board power-up sequencing, the power good output, internal softstart, and internal soft-discharge output that prevents negative voltages on shutdown. z A constant on-time PWM control scheme operates without sense resistor and provides 100ns response to load transients while maintaining a relatively constant switching frequency. The unique ultrasonic mode maintains the switching frequency above 25kHz, which eliminates noise in audio applications. Other features include diodeemulation mode (DEM), which maximizes efficiency in light-load applications, and fixed-frequency PWM mode, which reduces RF interference in sensitive application z z z z z z z z z z z z Wide Input Voltage Range 6V to 25V Dual Fixed 5V/3.3V Outputs or Adjustable from 2V to 5.5V, 1.5% Accuracy Fixed 3.3V and 5V LDO Output : 70mA μA 2V Reference Voltage ±1% : 50μ Constant ON-Time Control with 100ns Load Step Response Frequency Selectable via TONSEL Setting RDS(ON) Current Sensing and Programmable Current Limit combined with Enable Control Selectable PWM, DEM, or Ultrasonic Mode Internal Soft-Start and Soft-Discharge High Efficiency up to 97% 5mW Quiescent Power Dissipation Thermal Shutdown RoHS Compliant and Halogen Free Applications z z Notebook and Sub-Notebook Computers 3-Cell and 4-Cell Li+ Battery-Powered Devices Marking Information Ordering Information RT8223 Package Type QW : WQFN-24L 4x4 (W-Type) For marking information, contact our sales representative directly or through a Richtek distributor located in your area. Lead Plating System G : Green (Halogen Free and Pb Free) Z : ECO (Ecological Element with Halogen Free and Pb free) Pin Function A : Default B : With ENC Note : Richtek products are : ` RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. ` Suitable for use in SnPb or Pb-free soldering processes. DS8223A/B-04 April 2011 www.richtek.com 1 RT8223A/B Pin Configurations VOUT1 PGOOD BOOT1 UGATE1 PHASE1 LGATE1 VOUT1 PGOOD BOOT1 UGATE1 PHASE1 LGATE1 (TOP VIEW) 24 23 22 21 20 19 ENTRIP1 FB1 REF TONSEL FB2 ENTRIP2 24 23 22 21 20 19 1 18 2 17 3 16 GND 4 15 25 5 14 13 6 9 1 18 2 17 3 16 GND 4 15 25 5 14 13 6 10 11 12 7 8 9 ENC VREG5 VIN PGND SKIPSEL EN 10 11 12 VOUT2 VREG3 BOOT2 UGATE2 PHASE2 LGATE2 8 ENTRIP1 FB1 REF TONSEL FB2 ENTRIP2 VOUT2 VREG3 BOOT2 UGATE2 PHASE2 LGATE2 7 NC VREG5 VIN PGND SKIPSEL EN RT8223A RT8223B WQFN-24L 4x4 WQFN-24L 4x4 Typical Application Circuit For Fixed Voltage Regulator V IN R7 3.9 C1 10µF C6 0.1µF Q1 BSC119 N03S V OUT1 5V C3 220µF R5 C4 16 VIN BOOT2 PHASE2 11 R3 0 22 BOOT1 LGATE2 12 C11 0.22µF R9 0 Q2 BSC119 N03S R8 0 C7 0.1µF 24 VOUT1 3 REF Frequency Control 4 TONSEL PWM/DEM/Ultrasonic 14 SKIPSEL 13 EN 2 FB1 VOUT2 7 VREG5 17 PGOOD 23 VREG3 8 C5 4.7µF GND C8 10µF R10 V OUT2 3.3V C13 220µF C10 5V Always On R6 100k PGOOD Indicator C12 4.7µF ENTRIP1 1 ENTRIP2 C9 10µF L2 4.7µH Q4 BSC119 N03S PGND 15 20 PHASE1 19 LGATE1 ON 9 21 UGATE1 Q3 BSC119 N03S OFF UGATE2 10 R4 0 C2 0.1µF L1 6.8µH RT8223A 6 3.3V Always On R1 150k R2 150k Exposed Pad (25) 5 FB2 www.richtek.com 2 DS8223A/B-04 April 2011 RT8223A/B V IN R7 3.9 C1 10uF C10 0.1µF Q1 BSC119 N03S V OUT1 5V C3 220µF R5 C4 BOOT2 9 21 UGATE1 PHASE2 11 R3 0 22 BOOT1 LGATE2 12 PGND 20 PHASE1 19 LGATE1 Q3 BSC119 N03S 24 VOUT1 ON OFF C15 0.22µF ON 18 ENC 3 REF 13 EN OFF DS8223A/B-04 April 2011 UGATE2 10 R4 0 C2 0.1µF L1 6.8µH RT8223B 16 VIN Frequency Control 4 TONSEL PWM/DEM/Ultrasonic 14 SKIPSEL R9 0 Q2 BSC119 N03S R8 0 C7 0.1µF VOUT2 7 VREG5 17 PGOOD 23 VREG3 8 C9 4.7µF V OUT2 3.3V C17 220µF R10 C14 5V Always On R6 100k PGOOD Indicator C16 4.7µF ENTRIP1 1 ENTRIP2 C12 10µF L2 4.7µH Q4 BSC119 N03S 15 C13 10µF 6 3.3V Always On R1 150k R2 150k FB1 2 FB2 5 GND Exposed Pad (25) www.richtek.com 3 RT8223A/B For Adjustable Voltage Regulator V IN R7 3.9 C1 10µF C6 0.1µF Q1 BSC119 N03S C3 220µF 21 UGATE1 PHASE2 11 R3 0 22 BOOT1 LGATE2 12 C4 19 LGATE1 C15 0.1µF R11 15k ENTRIP2 R12 10k C11 0.22µF GND Frequency Control PWM/DEM/Ultrasonic 14 SKIPSEL ON R13 6.5k C17 C16 0.1µF R14 10k 5V Always On C5 4.7µF PGOOD 23 VREG3 8 13 EN C10 Exposed Pad (25) VREG5 17 4 TONSEL C13 220µF R2 150k 6 V OUT2 3.3V R10 R1 150k ENTRIP1 1 2 FB1 3 REF C8 10µF L2 4.7µH Q4 BSC119 N03S VOUT2 7 5 FB2 24 VOUT1 C14 C7 0.1µF PGND 15 20 PHASE1 C9 10µF Q2 BSC119 N03S R8 0 9 R4 0 Q3 BSC119 N03S R5 UGATE2 10 BOOT2 C2 0.1µF L1 6.8µH V OUT1 5V R9 0 RT8223A 16 VIN R6 100k PGOOD Indicator 3.3V Always On C12 4.7µF OFF V IN R7 3.9 C1 10µF RT8223B C10 0.1µF R4 0 Q1 BSC119 N03S C3 220µF R5 C4 BOOT2 C19 0.1µF PHASE2 11 22 BOOT1 LGATE2 12 20 PHASE1 19 LGATE1 Q3 BSC119 N03S 2 FB1 ON OFF 18 ENC 3 REF C15 0.22µF ON 13 EN OFF www.richtek.com 4 R9 0 Q2 BSC119 N03S R8 0 C7 0.1µF Frequency Control 4 TONSEL PWM/DEM/Ultrasonic 14 SKIPSEL C12 10µF L2 4.7µH Q4 BSC119 N03S V OUT2 3.3V C17 220µF R10 C14 VOUT2 7 R13 6.5k FB2 5 R11 15k R12 10k 9 21 UGATE1 24 VOUT1 C18 UGATE2 10 PGND 15 C2 0.1µF L1 6.8µH V OUT1 5V R3 0 16 VIN C13 10µF R1 150k ENTRIP1 1 ENTRIP2 GND R14 10k C21 C20 0.1µF R2 150k 6 Exposed Pad (25) VREG5 17 PGOOD 23 VREG3 8 C9 4.7µF 5V Always On R6 100k PGOOD Indicator C16 4.7µF 3.3V Always On DS8223A/B-04 April 2011 RT8223A/B Function Block Diagram TONSEL SKIPSEL BOOT1 BOOT2 UGATE1 UGATE2 PHASE2 PHASE1 VREG5 VREG5 SMPS1 PWM Buck Controller LGATE1 SMPS2 PWM Buck Controller LGATE2 PGND VOUT2 FB2 ENTRIP2 VOUT1 FB1 ENTRIP1 PGOOD Power-On Sequence Clear Fault Latch EN ENC GND SW Threshold SW Threshold Thermal Shutdown VREG3 VREG5 REF VREG5 VREG3 VIN REF Function Block Diagram TONSEL VIN UGATE On-Time Compute VOUT TON Q R 1-Shot TOFF TRIG 1-Shot Q TRIG REF - + - Comp + + - LGATE FB 1.1 x VREF 0.6 x VREF Over-Voltage + Fault Latch - VREG5 Blanking Time + Under-Voltage + 0.9 x VREF PGOOD + ENTRIP - + S + SS Time 25kHz Detector Zero Detector Current Limit + PHASE - SKIPSEL PWM Controller (One Side) DS8223A/B-04 April 2011 www.richtek.com 5 RT8223A/B Functional Pin Description ENTRIP1 (Pin 1) VOUT2 (Pin 7) Channel 1 enable and Current Limit setting Input. Connect a resistor to GND to set the threshold for channel 1 synchronous RDS(ON) sense. The GND − PHASE1 current- SMPS2 Output Voltage Sense Input. Connect to the SMPS2 output. VOUT2 is an input to the on-time one shot circuit. It also serves as the SMPS2 feedback input in fixed voltage mode. limit threshold is 1/10th the voltage seen at ENTRIP1 over a 0.5V to 2V range. There is an internal 10μA current source from VREG5 to ENTRIP1. VREG3 (Pin 8) 3.3V Linear Regulator Output. FB1 (Pin 2) SMPS1 Feedback Input. Connect FB1 to VREG5 or GND for fixed 5V operation. Or connect FB1 to a resistive voltagedivider from VOUT1 to GND to adjust output from 2V to 5.5V. BOOT2 (Pin 9) REF (Pin 3) UGATE2 (Pin 10) 2V Reference Output. Bypass to GND with a 0.22μF capacitor. REF can source up to 50μA for external loads. Loading REF degrades FBx and output accuracy according to the REF load regulation error. High-Side MOSFET Floating Gate Driver Output for SMPS2. UGATE2 swings between PHASE2 and BOOT2. TONSEL (Pin 4) Frequency Selectable Input for VOUT1/VOUT2 respectively. 400kHz/500kHz : Connect to VREG5 or VREG3 300kHz/375kHz : Connect to REF Boost Flying Capacitor Connection for SMPS2. Connect to an external capacitor according to the typical application circuits. PHASE2 (Pin 11) Inductor Connection for SMPS2. PHASE2 is the internal lower supply rail for the UGATE2 high side gate driver. PHASE2 is also the current-sense input for the SMPS2. LGATE2 (Pin 12) SMPS2 Synchronous-Rectifier Gate-Drive Output. LGATE2 swings between PGND and VREG5. 200kHz/250kHz : Connect to GND EN (Pin 13) FB2 (Pin 5) SMPS2 Feedback Input. Connect FB2 to VREG5 or GND for fixed 3.3V operation. Or connect FB2 to a resistive voltage-divider from VOUT2 to GND to adjust output from 2V to 5.5V. Master Enable Input. The REF/VREG5/VREG3 are enabled if it is within logic high level and disabled if it is less than the logic low level. SKIPSEL (Pin 14) Operation Mode Selectable Input. ENTRIP2 (Pin 6) Channel 2 enable and Current Limit setting Input. Connect a resistor to GND to set the threshold for channel 2 synchronous RDS(ON) sense. The GND − PHASE2 current limit threshold is 1/10th the voltage seen at ENTRIP2 over a 0.5V to 2V range. There is an internal 10μA current source from VREG5 to ENTRIP2. www.richtek.com 6 Ultrasonic Mode : Connect to VREG5 or VREG3 Diode Emulation Mode : Connect to GND PWM Mode : Connect to REF GND [Exposed Pad (25)] Analog Ground for SMPS controller. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. DS8223A/B-04 April 2011 RT8223A/B PGND (Pin 15) VOUT1 (Pin 24) Power Ground for SMPS controller. Connect PGND externally to the underside of the exposed pad. SMPS1 Output Voltage-Sense Input. Connect to the SMPS1 output. VOUT1 is an input to the on-time one shot circuit. It also serves as the SMPS1 feedback input in fixed-voltage mode. VIN (Pin 16) High Voltage Power Supply Input for 5V/3.3V LDO and Feed-forward ON-Time circuitry. VREG5 (Pin 17) 5V Linear Regulator Output.VREG5 is also the supply voltage for the low-side MOSFET driver and analog supply voltage for the device. NC (Pin 18) (RT8223A) No Internal Connection. ENC (Pin 18) (RT8223B) SMPSx Enable Input. Pull up to VREG3 or VREG5 to turn on both switcher channels. Short to GND to shutdown them. LGATE1 (Pin 19) SMPS1 Synchronous Rectifier Gate Drive Output. LGATE1 swings between PGND and VREG5. PHASE1 (Pin 20) Inductor Connection for SMPS1. PHASE1 is the internal lower supply rail for the UGATE1 high side gate driver. PHASE1 is also the current sense input for the SMPS1. UGATE1 (Pin 21) High-Side MOSFET Floating Gate Driver Output for SMPS1. UGATE1 swings between PHASE1 and BOOT1. BOOT1 (Pin 22) Boost Flying Capacitor Connection for SMPS1. Connect to an external capacitor according to the typical application circuits. PGOOD (Pin 23) Power Good Output for channel 1 and channel 2. (Logical AND) DS8223A/B-04 April 2011 www.richtek.com 7 RT8223A/B Absolute Maximum Ratings (Note 1) VIN, EN to GND -------------------------------------------------------------------------------------------------------------- –0.3V to 30V z PHASEx to GND DC ------------------------------------------------------------------------------------------------------------------------------- –0.3V to 30V < 20ns ------------------------------------------------------------------------------------------------------------------------- −8V to 38V z BOOTx to PHASEx --------------------------------------------------------------------------------------------------------- –0.3V to 6V z ENTRIPx, SKIPSEL, TONSEL, PGOOD, to GND ------------------------------------------------------------------- –0.3V to 6V z VREG5, VREG3, FBx, VOUTx, ENC, REF to GND ---------------------------------------------------------------- –0.3V to 6V z UGATEx to PHASEx DC ------------------------------------------------------------------------------------------------------------------------------- –0.3V to 6V < 20ns ------------------------------------------------------------------------------------------------------------------------- −5V to 7.5V z LGATEx to GND DC ------------------------------------------------------------------------------------------------------------------------------- –0.3V to 6V < 20ns ------------------------------------------------------------------------------------------------------------------------- −2.5V to 7.5V z Power Dissipation, PD @ TA = 25°C WQFN-24L 4x4 -------------------------------------------------------------------------------------------------------------- 1.923W z Package Thermal Resistance (Note 2) WQFN-24L 4x4, θJA --------------------------------------------------------------------------------------------------------- 52°C/W WQFN-24L 4x4, θJC -------------------------------------------------------------------------------------------------------- 7°C/W z Lead Temperature (Soldering, 10 sec.) --------------------------------------------------------------------------------- 260°C z Junction Temperature ------------------------------------------------------------------------------------------------------- 150°C z Storage Temperature Range ---------------------------------------------------------------------------------------------- –65°C to 150°C z ESD Susceptibility (Note 3) HBM (Human Body Mode) ------------------------------------------------------------------------------------------------ 2kV MM (Machine Mode) -------------------------------------------------------------------------------------------------------- 200V z Recommended Operating Conditions z z z (Note 4) Input Voltage, VIN ------------------------------------------------------------------------------------------------------------ 6V to 25V Junction Temperature Range ---------------------------------------------------------------------------------------------- −40°C to 125°C Ambient Temperature Range ---------------------------------------------------------------------------------------------- −40°C to 100°C www.richtek.com 8 DS8223A/B-04 April 2011 RT8223A/B Electrical Characteristics (VIN = 12V, EN = ENC = 5V, ENTRIP1 = ENTRIP2 = 2V, No Load on VREG5, VREG3, VOUT1, VOUT2 and REF, TA = 25°C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit Input Supply VIN Standby Supply Current VIN Shutdown Supply Current Quiescent Power Consumption IVIN_SBY VIN = 6V to 25V, Both SMPS Off, EN = 5V, ENC = GND -- 200 -- μA IVIN_SHDH VIN = 6V to 25V, ENTRIPx = EN = GND -- 20 40 μA Both SMPSs On, FBx = SKIPSEL = REF VOUT1 = 5.3V, VOUT2 = 3.5V (Note 5) -- 5 7 mW 4.975 5.05 5.125 V 3.285 3.33 3.375 V SMPS Output and FB Voltage VOUT1 Output Voltage in Fixed Mode VOUT2 Output Voltage in Fixed Mode FBx in Output Adjustable Mode Output Voltage Adjustment Range FBx Adjustable-mode Threshold Voltage V OUT2 VIN = 6V to 25V, FB1= REF or 5V, SKIPSEL = REF VIN = 6V to 25V, FB2 = REF or 5V, SKIPSEL = REF FBx VIN = 6V to 25V 1.975 2 2.025 V V OUT x SMPS1, SMPS2 2 -- 5.5 V Fixed or Adj-Mode comparator threshold 0.2 0.4 0.55 V Either SMPS, SKIPSEL = REF, 0 to 5A Either SMPS, SKIPSEL = VREG5, 0 to 5A Either SMPS, SKIPSEL = GND, 0 to 5A Either SMPS, VIN = 6V to 25V ----- −0.1 −1.7 −1.5 0.005 ----- V OUT1 = 5.05V 1895 2105 2315 V OUT2 = 3.33V 999 1110 1221 TONSEL = REF V OUT1 = 5.05V V OUT2 = 3.33V 1227 647 1403 740 1579 833 TONSEL = VREG5 V OUT1 = 5.05V V OUT2 = 3.33V 895 475 1052 555 1209 635 200 300 400 ns SKIPSEL = VREG5 or VREG3 20 28 -- kHz Zero to Full Limit from ENTRIPx Enable -- 2 -- ms V ENTRIPx = VREG5, GND−PHASEx 180 200 220 mV V ENTRIPx = 0.9V 9.4 10 10.6 μA -- 1600 -- PPM/°C 0.5 -- 2 V V OUT1 DC Load Regulation V LOAD Line Regulation VLINE % %/V On Time TONSEL = GND On-Time Pulse Width Minimum Off-Time Ultrasonic Mode Frequency tUGATEx tLGATEx ns Soft Start Soft-Start Time tSSx Current Sense Current Limit Threshold (Default) ENTRIPx Source Current ENTRIPx Current Temperature Coefficient ENTRIPx Adjustment Range IENTRIPx TC IENTRIPx V ENTRIPx = IENTRIPx x R ENTRIPx To be continued DS8223A/B-04 April 2011 www.richtek.com 9 RT8223A/B Parameter Symbol Current Limit Threshold Test Conditions GND−PHASEx, VENTRIPx =2V SKIPSEL = VREG5 or GND, GND−PHASEx Zero-Current Threshold Min Typ Max Unit 180 200 220 mV -- 3 -- mV 4.8 5 5.2 V 3.2 3.33 3.46 V Internal Regulator and Reference VOUT1 = GND, 6V < VIN < 25V, 0 < I VREG5 < 70mA VOUT2 = GND, 6V < VIN < 25V, 0 < I VREG3 < 70mA VREG5 Output Voltage VVREG5 VREG3 Output Voltage VVREG3 VREG5 Short Current IVREG5 VREG5 = GND, VOUT1 = GND -- 175 275 mA VREG3 Short Current IVREG3 VREG3 = GND, VOUT2 = GND -- 175 275 mA 4.53 4.66 4.79 V 2.98 3.08 3.18 V -- 1.5 3 Ω VREG5 Switchover Threshold to VOUT1 VREG3 Switchover Threshold VSW3 Rising Edge at VOUT1 Regulation Point Rising Edge at VOUT2 Regulation Point, Hysteresis = 6% VREGx Switchover Equivalent RSW Resistance REF Output Voltage VREF No External Load 1.98 2 2.02 V REF Load Regulation 0 < ILOAD < 50uA -- 10 -- mV REF Sink Current REF in Regulation 5 -- -- μA SMPSx off -- 2.5 -- V Rising Edge -- 4.35 4.5 V Falling Edge 3.9 4.05 4.25 V PGOOD Detect (FBx Rising Edge) −11 −7.5 −4 Hysteresis -- 8 -- PGOOD Propagation Delay Falling Edge, 50mV Overdrive -- 10 -- μs PGOOD Leakage Current High State, Forced to 5.5V -- -- 1 μA PGOOD Output Low Voltage ISINK = 4mA -- -- 0.3 V 108 111 115 % -- 10 -- μs UVP Detect (FBx Falling Edge) 46 52 58 Hysteresis -- 8 -- -- 3 -- ms -- 150 -- °C -- 10 -- °C 10 2.5 60 -- --- mA mA VREGx to VOUTx, 10mA UVLO VREG3 UVLO Threshold VREG5 UVLO Threshold Power Good PGOOD Threshold VPGOODx % Fault Detection OVP Trip Threshold VFB_OVP FBx with Respect to Internal Reference OVP Propagation Delay UVP Trip Threshold VUV UVP Shutdown Blanking Time tSHDN_UVP From ENTRIPx Enable % Thermal Shutdown Thermal Shutdown TSHDN Thermal Shutdown Hysteresis Discharge VOUTx Discharge Current VREGx Discharge Current IDISx ENTRIPx = ENC = 0V, VOUTx = 0.5V EN = 0V, VREGx = 0.5V To be continued www.richtek.com 10 DS8223A/B-04 April 2011 RT8223A/B Parameter Symbol Test Conditions Min Typ Max Low Level (Internal Fixed VOUTx) -- -- 0.2 High Level (Internal Fixed VOUTx) 4.5 -- -- Low Level (DEM Mode) -- -- 0.8 REF Level (PWM Mode) 1.8 -- 2.3 High Level (Ultrasonic Mode) Unit Logic Input FB1/FB2 Input Voltage SKIPSEL Input Voltage ENTRIPx Input Voltage V ENTRIPx 2.7 -- -- Low Level (SMPSs Off) -- -- 0.35 On Level (SMPSs On) 0.5 -- 2 High Level (SMPSs Off) 4.5 -- -- -- -- 0.4 Enable 2.4 -- -- Open 2.4 3.3 4.2 V EN = 0.2V (Source) 1 3 5 V EN = 3.3V (Sink) --- 3 -- 8 0.6 2 -- -- -1.8 2.7 −1 −1 ------ 0.8 2.3 -1 1 VREG5 to BOOTx -- 20 -- UGATEx, High state -- 3 6 UGATEx, Low state LGATEx, High State --- 1.5 2.2 4 5 LGATEx, Low State LGATEx Rising --- 0.6 30 1.5 -- UGATEx Rising -- 40 -- Shutdown EN Voltage V EN EN Current IEN ENC Threshold Voltage (RT8223B) VENC TONSEL Setting Voltage Input Leakage Current Internal BOOT Switch Internal Boost Charging Switch On-Resistance Shutdown Enable VOUT1/V OUT2 = 200kHz/250kHz VOUT1/V OUT2 = 300kHz/375kHz VOUT1/V OUT2 = 400kHz/500kHz TONSEL, SKIPSEL = 0V or 5V ENC = 0V or 5V (RT8223B) V V V V μA V V μA Ω Power MOSFET Drivers UGATEx On-Resistance LGATEx On-Resistance Dead Time Ω ns Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. θJA is measured in natural convection at TA = 25°C on a high effective thermal conductivity four-layer test board of JEDEC 51-7 thermal measurement standard. The measurement case positions of θJC are on the lead of the SOP package and the expose pad for the SOP(Exposed Pad) package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. PVIN + PVREG5 DS8223A/B-04 April 2011 www.richtek.com 11 RT8223A/B Typical Operating Characteristics VOUT1 Output Efficiency vs. Load Current VOUT2 Output Efficiency vs. Load Current 100 100 90 90 DEM Mode 80 70 Efficiency (%) Efficiency (%) 80 Ultrasonic Mode 60 50 PWM Mode 40 30 20 DEM Mode 70 60 Ultrasonic Mode 50 PWM Mode 40 30 20 VIN = 8V, TONSEL = GND, EN = VIN, ENTRIP1 = 0.91V, ENTRIP2 = GND 10 0 0.001 0.01 0.1 1 VIN = 8V, TONSEL = GND, EN = VIN, ENTRIP1 = GND, ENTRIP2 = 0.91V 10 0 0.001 10 0.01 Load Current (A) VOUT1 Output Efficiency vs. Load Current 100 90 90 Ultrasonic Mode Efficiency (%) Efficiency (%) 80 DEM Mode 70 60 50 PWM Mode 40 30 20 0 0.001 DEM Mode 70 Ultrasonic Mode 60 50 PWM Mode 40 30 0.01 0.1 1 VIN = 12V, TONSEL = GND, EN = VIN, ENTRIP1 = GND, ENTRIP2 = 0.91V, 10 0 0.001 10 0.01 Load Current (A) 100 90 90 Efficiency (%) 70 Ultrasonic Mode 60 PWM Mode 40 30 20 0 0.001 VIN = 20V, TONSEL = GND, EN = VIN, ENTRIP1 = 0.91V, ENTRIP2 = GND 0.1 Load Current (A) www.richtek.com 12 70 DEM Mode 60 Ultrasonic Mode 50 40 PWM Mode 30 20 0.01 10 80 DEM Mode 10 1 VOUT2 Output Efficiency vs. Load Current 100 50 0.1 Load Current (A) VOUT1 Output Efficiency vs. Load Current Efficiency (%) 10 20 VIN = 12V, TONSEL = GND, EN = VIN, ENTRIP1 = 0.91V, ENTRIP2 = GND 10 80 1 VOUT2 Output Efficiency vs. Load Current 100 80 0.1 Load Current (A) 1 10 VIN = 20V TONSEL = GND, EN = VIN, ENTRIP1 = GND, ENTRIP2 = 0.91V 10 0 0.001 0.01 0.1 1 10 Load Current (A) DS8223A/B-04 April 2011 RT8223A/B VOUT1 Output Switching Frequency vs. Load Current VOUT2 Output Switching Frequency vs. Load Current 225 300 VIN = 8V, TONSEL = GND, EN = VIN, ENTRIP1 = 0.91V, ENTRIP2 = GND 275 Switching Frequency (kHz) Switching Frequency (kHz) 250 200 PWM Mode 175 150 125 100 75 50 Ultrasonic Mode 25 0 0.001 250 PWM Mode 225 200 175 150 125 100 75 Ultrasonic Mode 50 25 DEM Mode 0.01 VIN = 8V, TONSEL = GND, EN = VIN, ENTRIP1 = GND, ENTRIP2 = 0.91V 0.1 1 0 0.001 10 DEM Mode 0.01 Load Current (A) 300 VIN = 12V, TONSEL = GND, EN = VIN, ENTRIP1 = 0.91V, ENTRIP2 = GND 275 200 PWM Mode 175 150 125 100 75 50 Ultrasonic Mode 25 0.01 0.1 VIN = 12V, TONSEL = GND, EN = VIN, ENTRIP1 = GND, ENTRIP2 = 0.91V 250 PWM Mode 225 200 175 150 125 100 75 Ultrasonic Mode 50 25 DEM Mode 0 0.001 1 0 0.001 10 DEM Mode 0.01 Load Current (A) 300 VIN = 20V, TONSEL = GND, EN = VIN, ENTRIP1 = 0.91V, ENTRIP2 = GND 275 200 175 PWM Mode 150 125 100 75 50 Ultrasonic Mode 25 0 0.001 0.1 Load Current (A) DS8223A/B-04 April 2011 10 1 VIN = 20V, TONSEL = GND, EN = VIN, ENTRIP1 = GND, ENTRIP2 = 0.91V 250 225 PWM Mode 200 175 150 125 100 75 50 Ultrasonic Mode 25 DEM Mode 0.01 1 VOUT2 Output Switching Frequency vs. Load Current Switching Frequency (kHz) Switching Frequency (kHz) 225 0.1 Load Current (A) VOUT1 Output Switching Frequency vs. Load Current 250 10 VOUT2 Output Switching Frequency vs. Load Current Switching Frequency (kHz) Switching Frequency (kHz) 225 1 Load Current (A) VOUT1 Output Switching Frequency vs. Load Current 250 0.1 10 0 0.001 DEM Mode 0.01 0.1 1 10 Load Current (A) www.richtek.com 13 RT8223A/B VOUT1 Output Voltage vs. Load Current 5.108 Output Voltage (V) 5.102 VOUT2 Output Voltage vs. Load Current 3.378 VIN = 12V, TONSEL = GND, EN = VIN, ENTRIP1 = 0.91V, ENTRIP2 = GND Ultrasonic Mode 5.096 5.090 DEM Mode 5.084 5.078 5.072 5.066 PWM Mode 5.060 VIN = 12V, TONSEL = GND, EN = VIN, ENTRIP1 = GND, ENTRIP2 = 0.91V 3.372 Output Voltage (V) 5.114 3.366 Ultrasonic Mode 3.360 3.354 DEM Mode 3.348 3.342 PWM Mode 3.336 3.330 5.054 5.048 0.001 0.01 0.1 1 3.324 0.001 10 0.01 0.1 Load Current (A) 4.978 3.324 VIN = 12V, TONSEL = GND, EN = VIN, ENTRIP1 = ENTRIP2 = GND 3.322 VIN = 12V, TONSEL = GND, EN = VIN, ENTRIP1 = ENTRIP2 = GND 3.320 Output Voltage (V) Output Voltage (V) 4.976 4.974 4.972 4.970 4.968 4.966 3.318 3.316 3.314 3.312 4.964 3.310 4.962 3.308 3.306 4.960 0 10 20 30 40 50 60 0 70 10 20 VREF vs. Output Current 2.0028 40 50 60 70 Battery Current vs. Input Voltage 100 VIN = 12V, TONSEL = GND, EN = VIN, ENTRIP1 = ENTRIP2 = GND Battery Current (mA) 2.0026 2.0024 V REF (V) 30 Output Current (mA) Output Current (mA) 2.0030 10 VREG3 Output Voltage vs. Output Current VREG5 Output Voltage vs. Output Current 4.980 1 Load Current (A) 2.0022 2.0020 2.0018 2.0016 2.0014 PWM Mode 10 Ultrasonic Mode 1 DEM Mode No Load, TONSEL = GND, EN = VIN, ENTRIP1 = ENTRIP2 = 0.91V 2.0012 2.0010 0.1 -10 0 10 20 30 Output Current (uA) www.richtek.com 14 40 50 7 9 11 13 15 17 19 21 23 25 Input Voltage (V) DS8223A/B-04 April 2011 RT8223A/B Shutdown Input Current vs. Input Voltage Standby Input Current vs. Input Voltage 22 No Load, EN = VIN, ENTRIP1 = ENTRIP2 = GND Shutdown Input Current (uA) Standby Input Current (uA) 252 250 248 246 244 242 No Load, EN = GND, ENTRIP1 = ENTRIP2 = GND 20 18 16 14 12 10 8 240 7 9 11 13 15 17 19 21 23 7 25 9 11 13 15 17 19 Input Voltage (V) Input Voltage (V) VREF vs. Temperature Start Up 21 23 25 2.011 2.008 VREG5 (5V/Div) VREG3 (5V/Div) VREF (V) 2.005 2.002 1.999 REF (5V/Div) 1.996 1.993 EN (10V/Div) VIN = 12V, ENTRIP1 = ENTRIP2 = GND, EN = VIN, TONSEL = GND No Load, VIN = 12V, TONSEL = GND, EN = VIN, ENTRIP1 = ENTRIP2 = GND 1.990 -50 -25 0 25 50 75 100 Time (400μs/Div) 125 Temperature (°C) VOUT1 Start Up VOUT1 Start Up No Load, VIN = 12V, TONSEL = GND, EN = VIN VOUT1 (5V/Div) VOUT1 (5V/Div) Inductor Current (2A/Div) Inductor Current (2A/Div) ENTRIP1 (2V/Div) PGOOD (10V/Div) Heavy Load, VIN = 12V, TONSEL = GND, EN = VIN ENTRIP1 (2V/Div) ENTRIP1 = ENTRIP2 = 0.91V Time (400μs/Div) DS8223A/B-04 April 2011 PGOOD (10V/Div) ENTRIP1 = NTRIP2 = 0.91V, IOUT1 = 4A Time (400μs/Div) www.richtek.com 15 RT8223A/B VOUT2 Start Up VOUT2 Start Up Heavy Load, VIN = 12V, TONSEL = GND, EN = VIN No Load, VIN = 12V, TONSEL = GND, EN = VIN VOUT2 (5V/Div) VOUT2 (5V/Div) Inductor Current (2A/Div) Inductor Current (2A/Div) ENTRIP2 (2V/Div) PGOOD (10V/Div) ENTRIP1 = ENTRIP2 = 0.91V ENTRIP2 (2V/Div) PGOOD (10V/Div) Time (400μs/Div) Time (400μs/Div) VOUT1 Delay Start VOUT2 Delay Start No Load, VIN = 12V, TONSEL = GND, EN = VIN VOUT1 (5V/Div) No Load, VIN = 12V, TONSEL = GND, EN = VIN VOUT2 (5V/Div) VOUT1 (5V/Div) VOUT2 (5V/Div) ENTRIP1 (1V/Div) ENTRIP1 (1V/Div) ENTRIP2 (1V/Div) ENTRIP2 (1V/Div) Time (400μs/Div) VOUT1 PWM Mode Load Transient Response Time (400μs/Div) VOUT2 PWM Mode Load Transient Response VIN = 12V, TONSEL = GND, EN = VIN, SKIPSEL = GND, IOUT1 = 0A to 6A VIN = 12V, TONSEL = GND, EN = VIN, SKIPSEL = GND, IOUT2 = 0A to 6A VOUT1_ac (50mV/Div) VOUT2_ac (50mV/Div) Inductor Current (5A/Div) Inductor Current (5A/Div) UGATE1 (20V/Div) LGATE1 (10V/Div) UGATE2 (20V/Div) LGATE2 (10V/Div) Time (20μs/Div) www.richtek.com 16 ENTRIP1 = ENTRIP2 = 0.91V Time (20μs/Div) DS8223A/B-04 April 2011 RT8223A/B OVP Power Off from ENTRIP1 No Load, VIN = 12V, TONSEL = GND, EN = VIN SKIPSEL = REF No Load, VIN = 12V, TONSEL = GND, EN = VIN SKIPSEL = GND VOUT1 (5V/Div) UGATE1 (20V/Div) VOUT1 (5V/Div) LGATE1 (5V/Div) VOUT2 (2V/Div) ENTRIP1 (1V/Div) PGOOD (5V/Div) Time (40ms/Div) Time (4ms/Div) UVP VIN = 12V, TONSEL = GND, EN = VIN SKIPSEL = GND VOUT1 (5V/Div) Inductor Current (5A/Div) UGATE1 (20V/Div) LGATE1 (10V/Div) Time (20μs/Div) DS8223A/B-04 April 2011 www.richtek.com 17 RT8223A/B Application Information The RT8223A/B is a dual, Mach ResponseTM DRVTM dual ramp valley mode synchronous buck controller. The controller is designed for low voltage power supplies for notebook computers. Richtek's Mach Response TM technology is specifically designed for providing 100ns “instant-on” response to load steps while maintaining a relatively constant operating frequency and inductor operating point over a wide range of input voltages. The topology circumvents the poor load-transient timing problems of fixed-frequency current mode PWMs while avoiding the problems caused by widely varying switching frequencies in conventional constant on-time and constant off-time PWM schemes. The DRV TM mode PWM modulator is specifically designed to have better noise immunity for such a dual output application. The RT8223A/ B includes 5V (VREG5) and 3.3V (VREG3) linear regulators. VREG5 linear regulator can step down the battery voltage to supply both internal circuitry and gate drivers. The synchronous-switch gate drivers are directly powered from VREG5. When VOUT1 voltage is above 4.66V, an automatic circuit will switch the power of the device from VREG5 linear regulator from VOUT1. PWM Operation The Mach ResponseTM DRVTM mode controller relies on the output filter capacitor's effective series resistance (ESR) to act as a current sense resistor, so the output ripple voltage provides the PWM ramp signal. Refer to the RT8223A/B's function block diagram, the synchronous high-side MOSFET will be turned on at the beginning of each cycle. After the internal one-shot timer expires, the MOSFET will be turned off. The pulse width of this one shot is determined by the converter's input voltage and the output voltage to keep the frequency fairly constant over the input voltage range. Another one shot sets a minimum off-time (300ns typ.). The on-time one shot will be triggered if the error comparator is high, the low side switch current is below the current limit threshold, and the minimum off-time one shot has timed out. PWM Frequency and On-Time Control The Mach ResponseTM control architecture runs with pseudo-constant frequency by feed forwarding the input www.richtek.com 18 and output voltage into the on-time one shot timer. The high-side switch on-time is inversely proportional to the input voltage as measured by the VIN, and proportional to the output voltage. There are two benefits of a constant switching frequency. The first is the frequency can be selected to avoid noise sensitive regions such as the 455kHz IF band. The second is the inductor ripple-current operating point remains relatively constant, resulting in easy design methodology and predictable output voltage ripple. The frequency for 3V SMPS is set at 1.25 times higher than the frequency for 5V SMPS. This is done to prevent audio-frequency “beating” between the two sides, which switch asynchronously for each side. The frequencies are set by TONSEL pin connection as Table1. The on-time is given by : On-Time = K x (VOUT / VIN) where “K” is set by the TONSEL pin connection (Table 1). The on-time guaranteed in the Electrical Characteristics tables are influenced by switching delays in the external high-side power MOSFET. Two external factors that influence switching-frequency accuracy are resistive drops in the two conduction loops (including inductor and PC board resistance) and the dead-time effect. These effects are the largest contributors to the change of frequency with changing load current. The dead time effect increases the effective on-time, reducing the switching frequency as one or both dead times. It occurs only in PWM mode (SKIPSEL= REF) when the inductor current reverses at light or negative load currents. With reversed inductor current, the inductor's EMF causes PHASEx to go high earlier than normal, extending the on-time by a period equal to the low-to-high dead time. For loads above the critical conduction point, the actual switching frequency is : f = (VOUT + VDROP1) / (tON x (VIN + VDROP1 -VDROP2) ) where VDROP1 is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and PC board resistances; VDROP2 is the sum of the resistances in the charging path; and tON is the on-time calculated by the RT8223A/B. DS8223A/B-04 April 2011 RT8223A/B Table 1. TONSEL Connection and Switching Frequency SMPS 1 SMPS 1 SMPS 2 TON K-Factor Frequency K-Factor (us) (kHz) (us) GND 5 200 4 REF 3.33 300 2.67 VREG5 or 2.5 400 2 VREG3 TON GND REF VREG5 or VREG3 SMPS 2 Frequency (kHz) 250 375 Approximate K-Factor Error (%) ±10 ±10 500 ±10 Operation Mode Selection (SKIPSEL) The RT8223A/B supports three operation modes : Diode Emulation Mode, Ultrasonic Mode, and Forced CCM Mode. Diode-Emulation Mode (SKIPSEL = GND) In Diode Emulation mode, The RT8223A/B automatically reduces switching frequency at light load conditions to maintain high efficiency. This reduction of frequency is achieved smoothly and without increase of VOUT ripple or load regulation. As the output current decreases from heavy load condition, the inductor current is also reduced, and eventually comes to the point that its valley touches zero current, which is the boundary between continuous conduction and discontinuous conduction modes. By emulating the behavior of diodes, the low-side MOSFET allows only partial of negative current when the inductor free-wheeling current reach negative. As the load current is further decreased, it takes longer and longer to discharge the output capacitor to the level that requires the next “ON” cycle. The on-time is kept the same as that in the heavy-load condition. In reverse, when the output current increases from light load to heavy load, the switching frequency increases to the preset value as the inductor current reaches the continuous conduction. The transition load point to the light load operation can be calculated as follows (Figure 1) : ILOAD(SKIP) (VIN − VOUT ) ≈ × TON 2L where Ton is the On-time. DS8223A/B-04 April 2011 IL Slope = (VIN -VOUT) / L iL, peak iLoad = iL, peak / 2 0 tON t Figure 1. Boundary condition of CCM/DCM The switching waveforms may appear noisy and asynchronous when light loading causes Diode-Emulation operation, but this is a normal operating condition that results in high light load efficiency. Trade offs in PFM noise vs. light load efficiency are made by varying the inductor value. Generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. Penalties for using higher inductor values include larger physical size and degraded load transient response (especially at low input-voltage levels). Ultrasonic Mode (SKIPSEL = VREG5 or VREG3) Connecting SKIPSEL to VREG5 or VREG3 activates a unique Diode-Emulation mode with a minimum switching frequency of 25kHz. This ultrasonic mode eliminates audio-frequency modulation that would otherwise be present when a lightly loaded controller automatically skips pulses. In ultrasonic mode, the low-side switch gate driver signal is OR with an internal oscillator (>25kHz). Once the internal oscillator is triggered, the ultrasonic controller pulls LGATEx high, turning on the low side MOSFET to induce a negative inductor current. After the output voltage across the REF, the controller turns off the low-side MOSFET (LGATEx pulled low) and triggers a constant on-time (UGATEx driven high). When the ontime has expired, the controller re-enables the low-side MOSFET until the controller detects that the inductor current dropped below the zero-crossing threshold. Forced CCM Mode (SKIPSEL = REF) The low-noise, forced CCM mode (SKIPSEL = REF) disables the zero-crossing comparator, which controls the low side switch on-time. This causes the low side gate driver waveform to become the complement of the high www.richtek.com 19 RT8223A/B side gate-driver waveform. This in turn causes the inductor current to reverse at light loads as the PWM loop to maintain a duty ratio of VOUT/VIN. The benefit of forcedCCM mode is to keep the switching frequency fairly constant, but it comes at a cost : The no load battery current can be 10mA to 40mA, depending on the external MOSFETs. IL IL, peak ILoad ILIM t 0 Figure 2. “valley” Current-Limit Reference and linear Regulators (REF, VREGx) The 2V reference (REF) is accurate within ±1% over temperature, making REF useful as a precision system reference. Bypass REF to GND with a 0.22μF (min) capacitor. REF can supply up to 50uA for external loads. Loading REF reduces the VOUTx output voltage slightly because of the reference load regulation error. VREG5 regulator supplies total of 70mA for internal and external loads, including MOSFET gate driver and PWM controller. VREG3 regulator supplies up to 70mA for external loads. Bypass VREG5 and VREG3 with a 4.7μF (min) capacitor; use an additional 1μF per 5mA of internal and external load. When the 5V main output voltage is above the VREG5 switchover threshold, an internal 1.5Ω N-MOSFET switch connects VOUT1 to VREG5 while simultaneously shutting down the VREG5 linear regulator. Similarly, when the 3.3V main output voltage is above the VREG3 switchover threshold, an internal 1.5Ω N-MOSFET switch connects VOUT2 to VREG3 while simultaneously shutting down the VREG3 linear regulator. It can decrease the power dissipation from the same battery, because the converted efficiency of SMPS is better than the converted efficiency of linear regulator. Current Limit Setting (ENTRIPx) The RT8223A/B has cycle-by-cycle current limiting control. The current limit circuit employs a unique “valley” current sensing algorithm. If the magnitude of the current sense signal at PHASEx is above the current limit threshold, the PWM is not allowed to initiate a new cycle (Figure 2). The actual peak current is greater than the current limit threshold by an amount equal to the inductor ripple current. Therefore, the exact current limit characteristic and maximum load capability are a function of the sense resistance, inductor value, battery and output voltage. www.richtek.com 20 The RT8223A/B uses the on resistance of the synchronous rectifier as the current sense element. Use the worse case maximum value for RDS(ON) from the MOSFET datasheet, and add a margin of 0.5%/°C for the rise in RDS(ON) with temperature. The RILIM resistor between the ENTRIPx pin and GND sets the over current threshold. The resistor RILIM is connected to a 10μA current source from ENTRIPx. When the voltage drop across the sense resistor or low side MOSFET equals 1/10 the voltage across the RILIM resistor, positive current limit will be activated. The high side MOSFET will not be turned on until the voltage drop across the MOSFET falls below 1/10 the voltage across the RILIM resistor. Choose a current limit resistor by following equation : VILIM = (RILIM x 10μA) / 10 = IILIM x RDS(ON) RILIM = (IILIM x RDS(ON)) x 10 / 10μA Carefully observe the PC board layout guidelines to ensure that noise and DC errors do not corrupt the current sense signal at PHASEx and GND. Mount or place the IC close to the low side MOSFET. MOSFET Gate Driver (UGATEx, LGATEx) The high side driver is designed to drive high current, low RDS(ON) N-MOSFET(s). When configured as a floating driver, 5-V bias voltage is delivered from VREG5 supply. The average drive current is also calculated by the gate charge at VGS = 5 V times switching frequency. The instantaneous drive current is supplied by the flying capacitor between BOOTx and PHASEx pins. A dead time to prevent shoot through is internally generated between high side MOSFET off to low side MOSFET on, and low side MOSFET off to high side MOSFET on. The low side driver is designed to drive high current low RDS(ON) N-MOSFET(s). The internal pull down transistor DS8223A/B-04 April 2011 RT8223A/B that drives LGATEx low is robust, with a 0.6Ω typical onresistance. A 5V bias voltage is delivered from VREG5 supply. The instantaneous drive current is supplied by an input capacitor connected between VREG5 and GND. For high current applications, some combinations of high and low side MOSFETs might be encountered that will cause excessive gate-drain coupling, which can lead to efficiency-killing, EMI-producing shoot-through currents. This is often remedied by adding a resistor in series with BOOTx, which increases the turn-on time of the high side MOSFET without degrading the turn-off time (Figure 3). V IN BOOTx 10 UGATEx Output Over Voltage Protection (OVP) The output voltage can be continuously monitored for over voltage. When over voltage protection is enabled, if the output voltage exceeds 11% of its set voltage threshold, the over voltage protection will be triggered and the LGATEx low-side gate drivers will be forced high. This activates the low side MOSFET switch, which rapidly discharges the output capacitor and pulls the input voltage downward. RT8223A/B will be latched once OVP is triggered and can only be released by EN power-on reset. There is a 10μs delay built into the over voltage protection circuit to prevent false transition. Note that LGATEx latching high causes the output voltage to dip slightly negative when energy has been previously stored in the LC tank circuit. For loads that cannot tolerate a negative voltage, place a power Schottky diode across the output to act as a reverse polarity clamp. PHASEx Figure 3. Reducing the UGATEx Rise Time Soft-Start A build-in soft-start is used to prevent surge current from power supply input after ENTRIPx is enabled. The typical soft-start duration is 2ms period. Furthermore, the maximum allowed current limit is segmented in 5 steps: 20%, 40%, 60%, 80% and 100% during the 2ms period. UVLO Protection The RT8223A/B has VREG5 under voltage lock out protection (UVLO). When the VREG5 voltage is lower than 4.2V (typ.) and the VREG3 voltage is lower than 2.5V (typ.), both switch power supplies will be shut off. This is a non-latch protection. Power Good Output (PGOOD) The PGOOD is an open-drain type output and requires a pull-up resistor. PGOOD is actively held low in soft-start, standby, and shutdown. It will be released when both output voltage are above 92.5% of nominal regulation point. The PGOOD goes low if either output turns off or is 10% below its nominal regulator point. DS8223A/B-04 April 2011 If the over voltage condition is caused by a short in highside switch, turning the low side MOSFET on 100% creates an electrical short between the battery and GND, blowing the fuse and disconnecting the battery from the output. Output Under voltage Protection (UVP) The output voltage can be continuously monitored for under voltage protection. When under voltage protection is enabled, if the output is less than 70% of its set voltage threshold, under voltage protection will be triggered, then both UGATEx and LGATEx gate drivers are forced low while entering soft-discharge mode. During soft-start, the UVP will be blanked around 3ms. Thermal Protection The RT8223A/B provides thermal shutdown to prevent the overheat damage. Thermal shutdown occurs when the die temperature exceeds +150°C. All internal circuitry shuts down during thermal shutdown. The RT8223A/B triggers thermal shutdown if VREGx is not supplied from VOUTx, while input voltage on VIN and drawing current from VREGx are too high. Even if VREGx is supplied from VOUTx, overloading the VREGx causes large power dissipation on automatic switches, which may result in thermal shutdown. www.richtek.com 21 RT8223A/B Discharge Mode (Soft Discharge) When ENTRIPx is low and a transition to standby, shutdown mode occurs, or the output under voltage fault latch is set, the outputs discharge mode will be triggered. During discharge mode, there is one path to discharge the outputs capacitor residual charge. That is output capacitor discharge to GND through an internal MOS switch. Shutdown Mode VREG5 connects to VOUT1 through an internal switch only when VOUT1 is above the VREG5 automatic switch threshold (4.66V). VREG3 connects to VOUT2 through an internal switch only when VOUT2 is above the VREG3 automatic switch threshold (3V). This is the most effective way when the fixed output voltages are used. Once VREGx is supplied from VOUTx, the internal linear regulator turns off. This reduces internal power dissipation and improves efficiency when the VREGx is powered with a high input voltage. The RT8223A/B SMPS1, SMPS2, VREG3 and VREG5 have independent enabling control. Drive EN, ENTRIP1, ENTRIP2 and ENC below the precise input falling edge trip level to place the RT8223A/B in its low power shutdown state. The RT8223A/B consumes only 20μA of input current while in shutdown. VIN PHASEx LGATEx VOUTx FBx PGND Power-Up Sequencing and On/Off Controls (ENTRIPx, ENC) ENTRIP1 and ENTRIP2 control SMPS power-up sequencing. When the RT8223A/B applies in the single channel mode, ENTRIP1 or ENTRIP2 enables the respective outputs when ENTRIPx voltage rises above 0.4V. Furthermore, the RT8223A/B applies in the dual channel mode. ENC enables the outputs when ENC voltage rises above 2V. If both of ENTRIP1 and ENTRIP2 become higher than the enable threshold voltage at a different time (without 60μs), one can force the latter one output starts after the former one regulates. Output Voltage Setting (FBx) Connect FBx directly to GND or VREG5 to enable the fixed, SMPS output voltages (3.3V and 5V). Connect a resistor voltage divider at the FBx between the VOUTx and GND to adjust the respective output voltage between 2V and 5.5V (Figure 4). Choose R2 to be approximately 10kΩ, and solve for R1 using the equation : ⎡ ⎤ VOUTx = VFBx × ⎢1 + ⎛⎜ R1 ⎞⎟ ⎥ ⎣ ⎝ R2 ⎠ ⎦ where VFBx is 2V (typ.). www.richtek.com 22 VOUTx UGATEx R1 R2 GND Figure 4. Setting VOUTx with a Resistor-Divider Output Inductor Selection The switching frequency (on-time) and operating point (% ripple or LIR) determine the inductor value as shown as follows : L= TON × (VIN − VOUTx ) LIR × ILOAD(MAX) where LIR is the ratio of the peak to peak ripple current to the average inductor current. Find a low loss inductor having the lowest possible DC resistance that fits in the allotted dimensions. Ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200kHz. The core must be large enough not to saturate at the peak inductor current (IPEAK) : IPEAK = ILOAD(MAX) + [(LIR / 2) x ILOAD(MAX)] This inductor ripple current also impacts transient-response performance, especially at low VIN − VOUTx differences. Low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. The peak amplitude of the output transient VSAG is also a function of the output transient. The VSAG also features a function of the DS8223A/B-04 April 2011 RT8223A/B maximum duty factor, which can be calculated from the on-time and minimum off-time : VSAG V (ΔILOAD )2 × L × ⎛⎜ K OUTx + TOFF(MIN) ⎞⎟ VIN ⎝ ⎠ = ⎡ ⎛ VIN − VOUTx ⎞ ⎤ 2 × COUT × VOUTx × ⎢K ⎜ ⎟ − TOFF(MIN) ⎥ V IN ⎠ ⎣ ⎝ ⎦ Where minimum off-time (TOFF(MIN)) = 300ns (typ.) and K is from Table 1. Output Capacitor Selection The output filter capacitor must have low enough ESR to meet output ripple and load-transient requirements, yet have high enough ESR to satisfy stability requirements. Also, the capacitance value must be high enough to absorb the inductor energy going from a full load to no load condition without tripping the OVP circuit. For CPU core voltage converters and other applications where the output is subject to violent load transients, the output capacitor's size depends on how much ESR is needed to prevent the output from dipping too low under a load transient. Ignoring the sag due to finite capacitance : ESR ≤ VP-P ILOAD(MAX) In non-CPU applications, the output capacitor's size depends on how much ESR is needed to maintain an acceptable level of output voltage ripple : VP-P ESR ≤ LIR × ILOAD(MAX) where VP-P is the peak to peak output voltage ripple. Organic semiconductor capacitor(s) or specialty polymer capacitor(s) are recommended. For low input to output voltage differentials (VIN / VOUTx < 2), additional output capacitance is required to maintain stability and good efficiency in ultrasonic mode. The amount of overshoot due to stored inductor energy can be calculated as : VSOAR ≤ (IPEAK )2 × L 2 × COUT × VOUTx where IPEAK is the peak inductor current. DS8223A/B-04 April 2011 Output Capacitor Stability Stability is determined by the value of the ESR zero relative to the switching frequency. The point of instability is given by the following equation : fESR = f 1 ≤ SW 2 × π × ESR × COUT 4 Do not put high-value ceramic capacitors directly across the outputs without taking precautions to ensure stability. Large ceramic capacitors can have a high- ESR zero frequency and cause erratic, unstable operation. However, it is easy to add enough series resistance by placing the capacitors a couple of inches downstream from the inductor and connecting VOUTx or the FBx divider close to the inductor. Unstable operation manifests itself in two related and distinctly different ways: double pulsing and feedback loop instability. Double pulsing occurs due to noise on the output or because the ESR is so low that there is not enough voltage ramp in the output voltage signal. This “fools” the error comparator into triggering a new cycle immediately after the 300ns minimum off-time period has expired. Double pulsing is more annoying than harmful, resulting in nothing worse than increased output ripple. However, it may indicate the possible presence of loop instability, which is caused by insufficient ESR. Loop instability can result in oscillations at the output after line or load perturbations that can trip the overvoltage protection latch or cause the output voltage to fall below the tolerance limit. The easiest method for checking stability is to apply a very fast zero to max load transient and carefully observe the output voltage ripple envelope for overshoot and ringing. It helps to simultaneously monitor the inductor current with an AC current probe. Do not allow more than one cycle of ringing after the initial step response under or overshoot. Thermal Considerations For continuous operation, do not exceed absolute maximum operation junction temperature. The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow www.richtek.com 23 RT8223A/B and temperature difference between junction to ambient. The maximum power dissipation can be calculated by following formula : PD(MAX) = (TJ(MAX) − TA) / θJA Where T J(MAX) is the maximum operation junction temperature, TA is the ambient temperature and the θJA is the junction to ambient thermal resistance. For recommended operating conditions specification of RT8223A/B, the maximum junction temperature is 125°C. The junction to ambient thermal resistance θJA is layout dependent. For WQFN-24L 4x4 package, the thermal resistance θJA is 52°C/W on the standard JEDEC 51-7 four layers thermal test board. The maximum power dissipation at TA = 25°C can be calculated by following formula : PD(MAX) = (125°C − 25°C) / (52°C/W) = 1.923W for WQFN-24L 4x4 package The maximum power dissipation depends on operating ambient temperature for fixed T J(MAX) and thermal resistance θJA. For RT8223A/B package, the Figure 5 of derating curves allows the designer to see the effect of rising ambient temperature on the maximum power dissipation allowed. Maximum Power Dissipation (W) 2.0 Four Layers PCB 1.8 1.6 1.4 WQFN-24L 4x4 1.2 Layout Considerations Layout is very important in high frequency switching converter design. If the IC is designed improperly, the PCB could radiate excessive noise and contribute to the converter instability. Certain points must be considered before starting a layout using the RT8223A/B. ` Place the filter capacitor close to the IC, within 12 mm (0.5 inch) if possible. ` Keep current limit setting network as close as possible to the IC. Routing of the network should avoid coupling to high voltage switching node. ` Connections from the drivers to the respective gate of the high side or the low side MOSFET should be as short as possible to reduce stray inductance. Use 0.65mm (25 mils) or wider trace. ` All sensitive analog traces and components such as VOUTx, FBx, GND, ENTRIPx, PGOOD, and TONSEL should be placed away from high voltage switching nodes such as PHASEx, LGATEx, UGATEx, or BOOTx nodes to avoid coupling. Use internal layer(s) as ground plane(s) and shield the feedback trace from power traces and components. ` Gather ground terminal of VIN capacitor(s), VOUTx capacitor(s), and source of low side MOSFETs as close as possible. PCB trace defined as PHASEx node, which connects to source of high side MOSFET, drain of low side MOSFET and high voltage side of the inductor, should be as short and wide as possible. 1.0 0.8 0.6 0.4 0.2 0.0 0 25 50 75 100 125 Ambient Temperature (°C) Figure 5. Derating Curve for RT8223A/B Package www.richtek.com 24 DS8223A/B-04 April 2011 RT8223A/B Table 2. Operation Mode Truth Table Mode Test Condition Comment Transitions to discharge mode after a VIN POR and after REF becomes valid. VREG5, VREG3, and REF remain active. Power-UP VREGx < UVLO threshold RUN Over Voltage Protection Under Voltage Protection EN = high, VOUT1 or VOUT2 enabled Normal Operation. Either output > 111% of the nominal level. LGATEx is forced high. VREG3, VREG5 active. Exited by VIN POR or by toggling EN, ENTRIPx Either output < 70% of the nominal level after 3ms time-out expires and output is enabled Either SMPS output is still high in Discharge either standby mode or shutdown mode ENC < startup threshold, Standby EN = high. Shutdown EN = low Thermal TJ > +150°C Shutdown Both UGATEx and LGAT Ex are forced low and enter discharge mode. VREG3, VREG5 active. Exited by VIN POR or by toggling EN, ENTRIPx, ENC During discharge mode, there is one path to discharge the outputs capacitor residual charge. That is output capacitor discharge to GND through an internal switch. VREG3, VREG5 active. All circuitry off. All circuitry off. Exit by VIN POR or by toggling EN, ENTRIPx, ENC Table 3. Power Up Sequencing EN (V) ENC (V) ENTRIP1 (V) ENTRIP2 (V) Low Low X X “>1V” => High Low X X “>1V” => “>2V” High => High Low Low “>1V” => “>2V” High => High Low High “>1V” => “>2V” High => High High (after ENTRIP2 is high without 60μs) High “>1V” => “>2V” High => High High Low “>1V” => “>2V” High => High High High (after ENTRIP1 is high without 60μs) “>1V” => “>2V” High => High High High DS8223A/B-04 April 2011 VREG5 VREG3 SMPS1 SMPS2 Off On (after REF powers up) On (after REF powers up) On (after REF powers up) On (after REF powers up) On (after REF powers up) On (after REF powers up) On (after REF powers up) Off On (after REF powers up) On (after REF powers up) On (after REF powers up) On (after REF powers up) On (after REF powers up) On (after REF powers up) On (after REF powers up) Off Off Off Off Off Off Off On On (after SMPS2 on) On On Off ON On (after SMPS1 on) On On www.richtek.com 25 RT8223A/B Outline Dimension D2 D SEE DETAIL A L 1 E E2 e b 1 1 2 2 DETAIL A Pin #1 ID and Tie Bar Mark Options A A3 A1 Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 D 3.950 4.050 0.156 0.159 D2 2.300 2.750 0.091 0.108 E 3.950 4.050 0.156 0.159 E2 2.300 2.750 0.091 0.108 e L 0.500 0.350 0.020 0.450 0.014 0.018 W-Type 24L QFN 4x4 Package Richtek Technology Corporation Richtek Technology Corporation Headquarter Taipei Office (Marketing) 5F, No. 20, Taiyuen Street, Chupei City 5F, No. 95, Minchiuan Road, Hsintien City Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)86672399 Fax: (8862)86672377 Email: [email protected] Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek. www.richtek.com 26 DS8223A/B-04 April 2011