TRIQUINT TGA4807

TGA4807
10.7Gb/s Modulator Driver Amplifier
Key Features and Performance
•
•
•
•
•
•
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Single-ended Input / Output
Small Signal Gain 19dB
Small Signal Bandwidth 10GHz
Wide Drive Range (3V to 11V)
25ps Edge Rates (20/80)
Power Dissipation 2.25Watts
Die Size: 3.3 x 2 x 0.1 mm
Primary Applications
Description
•
Mach-Zehnder Modulator Driver for
The TriQuint TGA4807 is part of a series of optical driver
amplifiers suitable for a variety of driver applications.
The TGA4807 is a medium power wideband AGC
amplifier MMIC die that typically provides 19dB small
signal gain with 19dB AGC range. RF ports are DC
coupled enabling the user to customize system corner
frequencies.
The TGA4807 is an excellent choice for applications
requiring high drive levels. The TGA4807 has
demonstrated capability to amplify a 2V input signal to
11Vpp saturated.
The TGA4807 requires off-chip decoupling, a DC block
and a bias tee. The TGA4807 is available in die form.
Metro and Long Haul.
Measured Performance
TGA4807 Fixtured Data
Vd(Rfout)=7V, Id=250mA, (Pdc=1.75W)
Vout=11Vpp, Vin = 2Vpp
Scale: 2V/div, 15ps/div
10.7Gb/s
Vin=2V
Lead-free and RoHS compliant
Vout=11Vpp
Datasheet subject to change without notice
1
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TGA4807
MAXIMUM RATINGS
SYMBOL
PARAMETER 6/
VALUE
NOTES
POSITIVE SUPPLY VOLTAGE
Vd
Drain Voltage at RF output
7V
POSITIVE SUPPLY CURRENT
Id
Pd
Drain Current
POWER DISSIPATION
285 mA
1/
2.2 W
2/
NEGATIVE GATE
Vg
Voltage
Ig
Gate Current
0 V to –3 V
5 mA
CONTROL GATE
Vctrl
Ictrl
Vd/2 to –3 V
Voltage
3/
5 mA
Gate Current
RF INPUT
PIN
TCH
Sinusoidal Continuous Wave Power
23 dBm
OPERATING CHANNEL TEMPERATURE
200 °C
MOUNTING TEMPERATURE
320 °C
4/ 5/
(30 SECONDS)
TSTG
STORAGE TEMPERATURE
-65 to 150 °C
Notes:
1/
2/
3/
4/
5/
Assure the combination of Vd and Id does not exceed maximum power dissipation rating.
When operated at this bias condition with a base plate temperature of 70 °C, the median life is 3.4E6 hours.
Assure Vctrl never exceeds Vd during bias on and off sequences, and normal operation.
These ratings apply to each individual FET.
Junction operating temperature will directly affect the device median time to failure (Tm). For maximum
life, it is recommended that junction temperatures be maintained at the lowest possible levels.
6/ These ratings represent the maximum operable values for the device.
2
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TGA4807
THERMAL INFORMATION
Parameter
Test Condition
θJC Thermal Resistance
(channel to backside of
carrier)
VD(RFout)=7V
Id=250mA
Pdiss
(W)
TBase
(°C)
TCH
(°C)
θJC
(°C/W)
Tm
(HRS)
1.75
70
122
30
1.2E7
Notes:
1. Assumes worst case power dissipation condition where no RF is applied at the input (no
power is dissipated in the load).
2. Thermal transfer is conducted thru the bottom of the TGA4807 into the mounting carrier. Design the
mounting interface to assure adequate thermal transfer to the base plate.
Median Lifetime (Tm) vs. Channel Temperature
1.E+13
Median Lifetime (Hours)
1.E+12
1.E+11
1.E+10
1.E+09
1.E+08
1.E+07
1.E+06
1.E+05
1.E+04
FET3
25
50
75
100
125
150
175
200
Channel Temperature ( °C)
3
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TGA4807
DC PROBE TEST
(TA = 25 °C, nominal)
NOTES
SYMBOL
UNITS
LIMITS
MIN
1/, 2/
|VBVGS|
13
1/, 2/
|VBVGD|
13
MAX
V
V
Notes:
1/ Verified at die level on-wafer probe.
2/ VBVGS and VBVDS are negative.
Definitions:
VBVGS: Breakdown voltage, Gate to Source
VBVGD: Breakdown voltage, Gate to Drain
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TGA4807
RF SPECIFICATIONS
(TA = 25°C Nominal)
NOTE
TEST
MEASUREMENT
CONDITIONS
VALUE
MIN
SMALL SIGNAL BW
1/, 2/
SMALL-SIGNAL
GAIN MAGNITUDE
TYP
UNITS
MAX
10
2 GHz
18
4 GHz
17
6 GHz
16
10 GHz
15
14 GHz
12
GHz
dB
1/, 2/
SMALL SIGNAL AGC RANGE
2, 4, 6, 10, and
14GHz
20
dB
1/, 2/
INPUT RETURN LOSS
MAGNITUDE
2, 4, 6, 10, and
14GHz
10
dB
1/, 2/
OUTPUT RETURN LOSS
MAGNITUDE
2, 4, 6, 10, and
14GHz
12
dB
3/, 4/
SATURATED OUTPUT
POWER
2, 4, 6, 10, and
14GHz
25
dBm
3/, 4/
EYE AMPLITUDE
Vd(Rfout) = 7V
11.0
Vpp
Vd(Rfout) = 6V
10.0
Vd(Rfout) = 5V
9.0
Vd(Rfout) = 4V
8.0
3/, 5/
3/
ADDITIVE JITTER
5
ps
RISE TIME
25
ps
Notes:
1/ Verified at package level RF probe.
2/ Bias: V+ = 7 V, adjust Vg1 to achieve Id = 250 mA, Vctrl = +1 V
3/ Verified by design, TGA4807 assembled onto a demonstration board shown on page 9 then tested
using the application circuit and bias procedure detailed on pages 7 and 8.
4/ Vin = 2 V, Data Rate = 12.5 Gb/s, Vctrl and Vg are adjusted for maximum output.
5/ Computed using RSS Method where Jpp_additive = SQRT(Jpp_out2 - Jpp_in2)
5
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TGA4807
Typical Small Signal S-Parameters
6
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TGA4807
TGA4807 Application Circuit
V+ (No Connection)
C4
C5
VDT
VCTRL
4
6
VD(RFout)
C6
TGA4807
RF(in)
Bias Tee
13
(PSPL 5545)
RF(out)
2
19
DC Block
(PSPL 5509)
VG
C1
C2
C3
Notes:
Recommended Components are detailed on page 9.
7
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TGA4807
Bias Procedure for 11V Output
Bias ON
Bias OFF
1. Disable the RF source (PPG)
1. Disable the output of the PPG
2. Set VdT=0V Vctrl=0V and Vg=0V
2. Set Vctrl=0V
3. Set Vg=-1.5V
3. Set VdT=0V
4. Increase VdT to 8V observing Id.
4. Set Vg=0V
- Assure Id=0mA
5. Set Vctrl=+1.2V
- Id should still be 0mA
6. Make Vg more positive until Idd=250mA.
- Typical value for Vg is -0.2V
7. Measure V+, adjust VdT such that V+ is 7V.
- This will set Vd(RFout) to approximately 7V.
- Idd will increase slightly
8. Adjust Vg such that Idd=250mA.
9. Enable the RF source (PPG)
- Set Vin=2V
10. Output Swing Adjust: Adjust Vctrl slightly positive to increase output swing or
adjust Vctrl slightly negative to decrease the output swing.
- Typical value for Vctrl is +1.2V for Vo=11V.
11. Crossover Adjust: Adjust: Vg slightly positive to push the crossover down or adjust
Vg slightly negative to push the crossover up.
- Typical value for Vg is -0.57V to center crossover with Vo=11V.
Notes:
1. Assure Vctrl never exceeds Vd during Bias ON and Bias OFF sequences and
during normal operation.
8
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TGA4807
Recommended Assembly Diagram
V+
C5
VCTRL
C4
C6
RF(out)
and
Vd(RFout)
RF(in)
C1
VG
C3
C2
Recommended Components:
DESIGNATOR
DESCRIPTION
MANUFACTURER
PART NUMBER
C1, C4
1500pF Capacitor SLC
Presidio
SL5050X7R1522H5
C2, C5
0.1uF Capacitor MLC Ceramic
AVX
0603YC104KAT
C3
10uF Capacitor MLC Ceramic
AVX
0603YC102KAT
C6
0.01 uF Capacitor MLC
AVX
0603YC103KAT
GaAs MMIC devices are susceptible to damage from Electrostatic Discharge. Proper precautions should
be observed during handling, assembly and test.
9
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May 2009 © Rev -
TGA4807
TGA4807 Detector Application Circuit
VREF
5-8V
VDET
C8
R1
R2
C7
C9
8
4
10
11
6
TGA4807
RF(in)
9
C10
13
RF(out)
2
19
Recommended Components:
DESIGNATOR
DESCRIPTION
MANUFACTURER
PART NUMBER
R1, R2
40K ohm Resistor Chip Silicon
MSI
MSBC 2ST-40001F-E
C7, C8, C9
100pF Capacitor SLC Ceramic
AVX
GB015810KA6
C10
.01uF Capacitor MLC Ceramic
AVX
VL303X7R103M16VG5
10
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May 2009 © Rev -
TGA4807
Assembly Process Notes
Assembly Notes:
Reflow Attachment:
Use AuSn (80/20) solder with limited exposure to temperatures at or above 300C
Use alloy station or conveyor furnace with reducing atmosphere
No fluxes should be utilized
Coefficient of thermal expansion matching is critical for long-term reliability
Storage in dry nitrogen atmosphere
Adhesive Attachment:
Organic attachment can be used in low-power applications
Curing should be done in a convection oven; proper exhaust is a safety concern
Microwave or radiant curing should not be used because of differential heating
Coefficient of thermal expansion matching is critical
Component Pickup and Placement:
Vacuum pencil and/or vacuum collet preferred method of pick up
Avoidance of air bridges during placement
Force impact critical during auto placement
Interconnect:
Thermosonic ball bonding is the preferred interconnect technique
Force, time, and ultrasonics are critical parameters
Aluminum wire should not be used
Discrete FET devices with small pad sizes should be bonded with 0.0007-inch wire
Maximum stage temperature: 200C
11
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May 2009 © Rev -
TGA4807
TGA4807 Mechanical Drawing
2.932 (0.115)
3.159 (0.124)
6
7
8
5
4
3.181 (0.125)
2.686 (0.106)
3
2.475 (0.097)
0.767 (0.030)
0.381 (0.015)
2.000 (0.079)
1.868 (0.074)
1.870 (0.074)
1.343 (0.053)
9
0.934 (0.037)
0.437 (0.017)
2
10
0.928 (0.037)
1
0.174 (0.007)
12 11
0.000 (0.000)
3.335 (0.131)
3.206 (0.126)
2.832 (0.111)
3.014 (0.119)
0.154 (0.006)
0.130 (0.005)
0.000 (0.000)
Units: millimeters (inches)
Thickness: 0.100 (0.004)
Chip edge to bond pad dimensions are shown to center of bond pad
Chip size tolerance: +/- 0.051 (0.002)
RF GND IS BACKSIDE OF MMIC
Bond
Bond
Bond
Bond
Bond
Bond
Bond
Bond
Bond
Bond
Bond
Bond
pad
pad
pad
pad
pad
pad
pad
pad
pad
pad
pad
pad
#1
#2
#3
#4
#5
#6
#7
#8
#9
#10
#11
#12
(RF In)
(Vctrl)
(V+)
(V+ aux)
(Vref)
(A)
(B)
(V det)
(RF Out)
(Vctrl aux)
(Vg aux)
(Vg)
0.155
0.106
0.368
0.368
0.095
0.095
0.095
0.095
0.155
0.106
0.155
0.155
x
x
x
x
x
x
x
x
x
x
x
x
0.155
0.157
0.109
0.109
0.095
0.095
0.095
0.095
0.155
0.157
0.155
0.155
(0.006
(0.004
(0.014
(0.014
(0.004
(0.004
(0.004
(0.004
(0.006
(0.004
(0.006
(0.006
x
x
x
x
x
x
x
x
x
x
x
x
0.006)
0.006)
0.004)
0.004)
0.004)
0.004)
0.004)
0.004)
0.006)
0.006)
0.006)
0.006)
12
TriQuint Semiconductor: www. triquint.com (972)994-8465 Fax (972)994-8504 [email protected]
May 2009 © Rev -