TQP3M9006 High Linearity LNA Gain Block Applications Repeaters Mobile Infrastructure LTE / WCDMA / CDMA / EDGE General Purpose Wireless Product Features 16-pin 3x3 QFN package Functional Block Diagram 500-4000 MHz 13.5 dB Gain @ 1.9 GHz 1.0 dB Noise Figure @ 1.9 GHz +38.5 dBm Output IP3 +22.4 dBm P1dB 50 Ohm Cascadable Gain Block Unconditionally Stable High Input Power Capability +5V Single Supply, 90 mA Current 3x3 mm QFN Package General Description Pin Configuration The TQP3M9006 is a high linearity low noise gain block amplifier in a low-cost surface-mount package. At 1.9 GHz, the amplifier typically provides 13.5 dB gain, +38.5 dBm OIP3, and 1.2 dB Noise Figure while only drawing 90 mA current. The device is housed in a leadfree/green/RoHS-compliant industry-standard 16-pin 3x3mm QFN package. Pin # Symbol 2 11 All Other Pins Backside Paddle RF Input RF Output / Vdd N/C or GND GND The TQP3M9006 has the benefit of having high linearity while also providing very low noise across a broad range of frequencies. This allows the device to be used in both receive and transmit chains for high performance systems. The amplifier is internally matched using a high performance E-pHEMT process and only requires an external RF choke and blocking/bypass capacitors for operation from a single +5V supply. The internal active bias circuit also enables stable operation over bias and temperature variations. The TQP3M9006 covers the 0.5- 4 GHz frequency band and is targeted for wireless infrastructure or other applications requiring high linearity and/or low noise figure. Ordering Information Part No. Description TQP3M9006 TQP3M9006-PCB High Linearity LNA Gain Block 0.5-4 GHz Evaluation Board Standard T/R size = 2500 pieces on a 7” reel. Data Sheet: Rev C 05/26/11 © 2011 TriQuint Semiconductor, Inc. - 1 of 9 - Disclaimer: Subject to change without notice Connecting the Digital World to the Global Network® TQP3M9006 High Linearity LNA Gain Block Specifications Recommended Operating Conditions Absolute Maximum Ratings Parameter Rating Parameter Storage Temperature -55 to 150 oC RF Input Power,CW,50 Ω,T=25ºC + 20 dBm Device Voltage,Vdd +7 V Vdd Tcase Tj (for>106 hours MTTF) Min Typ 3.0 -40 5 Max Units 5.25 +85 190 V o C o C Electrical specifications are measured at specified test conditions. Specifications are not guaranteed over all recommended operating conditions. Operation of this device outside the parameter ranges given above may cause permanent damage. Electrical Specifications Test conditions unless otherwise noted: +25ºC, +5V Vsupply, 50 Ω system. Parameter Conditions Operational Frequency Range Min Typical 500 Test Frequency Max Units 4000 MHz 1900 Gain 12 13.5 MHz 15 dB Input Return Loss 13 dB Output Return Loss 19 dB Output P1dB Output IP3 See Note 1. +35 +22.4 dBm +38.5 dBm Noise Figure 1.0 dB Supply Voltage, Vdd +5 V 68 Current, Idd 90 54.5 Thermal Resistance (jnc to case) θjc 112 mA o C/W Notes: 1. OIP3 is measured with two tones at an output power of 4 dBm / tone separated by 1 MHz. The suppression on the largest IM3 product is used to calculate the OIP3 using 2:1 rule. 2:1 rule gives relative value with respect to fundamental tone. Data Sheet: Rev C 05/26/11 © 2011 TriQuint Semiconductor, Inc. - 2 of 9 - Disclaimer: Subject to change without notice Connecting the Digital World to the Global Network® TQP3M9006 High Linearity LNA Gain Block Device Characterization Data S22 0.8 2. 0 0 2. 4 0. 3. 0 0. De-embedded S-parameter Vcc = 5V 4 25 3. 0 0 4. 0 4. 5.0 5.0 0.2 0.2 10.0 15 10.0 5.0 4.0 3.0 2.0 1.0 0.8 0.6 0.4 0 10.0 5.0 4.0 3.0 2.0 1.0 0.8 0.6 0.4 0 0.2 20 0.2 10.0 -10.0 -10.0 -0 .4 2.0 2.5 3.0 3.5 4.0 Frequency (GHz) -2 -0 .6 Swp Min 0.01GHz -1.0 1.5 S(1,1) -0.8 1.0 -0.8 0.5 -1.0 -0 .6 0.0 . -2 0 .0 .0 .4 -3 -0 5 -3 -4 .0 -5. 0 Gain (dB) 2 -0. .0 2 -0. 10 -4 .0 -5. 0 Gain (dB) Swp Max 6GHz 6 0. 1.0 0.8 6 0. 30 Swp Max 6GHz 1.0 S11 De-embedded Gain S(2,2) Swp Min 0.01GHz S-Parameter Data Vdd = +5 V, Icq = 90 mA, T = +25°C, unmatched 50 ohm system, calibrated to device leads Freq (MHz) 50 100 200 400 800 1000 1200 1500 1900 2000 2200 2500 2600 3000 3500 4000 S11 (dB) S11 (ang) S21 (dB) S21 (ang) S12 (dB) S12 (ang) S22 (dB) S22 (ang) -16.84 -17.401 -17.287 -16.259 -14.058 -13.461 -13.096 -12.757 -12.718 -12.97 -13.043 -13.062 -13.221 -13.475 -14.256 -14.52 -151.32 -164.51 -168.02 -169.15 -173.2 -175.46 -177.29 -177.2 -173.31 -172.34 -169.97 -163.57 -163 -157.55 -162.42 178.56 23.531 23.315 22.903 21.851 19.184 17.931 16.795 15.241 13.397 12.969 12.161 11.043 10.671 9.3978 8.1567 7.1124 168.18 165.29 156.16 138.35 111.93 102.1 93.532 81.983 68.817 65.789 60.064 52.376 49.934 40.398 28.943 16.613 -28.093 -28.064 -27.93 -27.459 -25.857 -24.902 -23.936 -22.616 -21.104 -20.821 -20.183 -19.352 -19.117 -18.141 -17.037 -16.013 6.4819 6.2924 10.039 17.79 30.27 33.496 36.097 37.018 36.304 36.102 34.744 32.905 32.135 28.959 24.266 16.846 -13.835 -14.006 -14.114 -14.288 -15.59 -16.791 -18.092 -19.269 -18.018 -17.678 -16.05 -14.575 -14.005 -12.674 -12.843 -14.488 -175.95 164.09 138.62 101.29 50.117 30.427 9.8602 -24.674 -60.918 -67.922 -77.206 -88.454 -90.198 -99.96 -111.14 -134.94 Data Sheet: Rev C 05/26/11 © 2011 TriQuint Semiconductor, Inc. - 3 of 9 - Disclaimer: Subject to change without notice Connecting the Digital World to the Global Network® TQP3M9006 High Linearity LNA Gain Block Application Circuit Configuration Notes: 1. See PC Board Layout, under Applications Information section, for more information. 2. Components shown on the silkscreen but not on the schematic are not used. 3. B1 (0 Ω jumper) may be replaced with copper trace in the target application layout. Bill of Material: TQP3M9006-PCB Reference Desg. Value U1 Description Manufacturer Part Number High Linearity LNA Gain Block TriQuint TQP3M9006 C2, C6 100 pF Cap, Chip, 0603, 50V, NPO, 5% various C1 0.1 uF Cap, Chip, 0603, 16V, X7R, 10% various L2 47 nH Ind, Chip, 0603, 5% various C3 4.7 uF Cap, Chip, 0603, 6.3V, X5R, 20% various B1 0Ω Res, Chip, 0603, 1/16W, 5% L1, D1, C4 Do Not Place Data Sheet: Rev C 05/26/11 © 2011 TriQuint Semiconductor, Inc. various various - 4 of 9 - Disclaimer: Subject to change without notice Connecting the Digital World to the Global Network® TQP3M9006 High Linearity LNA Gain Block Typical Performance TQP3M9006-PCB Test conditions unless otherwise noted: +25ºC, +5V, 90 mA, 50 Ω system. The data shown below is measured on TQP3M9006-PCB Frequency MHz 500 900 1900 2600 Gain Input Return Loss Output Return Loss Output P1dB OIP3 [1] Noise Figure [2] dB dB dB dBm dBm dB 21.2 13 10 +22.3 +36.8 1.0 18.7 13 14 +22.3 +37.3 1.1 13.5 13 19 +22.4 +38.5 1.0 10.7 14 15 +22.6 +38.9 1.5 Notes: 1. OIP3 measured with two tones at an output power of +4 dBm / tone separated by 1 MHz. The suppression on the largest IM3 product is used to calculate the OIP3 using 2:1 rule. 2. Noise figure data shown in the table above is measured on evaluation board and corrected for the board loss of around 0.13dB @ 1.9 GHz. Performance Plots Performance plots data is measured using TQP3M9006-PCB. Noise figure plot has been corrected for evaluation board loss of around 0.13dB @ 1.9 GHz. Gain vs. Frequency 24 Vcc = 5V Vcc = 5V 22 Input Return Loss (dB) 20 +85°C +25°C −40°C 18 Gain (dB) Input Return Loss vs. Frequency 0 16 14 12 10 -5 +85°C +25°C −40°C -10 -15 -20 8 6 -25 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0.0 0.5 1.0 Frequency (GHz) Output Return Loss vs. Frequency 0 3.0 3.5 4.0 Vcc = 5 V +85°C +25°C −40°C 3.0 NF (dB) Output Return Loss (dB) 2.5 3.5 +85°C +25°C −40°C -10 2.0 Noise Figure vs. Frequency 4.0 Vcc = 5V -5 1.5 Frequency (GHz) -15 2.5 2.0 1.5 1.0 -20 0.5 -25 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Frequency (GHz) Data Sheet: Rev C 05/26/11 © 2011 TriQuint Semiconductor, Inc. 0.5 1.0 1.5 2.0 2.5 3.0 Frequency (GHz) - 5 of 9 - Disclaimer: Subject to change without notice Connecting the Digital World to the Global Network® TQP3M9006 High Linearity LNA Gain Block Performance Plots OIP3 vs. Output Power/Tone 50 Freq. = 900 MHz 1MHz Tone Spacing Vcc = 5V 35 40 35 30 30 0 2 4 6 8 10 12 0 2 Output Power (dBm) 4 6 8 10 12 Output Power/Tone (dBm) OIP3 vs. Output Power/Tone 50 P1dB vs. Temperature 24 Vcc = 5V 1 MHz Tone Spacing Temp. = 25oC Vcc = 5V 45 1900 MHz 900 MHz 23 2600 MHz 500 MHz P1dB (dBm) OIP3 (dBm) +85°C +25°C −30 C −40°C 45 OIP3 (dBm) 40 Vcc = 5V Freq. = 1900 MHz 1 MHz Tone Spacing +85°C +25°C −30 C −40°C 45 OIP3 (dBm) OIP3 vs. Output Power/Tone 50 40 22 21 35 20 30 0 1 2 3 4 5 6 7 Data Sheet: Rev C 05/26/11 © 2011 TriQuint Semiconductor, Inc. -40 -20 0 20 40 60 80 Temperature (°C) Output Power/Tone (dBm) - 6 of 9 - Disclaimer: Subject to change without notice Connecting the Digital World to the Global Network® TQP3M9006 High Linearity LNA Gain Block Pin Description Pin Symbol Description 2 RF Input Input, matched to 50 ohms. External DC Block is required. 11 Vdd / RFout All other pins GND Output, matched to 50 ohms, External DC Block is required and supply voltage. These pins are not connected internally but are recommended to be grounded on the PCB for optimal isolation. Backside Paddle. Multiple vias should be employed to minimize inductance and thermal resistance; see page 7 for mounting configuration. GND Paddle Applications Information PC Board Layout Top RF layer is .014” NELCO N4000-13, єr = 3.9, 4 total layers (0.062” thick) for mechanical rigidity. Metal layers are 1-oz copper. 50 ohm Microstrip line details: width = .029”, spacing = .035” The pad pattern shown has been developed and tested for optimized assembly at TriQuint Semiconductor. The PCB land pattern has been developed to accommodate lead and package tolerances. Since surface mount processes vary from company to company, careful process development is recommended. For further technical information, Refer to www.TriQuint.com Data Sheet: Rev C 05/26/11 © 2011 TriQuint Semiconductor, Inc. - 7 of 9 - Disclaimer: Subject to change without notice Connecting the Digital World to the Global Network® TQP3M9006 High Linearity LNA Gain Block Mechanical Information Package Information and Dimensions This package is lead-free/RoHS-compliant. The plating material on the leads is annealed matte tin. It is compatible with both leadfree (maximum 260 °C reflow temperature) and lead (maximum 245 °C reflow temperature) soldering processes. The component will be marked with a “9006” designator with an alphanumeric lot code on the top surface of package. TriQuint 9006 YYWW aXXXX Mounting Configuration All dimensions are in millimeters (inches). Angles are in degrees. Notes: 1. Ground / thermal vias are critical for the proper performance of this device. Vias should use a .35mm (#80 / .0135”) diameter drill and have a final plated thru diameter of .25 mm (.010”). 2. Add as much copper as possible to inner and outer layers near the part to ensure optimal thermal performance. Data Sheet: Rev C 05/26/11 © 2011 TriQuint Semiconductor, Inc. - 8 of 9 - Disclaimer: Subject to change without notice Connecting the Digital World to the Global Network® TQP3M9006 High Linearity LNA Gain Block Product Compliance Information ESD Information Solderability Compatible with the latest version of J-STD-020, Lead free solder, 260° ESD Rating: Value: Test: Standard: Class 1A Passes 250 V to < 500 V Human Body Model (HBM) JEDEC Standard JESD22-A114 ESD Rating: Value: Test: Standard: Class IV Passes 1000 V Charged Device Model (CDM) JEDEC Standard JESD22-C101 This part is compliant with EU 2002/95/EC RoHS directive (Restrictions on the Use of Certain Hazardous Substances in Electrical and Electronic Equipment). This product also has the following attributes: Lead Free Halogen Free (Chlorine, Bromine) Antimony Free TBBP-A (C15H12Br402) Free PFOS Free SVHC Free MSL Rating MSL 1 at +260 °C convection reflow The part is rated Moisture Sensitivity Level 1 at 260°C per JEDEC standard IPC/JEDEC J-STD-020. Contact Information For the latest specifications, additional product information, worldwide sales and distribution locations, and information about TriQuint: Web: www.triquint.com Email: [email protected] Tel: Fax: +1.503.615.9000 +1.503.615.8902 For technical questions and application information: Email: [email protected] Important Notice The information contained herein is believed to be reliable. TriQuint makes no warranties regarding the information contained herein. TriQuint assumes no responsibility or liability whatsoever for any of the information contained herein. TriQuint assumes no responsibility or liability whatsoever for the use of the information contained herein. The information contained herein is provided "AS IS, WHERE IS" and with all faults, and the entire risk associated with such information is entirely with the user. All information contained herein is subject to change without notice. Customers should obtain and verify the latest relevant information before placing orders for TriQuint products. The information contained herein or any use of such information does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other intellectual property rights, whether with regard to such information itself or anything described by such information. TriQuint products are not warranted or authorized for use as critical components in medical, life-saving, or life-sustaining applications, or other applications where a failure would reasonably be expected to cause severe personal injury or death. Data Sheet: Rev C 05/26/11 © 2011 TriQuint Semiconductor, Inc. - 9 of 9 - Disclaimer: Subject to change without notice Connecting the Digital World to the Global Network®