SMD Type Product specification NDS355N General Description Features These N-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications in notebook computers, portable phones, PCMICA cards, and other battery powered circuits where fast switching, and low in-line power loss are needed in a very small outline surface mount package. 1.6A, 30V. RDS(ON) = 0.125Ω @ VGS = 4.5V. Proprietary package design using copper lead frame for superior thermal and electrical capabilities. High density cell design for extremely low RDS(ON). Exceptional on-resistance and maximum DC current capability. Compact industry standard SOT-23 surface mount package. _______________________________________________________________________________ D S G Absolute Maximum Ratings T A = 25°C unless otherwise noted Symbol Parameter NDS355N Units VDSS Drain-Source Voltage 30 V VGSS Gate-Source Voltage - Continuous 20 V ID Drain Current - Continuous ± 1.6 A (Note 1a) - Pulsed PD ± 10 Maximum Power Dissipation (Note 1a) (Note 1b) TJ,TSTG 0.5 W 0.46 Operating and Storage Temperature Range -55 to 150 °C THERMAL CHARACTERISTICS RθJA Thermal Resistance, Junction-to-Ambient (Note 1a) 250 °C/W RθJC Thermal Resistance, Junction-to -Case (Note 1) 75 °C/W http://www.twtysemi.com [email protected] 4008-318-123 1 of 3 SMD Type Product specification NDS355N Electrical Characteristics (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units 1 µA OFF CHARACTERISTICS BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA IDSS Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V 30 V 10 µA IGSSF Gate - Body Leakage, Forward VGS = 12 V, VDS = 0 V 100 nA IGSSR Gate - Body Leakage, Reverse VGS = -12 V, VDS= 0 V -100 nA V TJ=125°C ON CHARACTERISTICS (Note 2) VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA TJ=125°C RDS(ON) Static Drain-Source On-Resistance 1 1.6 2 0.5 1.3 1.5 0.125 VGS = 4.5 V, ID = 1.6 A TJ=125°C Ω 0.25 0.085 VGS = 10 V, ID = 1.9 A ID(ON) On-State Drain Current VGS = 4.5 V, VDS = 5 V 6 A gFS Forward Transconductance VDS = 5 V, ID = 1.6 A 3.5 S VDS = 10 V, VGS = 0 V, f = 1.0 MHz 245 pF 130 pF 20 pF DYNAMIC CHARACTERISTICS Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance SWITCHING CHARACTERISTICS tD(on) Turn - On Delay Time tr Turn - On Rise Time tD(off) Turn - Off Delay Time tf Turn - Off Fall Time Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge http://www.twtysemi.com (Note 2) VDD = 10 V, ID = 1 A, VGS = 10 V, RGEN = 6 Ω VDS = 10 V, ID = 1.6 A, VGS = 5 V [email protected] 15 30 ns 14 30 ns 12 25 ns 4 10 ns 3.5 5 nC 1 nC 2 nC 4008-318-123 2 of 3 SMD Type Product specification NDS355N Electrical Characteristics (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS IS Maximum Continuous Source Current 0.6 A ISM Maximum Pulse Source Current (Note 2) 6 A VSD Drain-Source Diode Forward Voltage 1.2 V VGS = 0 V, IS = 1.6 A 0.8 Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. PD (t ) = TJ −TA R θJ A(t ) = TJ − TA R θJ C+RθCA(t ) = I 2D (t ) × RDS (ON ) TJ Typical RθJA using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment: a. 250oC/W when mounted on a 0.02 in2 pad of 2oz cpper. b. 270oC/W when mounted on a 0.001 in2 pad of 2oz cpper. 1a 1b Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%. http://www.twtysemi.com [email protected] 4008-318-123 3 of 3