TYSEMI PMV60EN

Product specification
PMV60EN
µTrenchMOS™ enhanced logic level FET
Rev. 01 — 15 January 2003
Product data
1. Product profile
1.1 Description
N-channel enhancement mode field-effect transistor in a plastic package using
TrenchMOS™ technology.
Product availability:
PMV60EN in SOT23.
1.2 Features
■ Surface mount package
■ Fast switching.
1.3 Applications
■ Battery management
■ High speed switch.
1.4 Quick reference data
■ VDS ≤ 30 V
■ Ptot ≤ 2 W
■ ID ≤ 4.7 A
■ RDSon ≤ 55 mΩ
2. Pinning information
Table 1:
Pinning - SOT23 simplified outline and symbol
Pin
Description
1
gate (g)
2
source (s)
3
drain (d)
Simplified outline
Symbol
d
3
g
1
2
Top view
MBB076
s
MSB003
SOT23
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Product specification
PMV60EN
µTrenchMOS™ enhanced logic level FET
3. Limiting values
Table 2:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
Unit
VDS
drain-source voltage (DC)
25 °C ≤ Tj ≤ 150 °C
-
30
V
VDGR
drain-gate voltage (DC)
25 °C ≤ Tj ≤ 150 °C; RGS = 20 kΩ
-
30
V
VGS
gate-source voltage (DC)
ID
drain current (DC)
-
±20
V
Tsp = 25 °C; VGS = 10 V; Figure 2 and 3
-
4.7
A
Tsp = 100 °C; VGS = 10 V; Figure 2
-
2.9
A
-
18.8
A
IDM
peak drain current
Tsp = 25 °C; pulsed; tp ≤ 10 µs; Figure 3
Tsp = 25 °C; Figure 1
Ptot
total power dissipation
-
2
W
Tstg
storage temperature
−55
+150
°C
Tj
junction temperature
−55
+150
°C
Source-drain diode
IS
source (diode forward) current (DC) Tsp = 25 °C
-
1.7
A
ISM
peak source (diode forward) current Tsp = 25 °C; pulsed; tp ≤ 10 µs
-
6.9
A
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Product specification
PMV60EN
µTrenchMOS™ enhanced logic level FET
4. Characteristics
Table 3:
Characteristics
Tj = 25 °C unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tj = 25 °C
30
-
-
V
Tj = −55 °C
27
-
-
V
1
-
2
V
Static characteristics
V(BR)DSS drain-source breakdown voltage
VGS(th)
gate-source threshold voltage
ID = 250 µA; VGS = 0 V
ID = 1 mA; VDS = VGS; Figure 9
Tj = 25 °C
IDSS
drain-source leakage current
Tj = 150°C
0.6
-
-
V
Tj = −55°C
-
-
2.2
V
-
-
1
µA
VDS = 30 V; VGS = 0 V
Tj = 25 °C
Tj = 150 °C
IGSS
gate-source leakage current
VGS = ±20 V; VDS = 0 V
RDSon
drain-source on-state resistance
VGS = 10 V; ID = 2 A; Figure 7 and 8
Tj = 25 °C
Tj = 150 °C
-
-
100
µA
-
10
100
nA
-
47
55
mΩ
-
79.9
93.5
mΩ
VGS = 4.5 V; ID = 1.5 A; Figure 7
-
60
72
mΩ
ID = 3 A; VDD = 15 V; VGS = 10 V; Figure 13
-
9.4
-
nC
Dynamic characteristics
Qg(tot)
total gate charge
Qgs
gate-source charge
-
1.2
-
nC
Qgd
gate-drain (Miller) charge
-
1.9
-
nC
Ciss
input capacitance
-
350
-
pF
Coss
output capacitance
-
70
-
pF
Crss
reverse transfer capacitance
td(on)
turn-on delay time
tr
VGS = 0 V; VDS = 30 V; f = 1 MHz; Figure 11
-
50
-
pF
-
5
-
ns
rise time
-
7
-
ns
td(off)
turn-off delay time
-
16
-
ns
tf
fall time
-
5.5
-
ns
-
0.79
1.2
V
VDD = 15 V; RL = 15 Ω; VGS = 10 V; RG = 6 Ω
Source-drain diode
VSD
source-drain (diode forward) voltage IS = 1.5 A; VGS = 0 V; Figure 12
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