LMP7731 2.9 nV/sqrt(Hz) Low Noise, Precision, RRIO Amplifier General Description Features The LMP7731 is a single, low noise, rail-to-rail input and output, low voltage amplifier. The LMP7731 is part of the LMP® precision amplifier family and is ideal for precision and low noise applications with low voltage requirements. This operational amplifier offers low voltage noise of 2.9 nV/ √Hz with a 1/f corner of only 3 Hz. The LMP7731 has bipolar input stages with a bias current of only 1.5 nA. This low input bias current, complemented by the very low level of voltage noise, makes the LMP7731 an excellent choice for photometry applications. The LMP7731 provides a wide GBW of 22 MHz while consuming only 2 mA of current. This high gain bandwidth along with the high open loop gain of 130 dB enables accurate signal conditioning in applications with high closed loop gain requirements. The LMP7731 has a supply voltage range of 1.8V to 5.5V, making it an ideal choice for battery operated portable applications. The LMP7731 is offered in the space saving 5-Pin SOT-23 and 8-Pin SOIC packages. (Typical values, TA = 25°C, VS = 5V) ■ Input voltage noise — f = 3 Hz — f = 1 kHz ■ CMRR ■ Open loop gain ■ GBW ■ Slew rate ■ THD @ f = 10 kHz, AV = +1, RL = 2 kΩ ■ Supply current per channel ■ Supply voltage range ■ Operating temperature range ■ Input bias current ■ RRIO 3.3 nV/√Hz 2.9 nV/√Hz 130 dB 130 dB 22 MHz 2.4 V/µs 0.001% 2.2 mA 1.8V to 5.5V −40°C to 125°C ±1.5 nA Applications ■ Gas analysis instruments ■ Photometric instrumentation ■ Medical instrumentation Typical Performance Characteristics Input Voltage Noise vs. Frequency Input Current Noise vs. Frequency 20175261 20175262 LMP® is a registered trademark of National Semiconductor Corporation. © 2009 National Semiconductor Corporation 201752 www.national.com LMP7731 2.9 nV/sqrt(Hz) Low Noise, Precision, RRIO Amplifier May 20, 2009 LMP7731 Storage Temperature Range Junction Temperature (Note 3) Soldering Information Infrared or Convection (20 sec) Wave Soldering Lead Temp. (10 sec) Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. ESD Tolerance (Note 2) Human Body Model Inputs pins only All other pins Machine Model Charge Device Model VIN Differential Supply Voltage (VS = V+ – V−) Operating Ratings 2000V 2000V 200V 1000V ±2V 6.0V 2.5V Electrical Characteristics −65°C to 150°C +150°C max 235°C 260°C (Note 1) Temperature Range Supply Voltage (VS = V+ – V–) −40°C to 125°C 1.8V to 5.5V Package Thermal Resistance (θJA) 5-Pin SOT-23 8-Pin SOIC 265°C/W 190°C/W (Note 4) Unless otherwise specified, all limits are guaranteed for TA = 25°C, V+ = 2.5V, V− = 0V, VCM = V+/2, RL >10 kΩ to V+/2. Boldface limits apply at the temperature extremes. Symbol VOS TCVOS IB IOS TCIOS Parameter Input Offset Voltage (Note 7) Input Offset Voltage Temperature Drift Conditions VCM = 2.0V ±9 ±500 ±600 VCM = 0.5V ±9 ±500 ±600 VCM = 2.0V ±0.5 ±5.5 VCM = 0.5V ±0.2 ±5.5 VCM = 2.0V ±1 ±30 ±45 VCM = 0.5V ±12 ±50 ±75 VCM = 2.0V ±1 ±50 ±75 VCM = 0.5V ±11 ±60 ±80 Input Bias Current Input Offset Current Input Offset Current Drift VCM = 0.5V and VCM = 2.0V 0.15V ≤ VCM ≤ 0.7V CMRR Common Mode Rejection Ratio Power Supply Rejection Ratio 0.0474 101 89 120 1.5V ≤ VCM ≤ 2.35V 105 99 129 2.5V ≤ V+ ≤ 5V 111 105 129 0.23V ≤ VCM ≤ 0.7V 1.5V ≤ VCM ≤ 2.27V PSRR Min Typ Max (Note 6) (Note 5) (Note 6) 1.8V ≤ V+ ≤ 5.5V CMVR Common Mode Voltage Range Large Signal CMRR ≥ 80 dB AVOL Open Loop Voltage Gain www.national.com μV/°C nA nA nA/°C dB dB 0 2.5 RL = 10 kΩ to VOUT = 0.5V to 2.0V 130 RL = 2 kΩ to V+/2 VOUT = 0.5V to 2.0V 109 90 119 2 μV 117 112 104 V+/2 Units V dB Parameter Conditions Min Typ Max (Note 6) (Note 5) (Note 6) RL = 10 kΩ to V+/2 4 50 75 RL = 2 kΩ to V+/2 13 50 75 RL = 10 kΩ to V+/2 6 50 75 RL = 2 kΩ to V+/2 9 50 75 Output Voltage Swing High VOUT Output Voltage Swing Low IOUT Output Current IS Supply Current (Per Channel) Sourcing, VOUT = V+/2 VIN (diff) = 100 mV 22 12 31 Sinking, VOUT = V+/2 VIN (diff) = −100 mV 15 10 44 VCM = 2.0V VCM = 0.5V Units mV from either rail mA 2.0 2.7 3.4 2.3 3.1 3.9 mA SR Slew Rate AV = +1, CL = 10 pF, RL = 10 kΩ to V+/2, VO = 2 VPP 2.4 V/μs GBW Gain Bandwidth CL = 20 pF, RL = 10 kΩ to V+/2 21 MHz GM Gain Margin CL = 20 pF, RL = 10 kΩ to V+/2 14 dB ΦM Phase Margin CL = 20 pF, RL = 10 kΩ to V+/2 60 deg RIN Input Resistance THD+N Total Harmonic Distortion + Noise Input Referred Voltage Noise Density en Input Voltage Noise in Input Referred Current Noise Density Differential Mode 38 kΩ Common Mode 151 MΩ 0.002 % AV = 1, f = 1 kHz, Amplitude = 1V f = 1 kHz, VCM = 2.0V 3 f = 1 kHz, VCM = 0.5V 3 0.1 Hz to 10 Hz 75 f = 1 kHz, VCM = 2.0V 1.1 f = 1 kHz, VCM = 0.5V 2.3 3.3V Electrical Characteristics nV/ nVPP pA/ (Note 4) Unless otherwise specified, all limits are guaranteed for TA = 25°C, V+ = 3.3V, V− = 0V, VCM = V+/2, RL > 10 kΩ to V+/2. Boldface limits apply at the temperature extremes. Symbol VOS TCVOS IB IOS Parameter Input Offset Voltage (Note 7) Input Offset Voltage Temperature Drift Conditions Min Typ Max (Note 6) (Note 5) (Note 6) VCM = 2.5V ±6 ±500 ±600 VCM = 0.5V ±6 ±500 ±600 VCM = 2.5V ±0.5 ±5.5 VCM = 0.5V ±0.2 ±5.5 VCM = 2.5V ±1.5 ±30 ±45 VCM = 0.5V ±13 ±50 ±77 VCM = 2.5V ±1 ±50 ±70 ±11 ±60 ±80 Input Bias Current Input Offset Current VCM = 0.5V 3 Units μV μV/°C nA nA www.national.com LMP7731 Symbol LMP7731 Symbol TCIOS CMRR Parameter Input Offset Current Drift Common Mode Rejection Ratio Conditions Power Supply Rejection Ratio Units 0.048 nA/°C VCM = 0.5V and VCM = 2.5V 0.15V ≤ VCM ≤ 0.7V 101 89 120 1.5V ≤ VCM ≤ 3.15V 105 99 130 2.5V ≤ V+ ≤ 5.0V 111 105 129 0.23V ≤ VCM ≤ 0.7V 1.5V ≤ VCM ≤ 3.07V PSRR Min Typ Max (Note 6) (Note 5) (Note 6) 1.8V ≤ V+ ≤ 5.5V CMVR Common Mode Voltage Range Open Loop Voltage Gain dB 117 Large Signal CMRR ≥ 80 dB 0 3.3 RL = 10 kΩ to VOUT = 0.5V to 2.8V 112 104 130 RL = 2 kΩ to V+/2 VOUT = 0.5V to 2.8V 110 92 119 V+/2 AVOL 5 50 75 RL = 2 kΩ to V+/2 14 50 75 RL = 10 kΩ to V+/2 9 50 75 RL = 2 kΩ to V+/2 13 50 75 VOUT Output Voltage Swing Low Output Current IS Supply Current (Per Channel) Sourcing, VOUT = V+/2 VIN (diff) = 100 mV 28 22 45 Sinking, VOUT = V+/2 VIN (diff) = -100 mV 25 20 48 V dB RL = 10 kΩ to V+/2 Output Voltage Swing High IOUT dB mV from either rail mA VCM = 2.5V 2.1 2.8 3.5 VCM = 0.5V 2.4 3.2 4.0 mA SR Slew Rate AV = +1, CL = 10 pF, RL = 10 kΩ to V+/2, VOUT = 2 VPP 2.4 V/μs GBW Gain Bandwidth CL = 20 pF, RL = 10 kΩ to V+/2 22 MHz GM Gain Margin CL = 20 pF, RL = 10 kΩ to V+/2 14 dB ΦM Phase Margin V+/2 62 deg 38 kΩ 151 MΩ 0.002 % RIN Input Resistance THD+N Total Harmonic Distortion + Noise en Input Referred Voltage Noise Density Input Voltage Noise in Input Referred Current Noise Density www.national.com CL = 20 pF, RL = 10 kΩ to Differential Mode Common Mode AV = 1, f = 1 kHz, Amplitude = 1V, f = 1 kHz, VCM = 2.5V 2.9 f = 1 kHz, VCM = 0.5V 2.9 0.1 Hz to 10 Hz 65 f = 1 kHz, VCM = 2.5V 1.1 f = 1 kHz, VCM = 0.5V 2.1 4 nV/ nVPP pA/ (Note 4) Unless otherwise specified, all limits are guaranteed for TA = 25°C, V+ = 5V, V− = 0V, VCM = V+/2, RL > 10 kΩ to V+/2. Boldface limits apply at the temperature extremes. Symbol VOS TCVOS IB IOS TCIOS Parameter Input Offset Voltage (Note 7) Input Offset Voltage Temperature Drift Conditions VCM = 4.5V ±6 ±500 ±600 VCM = 0.5V ±6 ±500 ±600 VCM = 4.5V ±0.5 ±5.5 VCM = 0.5V ±0.2 ±5.5 VCM = 4.5V ±1.5 ±30 ±50 VCM = 0.5V ±14 ±50 ±85 VCM = 4.5V ±1 ±50 ±70 VCM = 0.5V ±11 ±65 ±80 Input Bias Current Input Offset Current Input Offset Current Drift VCM = 0.5V and VCM = 4.5V 0.15V ≤ VCM ≤ 0.7V CMRR Common Mode Rejection Ratio Power Supply Rejection Ratio 0.0482 101 89 120 1.5V ≤ VCM ≤ 4.85V 105 99 130 2.5V ≤ V+ ≤ 5V 111 105 129 0.23V ≤ VCM ≤ 0.7V 1.5V ≤ VCM ≤ 4.77V PSRR Min Typ Max (Note 6) (Note 5) (Note 6) 1.8V ≤ V+ ≤ 5.5V CMVR Common Mode Voltage Range Large Signal CMRR ≥ 80 dB AVOL Open Loop Voltage Gain 0 112 104 130 RL = 2 kΩ to V+/2 VOUT = 0.5V to 4.5V 110 94 119 IS V dB 8 50 75 RL = 2 kΩ to V+/2 24 50 75 RL = 10 kΩ to V+/2 9 50 75 RL = 2 kΩ to V+/2 23 50 75 Sourcing, VOUT = V+/2 VIN (diff) = 100 mV 33 27 47 Sinking, VOUT = V+/2 VIN (diff) = -100 mV 30 25 49 mV from either rail mA 2.2 3.0 3.7 VCM = 0.5V 2.5 3.4 4.2 VCM = 4.5V nA dB RL = 10 kΩ to V+/2 Output Voltage Swing Low Supply Current (Per Channel) nA nA/°C 5 VOUT Output Current μV/°C dB Output Voltage Swing High IOUT μV 117 RL = 10 kΩ to VOUT = 0.5V to 4.5V V+/2 Units mA SR Slew Rate AV = +1, CL = 10 pF, RL = 10 kΩ to V+/2, VOUT = 2 VPP 2.4 V/μs GBW Gain Bandwidth CL = 20 pF, RL = 10 kΩ to V+/2 22 MHz 5 www.national.com LMP7731 5V Electrical Characteristics LMP7731 Symbol Parameter Min Typ Max (Note 6) (Note 5) (Note 6) Conditions Units GM Gain Margin CL = 20 pF, RL = 10 kΩ to V+/2 12 dB ΦM Phase Margin CL = 20 pF, RL = 10 kΩ to V+/2 65 deg RIN Input Resistance Differential Mode 38 kΩ 151 MΩ THD+N Total Harmonic Distortion + Noise 0.001 % en Common Mode AV = 1, f = 1 kHz, Amplitude = 1V Input Referred Voltage Noise Density Input Voltage Noise in Input Referred Current Noise Density f = 1 kHz, VCM = 4.5V 2.9 f = 1 kHz, VCM = 0.5V 2.9 0.1 Hz to 10 Hz 78 f = 1 kHz, VCM = 4.5V 1.1 f = 1 kHz, VCM = 0.5V 2.2 nV/ nVPP pA/ Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics Tables. Note 2: Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC) Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC). Note 3: The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board. Note 4: Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Absolute maximum Ratings indicate junction temperature limits beyond which the device maybe permanently degraded, either mechanically or electrically. Note 5: Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not guaranteed on shipped production material. Note 6: All limits are guaranteed by testing, statistical analysis or design. Note 7: Ambient production test is performed at 25°C with a variance of ±3°C. Connection Diagrams 5-Pin SOT-23 8-Pin SOIC 20175202 Top View 20175203 Top View Ordering Information Package Part Number Package Marking LMP7731MF 5-Pin SOT-23 LMP7731MFE AY3A 250 Units Tape an Reel LMP7731MFX 8-Pin SOIC www.national.com LMP7731MA LMP7731MAX Transport Media NSC Drawing 1k Units Tape and Reel MF05A 3k Units Tape and Reel 95 Units/Rail LMP7731MA 2.5k Tape and Reel 6 M08A Unless otherwise noted: TA = 25°C, RL > 10 kΩ, VCM = VS/2. Offset Voltage Distribution TCVOS Distribution 20175238 20175234 Offset Voltage Distribution TCVOS Distribution 20175236 20175239 Offset Voltage Distribution TCVOS Distribution 20175240 20175235 7 www.national.com LMP7731 Typical Performance Characteristics LMP7731 Offset Voltage Distribution TCVOS Distribution 20175241 20175237 Offset Voltage vs. Temperature Offset Voltage vs. Temperature 20175251 20175252 PSRR vs. Frequency CMRR vs. Frequency 20175256 20175229 www.national.com 8 LMP7731 Offset Voltage vs. Supply Voltage Offset Voltage vs. VCM 20175242 20175243 Offset Voltage vs. VCM Offset Voltage vs. VCM 20175245 20175244 Input Offset Voltage Time Drift Slew Rate vs. Supply Voltage 20175220 20175230 9 www.national.com LMP7731 Time Domain Voltage Noise Time Domain Voltage Noise 20175267 20175269 Time Domain Voltage Noise Output Voltage vs. Output Current 20175268 20175259 Input Bias Current vs. VCM Input Bias Current vs. VCM 20175226 20175225 www.national.com 10 Open Loop Frequency Response Over Temperature 20175218 20175227 Open Loop Frequency Response Open Loop Frequency Response 20175228 20175219 THD+N vs. Frequency THD+N vs. Output Voltage 20175257 20175258 11 www.national.com LMP7731 Input Bias Current vs. VCM LMP7731 Large Signal Step Response Small Signal Step Response 20175222 20175221 Large Signal Step Response Small Signal Step Response 20175224 20175223 Supply Current vs. Supply Voltage Output Swing High vs. Supply Voltage 20175246 www.national.com 20175250 12 LMP7731 Output Swing Low vs. Supply Voltage Sinking Current vs, Supply Voltage 20175249 20175247 Sourcing Current vs. Supply Voltage 20175248 13 www.national.com LMP7731 Figure 1 shows that as the common mode voltage gets closer to one of the extreme ends, current I1 significantly increases. This increased current shows as an increase in voltage drop across resistor R1 equal to I1*R1 on IN+ of the amplifier. This voltage contributes to the offset voltage of the amplifier. When common mode voltage is in the mid-range, the transistors are operating in the linear region and I1 is significantly small. The voltage drop due to I1 across R1 can be ignored as it is orders of magnitude smaller than the amplifier's input offset voltage. As the common mode voltage gets closer to one of the rails, the offset voltage generated due to I1 increases and becomes comparable to the amplifiers offset voltage. Application Information LMP7731 The LMP7731 is a single, low noise, rail-to-rail input and output, and low voltage amplifier. The low input voltage noise of only 2.9 nV/√Hz with a 1/f corner at 3 Hz makes the LMP7731 ideal for sensor applications where DC accuracy is of importance. The LMP7731 has a high gain bandwidth of 22 MHz. This wide bandwidth enables use of the amplifier at higher gain settings while retaining usable bandwidth for the application. This is particularly beneficial when system designers need to use sensors with very limited output voltage range as it allows larger gains in one stage which in turn increases the signal to noise ratio. The LMP7731 has proprietary input bias cancellation circuitry on the input stages. This allows the LMP7731 to have only about 1.5 nA bias current with a bipolar input stage. This low input bias current, paired with the inherent lower input voltage noise of bipolar input stages makes the LMP7731 an excellent choice for precision applications. The combination of low input bias current, and low input voltage noise enables the user to achieve unprecedented accuracy and higher signal integrity. National Semiconductor is heavily committed to precision amplifiers and the market segment they serve. Technical support and extensive characterization data are available for sensitive applications or applications with a constrained error budget. The LMP7731 is offered in the space saving 5-Pin SOT-23 and 8-Pin SOIC packages. These small packages are ideal solutions for area constrained PC boards and portable electronics. 20175206 FIGURE 1. Input Bias Current Cancellation INPUT BIAS CURRENT CANCELLATION The LMP7731 has proprietary input bias current cancellation circuitry on their input stages. The LMP7731 has rail-to-rail input. This is achieved by having two input stages in parallel. Figure 1 shows only one of the input stages as the circuitry is symmetrical for both stages. INPUT VOLTAGE NOISE MEASUREMENT The LMP7731 has very low input voltage noise. The peak-topeak input voltage noise of the LMP7731 can be measured using the test circuit shown in Figure 2 20175255 FIGURE 2. 0.1 Hz to 10 Hz Noise Test Circuit The frequency response of this noise test circuit at the 0.1 Hz corner is defined by only one zero. The test time for the 0.1 Hz to 10 Hz noise measurement using this configuration should not exceed 10 seconds, as this time limit acts as an www.national.com additional zero to reduce or eliminate the noise contributions of noise from frequencies below 0.1 Hz. Figure 3 shows typical peak-to-peak noise for the LMP7731 measured with the circuit in Figure 2 for the LMP7731. 14 DIODES BETWEEN THE INPUTS The LMP7731 has a set of anti-parallel diodes between the input pins as shown in Figure 5. These diodes are present to protect the input stage of the amplifier. At the same time, they limit the amount of differential input voltage that is allowed on the input pins. A differential signal larger than the voltage needed to turn on the diodes might cause damage to the diodes. The differential voltage between the input pins should be limited to ±3 diode drops or the input current needs to be limited to ±20 mA. 20175268 FIGURE 3. 0.1 Hz to 10 Hz Input Voltage Noise Measuring the very low peak-to-peak noise performance of the LMP7731, requires special testing attention. In order to achieve accurate results, the device should be warmed up for at least five minutes. This is so that the input offset voltage of the op amp settles to a value. During this warm up period, the offset can typically change by a few µV because the chip temperature increases by about 30°C. If the 10 seconds of the measurement is selected to include this warm up time, some of this temperature change might show up as the measured noise. Figure 4 shows the start-up drift of five typical LMP7731 units. 20175204 FIGURE 5. Anti-Parallel Diodes between Inputs 20175230 FIGURE 4. Start-Up Input Offset Voltage Drift 15 www.national.com LMP7731 During the peak-to-peak noise measurement, the LMP7731 must be shielded. This prevents offset variations due to airflow. Offset can vary by a few nV due to this airflow and that can invalidate measurements of input voltage noise with a magnitude which is in the same range. For similar reasons, sudden motions must also be restricted in the vicinity of the test area. The feed-through which results from this motion could increase the observed noise value which in turn would invalidate the measurement. LMP7731 DRIVING AN ADC Analog to Digital Converters, ADCs, usually have a sampling capacitor on their input. When the ADC's input is directly connected to the output of the amplifier a charging current flows from the amplifier to the ADC. This charging current causes a momentary glitch that can take some time to settle. There are different ways to minimize this effect. One way is to slow down the sampling rate. This method gives the amplifier sufficient time to stabilize its output. Another way to minimize the glitch caused by the switch capacitor is to have an external capacitor connected to the input of the ADC. This capacitor is chosen so that its value is much larger than the internal switching capacitor and it will hence provide the voltage needed to quickly and smoothly charge the ADC's sampling capacitor. Since this large capacitor will be loading the output of the amplifier as well, an isolation resistor is needed between the output of the amplifier and this capacitor. The isolation resistor, RISO, separates the additional load capacitance from the output of the amplifier and will also form a low-pass filter and can be designed to provide noise reduction as well as anti-aliasing. The drawback to having RISO is that it reduces signal swing since there is some voltage drop across it. Figure 6 (a) shows the ADC directly connected to the amplifier. To minimize the glitch in this setting, a slower sample rate needs to be used. Figure 6 (b) shows RISO and an external capacitor used to minimize the glitch. www.national.com 20175205 FIGURE 6. Driving an ADC 16 LMP7731 Physical Dimensions inches (millimeters) unless otherwise noted 5-Pin SOT-23 NS Package Number MF05A 8-Pin SOIC NS Package Number M08A 17 www.national.com LMP7731 2.9 nV/sqrt(Hz) Low Noise, Precision, RRIO Amplifier Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Design Support Amplifiers www.national.com/amplifiers WEBENCH® Tools www.national.com/webench Audio www.national.com/audio App Notes www.national.com/appnotes Clock and Timing www.national.com/timing Reference Designs www.national.com/refdesigns Data Converters www.national.com/adc Samples www.national.com/samples Interface www.national.com/interface Eval Boards www.national.com/evalboards LVDS www.national.com/lvds Packaging www.national.com/packaging Power Management www.national.com/power Green Compliance www.national.com/quality/green Switching Regulators www.national.com/switchers Distributors www.national.com/contacts LDOs www.national.com/ldo Quality and Reliability www.national.com/quality LED Lighting www.national.com/led Feedback/Support www.national.com/feedback Voltage Reference www.national.com/vref Design Made Easy www.national.com/easy www.national.com/powerwise Solutions www.national.com/solutions Mil/Aero www.national.com/milaero PowerWise® Solutions Serial Digital Interface (SDI) www.national.com/sdi Temperature Sensors www.national.com/tempsensors SolarMagic™ www.national.com/solarmagic Wireless (PLL/VCO) www.national.com/wireless www.national.com/training PowerWise® Design University THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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