NSC LPV521MGX

LPV521
Nanopower, 1.8V, RRIO, CMOS Input, Operational
Amplifier
General Description
Features
The LPV521 is a single nanopower 552 nW amplifier designed for ultra long life battery applications. The operating
voltage range of 1.6V to 5.5V coupled with typically 351 nA of
supply current make it well suited for RFID readers and remote sensor nanopower applications. The device has input
common mode voltage 0.1V over the rails, guaranteed
TCVOS and voltage swing to the rail output performance. The
LPV521 has a carefully designed CMOS input stage that outperforms competitors with typically 40 fA IBIAS currents. This
low input current significantly reduces IBIAS and IOS errors introduced in megohm resistance, high impedance photodiode,
and charge sense situations. The LPV521 is a member of the
PowerWise® family and has an exceptional power-to-performance ratio.
The wide input common mode voltage range, guaranteed 1
mV VOS and 3.5 µV/°C TCVOS enables accurate and stable
measurement for both high side and low side current sensing.
EMI protection was designed into the device to reduce sensitivity to unwanted RF signals from cell phones or other RFID
readers.
The LPV521 is offered in the 5-pin SC-70 package.
(For VS = 5V, Typical unless otherwise noted)
400 nA (max)
■ Supply current at VCM = 0.3V
1.6V to 5.5V
■ Operating voltage range
3.5 µV/°C (max)
■ Low TCVOS
1 mV (max)
■ VOS
40 fA
■ Input bias current
109 dB
■ PSRR
102 dB
■ CMRR
132 dB
■ Open loop gain
6.2 kHz
■ Gain bandwidth product
2.4 V/ms
■ Slew rate
255 nV/√Hz
■ Input voltage noise at f = 100 Hz
−40°C to 125°C
■ Temperature range
Applications
■
■
■
■
■
■
■
■
Wireless remote sensors
Powerline monitoring
Power meters
Battery powered industrial sensors
Micropower oxygen sensor and gas sensor
Active RFID readers
Zigbee based sensors for HVAC control
Sensor network powered by energy scavenging
Typical Application
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© 2009 National Semiconductor Corporation
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LPV521 Nanopower, 1.8V, RRIO, CMOS Input, Operational Amplifier
August 24, 2009
LPV521
Storage Temperature Range
Junction Temperature (Note 3)
Mounting Temperature
Infrared or Convection (30 sec.)
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
ESD Tolerance (Note 2)
Human Body Model
Machine Model
Charge-Device Model
Any pin relative to VIN+, IN-, OUT Pins
V+, V-, OUT Pins
Differential Input Voltage (VIN+ - VIN-)
−65°C to 150°C
150°C
260°C
Wave Soldering Lead Temp. (4 sec.)
2000V
200V
1000V
6V, −0.3V
V+ + 0.3V, V– – 0.3V
Operating Ratings
(Note 1)
Temperature Range (Note 3)
Supply Voltage (VS = V+ - V−)
−40°C to 125°C
1.6V to 5.5V
Package Thermal Resistance (θJA) (Note 3)
5-Pin SC-70
40mA
±300 mV
1.8V DC Electrical Characteristics
260°C
456 °C/W
(Note 4)
Unless otherwise specified, all limits guaranteed for TA = 25°C, V+ = 1.8V, V− = 0V, VCM = VO = V+/2, and RL > 1 MΩ. Boldface
limits apply at the temperature extremes.
Symbol
VOS
Parameter
Input Offset Voltage
Conditions
Min
(Note 6)
Typ
(Note 5)
Max
(Note 6)
VCM = 0.3V
0.1
±1.0
±1.23
VCM = 1.5V
0.1
±1.0
±1.23
Units
mV
TCVOS
Input Offset Voltage Drift
(Note 9)
±0.4
±3
μV/°C
IBIAS
Input Bias Current
0.01
±1
±50
pA
IOS
Input Offset Current
CMRR
Common Mode Rejection Ratio
10
0V ≤ VCM ≤ 1.8V
66
60
92
0V ≤ VCM ≤ 0.7V
75
74
101
1.2V ≤ VCM ≤ 1.8V
75
53
120
109
PSRR
Power Supply Rejection Ratio
1.6V ≤ V+ ≤ 5.5V
VCM = 0.3V
85
76
CMVR
Common Mode Voltage Range
CMRR ≥ 67 dB
0
0
CMRR ≥ 60 dB
AVOL
Large Signal Voltage Gain
VO = 0.5V to 1.3V
RL = 100 kΩ to
VO
IO
IS
V+/2
74
73
fA
dB
dB
1.8
1.8
125
dB
Output Swing High
RL = 100 kΩ to V+/2
VIN(diff) = 100 mV
2
50
50
Output Swing Low
RL = 100 kΩ to V+/2
VIN(diff) = −100 mV
2
50
50
Output Current (Note 7)
Sourcing, VO to V–
VIN(diff) = 100 mV
1
0.5
3
Sinking, VO to V+
VIN(diff) = −100 mV
1
0.5
3
Supply Current
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mV from
either rail
mA
VCM = 0.3V
345
400
580
VCM = 1.5V
472
600
850
2
V
nA
(Note 4)
Unless otherwise specified, all limits guaranteed for TA = 25°C, V+ = 1.8V, V− = 0V, VCM = VO = V+/2, and RL > 1 MΩ. Boldface
limits apply at the temperature extremes.
Symbol
Parameter
Conditions
Min
(Note 6)
Typ
(Note 5)
GBW
Gain-Bandwidth Product
CL = 20 pF, RL = 100 kΩ
6.1
SR
Slew Rate
AV = +1,
VIN = 0V to 1.8V
Falling Edge
2.9
Rising Edge
2.3
θm
Phase Margin
CL = 20 pF, RL = 100 kΩ
Gm
Gain Margin
CL = 20 pF, RL = 100 kΩ
en
Input-Referred Voltage Noise Density f = 100 Hz
265
Input-Referred Voltage Noise
0.1 Hz to 10 Hz
24
Input-Referred Current Noise
f = 100 Hz
100
in
3.3V DC Electrical Characteristics
Max
(Note 6)
Units
kHz
V/ms
72
deg
19
dB
nV/
μVPP
fA/
(Note 4)
Unless otherwise specified, all limits guaranteed for TA = 25°C, V+ = 3.3V, V− = 0V, VCM = VO = V+/2, and RL > 1 MΩ. Boldface
limits apply at the temperature extremes.
Symbol
VOS
Parameter
Input Offset Voltage
Conditions
Min
(Note 6)
Typ
(Note 5)
Max
(Note 6)
VCM = 0.3V
0.1
±1.0
±1.23
VCM = 3V
0.1
±1.0
±1.23
Units
mV
TCVOS
Input Offset Voltage Drift
(Note 9)
±0.4
±3
μV/°C
IBIAS
Input Bias Current
0.01
±1
±50
pA
IOS
Input Offset Current
CMRR
Common Mode Rejection Ratio
20
0V ≤ VCM ≤ 3.3V
72
70
97
0V ≤ VCM ≤ 2.2V
78
75
106
2.7V ≤ VCM ≤ 3.3V
77
76
121
85
76
109
PSRR
Power Supply Rejection Ratio
1.6V ≤ V+ ≤ 5.5V
VCM = 0.3V
CMVR
Common Mode Voltage Range
CMRR ≥ 72 dB
−0.1
0
CMRR ≥ 70 dB
AVOL
Large Signal Voltage Gain
VO = 0.5V to 2.8V
RL = 100 kΩ to V+/2
VO
IO
Output Swing High
82
76
dB
dB
3.4
3.3
120
RL = 100 kΩ to V+/2
VIN(diff) = 100 mV
3
Output Swing Low
RL = 100 kΩ to V+/2
VIN(diff) = −100 mV
2
Output Current (Note 7)
Sourcing, VO to V–
VIN(diff) = 100 mV
5
4
11
Sinking, VO to V+
VIN(diff) = −100 mV
5
4
12
3
fA
V
dB
50
50
50
50
mV
from either
rail
mA
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LPV521
1.8V AC Electrical Characteristics
LPV521
Symbol
IS
Parameter
Supply Current
Conditions
Typ
(Note 5)
Max
(Note 6)
VCM = 0.3V
346
400
600
VCM = 3V
471
600
860
3.3V AC Electrical Characteristics
Min
(Note 6)
Units
nA
(Note 4)
Unless otherwise is specified, all limits guaranteed for TA = 25°C, V+ = 3.3V, V− = 0V, VCM = VO = V+/2, and RL > 1 MΩ. Boldface limits apply at the temperature extremes.
Symbol
Parameter
Conditions
Min
(Note 6)
Typ
(Note 5)
GBW
Gain-Bandwidth Product
CL = 20 pF, RL = 100 kΩ
6.2
SR
Slew Rate
AV = +1,
VIN = 0V to 3.3V
Falling Edge
2.9
Rising Edge
2.5
θm
Phase Margin
Gm
Gain Margin
en
Input-Referred Voltage Noise Density f = 100 Hz
259
Input-Referred Voltage Noise
0.1 Hz to 10 Hz
22
Input-Referred Current Noise
f = 100 Hz
100
in
Max
(Note 6)
Units
kHz
V/ms
CL = 20 pF, RL = 10 kΩ
73
deg
CL = 20 pF, RL = 10 kΩ
19
dB
5V DC Electrical Characteristics
nV/
μVPP
fA/
(Note 4)
Unless otherwise specified, all limits guaranteed for TA = 25°C, V+ = 5V, V− = 0V, VCM = VO = V+/2, and RL > 1MΩ. Boldface limits
apply at the temperature extremes.
Symbol
VOS
Parameter
Input Offset Voltage
Conditions
Min
(Note 6)
Typ
(Note 5)
Max
(Note 6)
VCM = 0.3V
0.1
±1.0
±1.23
VCM = 4.7V
0.1
±1.0
±1.23
Units
mV
TCVOS
Input Offset Voltage Drift
(Note 9)
±0.4
±3.5
μV/°C
IBIAS
Input Bias Current
0.04
±1
±50
pA
IOS
Input Offset Current
CMRR
Common Mode Rejection Ratio
60
0V ≤ VCM ≤ 5.0V
75
74
102
0V ≤ VCM ≤ 3.9V
84
80
108
4.4V ≤ VCM ≤ 5.0V
77
76
115
85
76
109
PSRR
Power Supply Rejection Ratio
1.6V ≤ V+ ≤ 5.5V
VCM = 0.3V
CMVR
Common Mode Voltage Range
CMRR ≥ 75 dB
−0.1
0
CMRR ≥ 74 dB
AVOL
Large Signal Voltage Gain
VO = 0.5V to 4.5V
RL = 100 kΩ to V+/2
VO
84
76
fA
dB
dB
5.1
5
132
dB
Output Swing High
RL = 100 kΩ to V+/2
VIN(diff) = 100 mV
3
50
50
Output Swing Low
V+/2
3
50
50
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RL = 100 kΩ to
VIN (diff) = −100 mV
4
V
mV from
either rail
IO
Parameter
Output Current (Note 7)
IS
Supply Current
Conditions
Min
(Note 6)
Typ
(Note 5)
Sourcing, VO to V−
VIN(diff) = 100 mV
15
8
23
Sinking, VO to V+
VIN(diff) = −100 mV
15
8
22
Max
(Note 6)
mA
VCM = 0.3V
351
400
620
VCM = 4.7V
475
600
870
5V AC Electrical Characteristics
Units
nA
(Note 4)
Unless otherwise specified, all limits guaranteed for TA = 25°C, V+ = 5V, V− = 0V, VCM = VO = V+/2, and RL > 1MΩ. Boldface limits
apply at the temperature extremes.
Symbol
Parameter
Conditions
GBW
Gain-Bandwidth Product
CL = 20 pF, RL = 100 kΩ
SR
Slew Rate
AV = +1,
VIN = 0V to 5V
Min
(Note 6)
Typ
(Note 5)
Max
(Note 6)
Units
6.2
Falling Edge
1.1
1.2
2.7
Rising Edge
1.1
1.2
2.4
θm
Phase Margin
Gm
Gain Margin
en
Input-Referred Voltage Noise Density f = 100 Hz
255
Input-Referred Voltage Noise
0.1 Hz to 10 Hz
22
in
Input-Referred Current Noise
f = 100 Hz
100
EMIRR
EMI Rejection Ratio, IN+ and IN−
(Note 8)
VRF_PEAK = 100 mVP (−20 dBP),
f = 400 MHz
121
VRF_PEAK = 100 mVP (−20 dBP),
f = 900 MHz
121
VRF_PEAK = 100 mVP (−20 dBP),
f = 1800 MHz
124
VRF_PEAK = 100 mVP (−20 dBP),
f = 2400 MHz
142
kHz
V/ms
CL = 20 pF, RL = 100 kΩ
73
deg
CL = 20 pF, RL = 100 kΩ
20
dB
nV/
μVPP
fA/
dB
Note 1: Absolute Maximum Ratings indicate limits beyond which damage may occur. Operating Ratings indicate conditions for which the device is intended to
be functional, but specific performance is not guaranteed. For guaranteed specifications and test conditions, see the Electrical Characteristics.
Note 2: Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC)
Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
Note 3: The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
Note 4: Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating
of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ >
TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically.
Note 5: Typical values represent the most likely parametric norm at the time of characterization. Actual typical values may vary over time and will also depend
on the application and configuration. The typical values are not tested and are not guaranteed on shipped production material.
Note 6: All limits are guaranteed by testing, statistical analysis or design.
Note 7: The short circuit test is a momentary open loop test.
Note 8: The EMI Rejection Ratio is defined as EMIRR = 20log (VRF_PEAK/ΔVOS).
Note 9: The offset voltage average drift is determined by dividing the change in VOS at the temperature extremes by the total temperature change.
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LPV521
Symbol
LPV521
Connection Diagram
5-Pin SC-70
30054581
Top View
Ordering Information
Package
Part Number
Package Marking
LPV521MG
5-Pin SC-70
LPV521MGE
AHA
250 Units Tape and Reel
LPV521MGX
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Transport Media
NSC Drawing
1k Units Tape and Reel
3k Units Tape and Reel
6
MAA05A
LPV521
Typical Performance Characteristics
At TJ = 25°C, unless otherwise specified.
Supply Current vs. Supply Voltage
Supply Current vs. Supply Voltage
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Offset Voltage Distribution
TCVOS Distribution
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Offset Voltage Distribution
TCVOS Distribution
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LPV521
Offset Voltage Distribution
TCVOS Distribution
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Input Offset Voltage vs. Input Common Mode
Input Offset Voltage vs. Input Common Mode
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Input Offset Voltage vs. Input Common Mode
Input Offset Voltage vs. Supply Voltage
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Input Offset Voltage vs. Output Voltage
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Input Offset Voltage vs. Output Voltage
Input Offset Voltage vs. Output Voltage
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Input Offset Voltage vs. Sourcing Current
Input Offset Voltage vs. Sourcing Current
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LPV521
Input Offset Voltage vs. Supply Voltage
LPV521
Input Offset Voltage vs. Sourcing Current
Input Offset Voltage vs. Sinking Current
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Input Offset Voltage vs. Sinking Current
Input Offset Voltage vs. Sinking Current
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Sourcing Current vs. Output Voltage
Sinking Current vs. Output Voltage
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LPV521
Sourcing Current vs. Output Voltage
Sinking Current vs. Output Voltage
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Sourcing Current vs. Output Voltage
Sinking Current vs. Output Voltage
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Sourcing Current vs. Supply Voltage
Sinking Current vs. Supply Voltage
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LPV521
Output Swing High vs. Supply Voltage
Output Swing Low vs. Supply Voltage
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Input Bias Current vs. Common Mode Voltage
Input Bias Current vs. Common Mode Voltage
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Input Bias Current vs. Common Mode Voltage
Input Bias Current vs. Common Mode Voltage
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Input Bias Current vs. Common Mode Voltage
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PSRR vs. Frequency
CMRR vs. Frequency
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Frequency Response vs. Temperature
Frequency Response vs. Temperature
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LPV521
Input Bias Current vs. Common Mode Voltage
LPV521
Frequency Response vs. Temperature
Frequency Response vs. RL
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Frequency Response vs. RL
Frequency Response vs. RL
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Frequency Response vs. CL
Frequency Response vs. CL
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LPV521
Frequency Response vs. CL
Slew Rate vs. Supply Voltage
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Voltage Noise vs. Frequency
0.1 to 10 Hz Time Domain Voltage Noise
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0.1 to 10 Hz Time Domain Voltage Noise
0.1 to 10 Hz Time Domain Voltage Noise
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LPV521
Small Signal Pulse Response
Small Signal Pulse Response
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Large Signal Pulse Response
Large Signal Pulse Response
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Overload Recovery Waveform
EMIRR vs. Frequency
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LPV521
Application Information
The LPV521 is fabricated with National Semiconductor's
state-of-the-art VIP50 process. This proprietary process dramatically improves the performance of National
Semiconductor's low-power and low-voltage operational amplifiers. The following sections showcase the advantages of
the VIP50 process and highlight circuits which enable ultralow power consumption.
60 HZ TWIN T NOTCH FILTER
Small signals from transducers in remote and distributed
sensing applications commonly suffer strong 60 Hz interference from AC power lines. The circuit of Figure 1 notches out
the 60 Hz and provides a gain AV = 2 for the sensor signal
represented by a 1 kHz sine wave. Similar stages may be
cascaded to remove 2nd and 3rd harmonics of 60 Hz. Thanks
to the nA power consumption of the LPV521, even 5 such
circuits can run for 9.5 years from a small CR2032 lithium cell.
These batteries have a nominal voltage of 3V and an end of
life voltage of 2V. With an operating voltage from 1.6V to 5.5V
the LPV521 can function over this voltage range.
The notch frequency is set by F0 = 1/2πRC. To achieve a 60
Hz notch use R = 10 MΩ and C = 270 pF. If eliminating 50 Hz
noise, which is common in European systems, use R = 11.8
MΩ and C = 270 pF.
The Twin T Notch Filter works by having two separate paths
from VIN to the amplifier’s input. A low frequency path through
the resistors R - R and another separate high frequency path
through the capacitors C - C. However, at frequencies around
the notch frequency, the two paths have opposing phase angles and the two signals will tend to cancel at the amplifier’s
input.
To ensure that the target center frequency is achieved and to
maximize the notch depth (Q factor) the filter needs to be as
balanced as possible. To obtain circuit balance, while overcoming limitations of available standard resistor and capacitor
values, use passives in parallel to achieve the 2C and R/2
circuit requirements for the filter components that connect to
ground.
To make sure passive component values stay as expected
clean board with alcohol, rinse with deionized water, and air
dry. Make sure board remains in a relatively low humidity environment to minimize moisture which may increase the conductivity of board components. Also large resistors come with
considerable parasitic stray capacitance which effects can be
reduced by cutting out the ground plane below components
of concern.
Large resistors are used in the feedback network to minimize
battery drain. When designing with large resistors, resistor
thermal noise, op amp current noise, as well as op amp voltage noise, must be considered in the noise analysis of the
circuit. The noise analysis for the circuit in Figure 1 can be
done over a bandwidth of 5 kHz, which takes the conservative
approach of overestimating the bandwidth (LPV521 typical
GBW/AV is lower). The total noise at the output is approximately 800 µVpp, which is excellent considering the total
consumption of the circuit is only 540 nA. The dominant noise
terms are op amp voltage noise (550 µVpp), current noise
through the feedback network (430 µVpp), and current noise
through the notch filter network (280 µVpp). Thus the total
circuit's noise is below 1/2 LSB of a 10 bit system with a 2 V
reference, which is 1 mV.
30054576
FIGURE 1. 60 Hz Notch Filter
30054577
FIGURE 2. 60 Hz Notch Filter Waveform
BATTERY CURRENT SENSING
The rail-to-rail common mode input range and the very low
quiescent current make the LPV521 ideal to use in high side
and low side battery current sensing applications. The high
side current sensing circuit in Figure 3 is commonly used in a
battery charger to monitor the charging current in order to
prevent over charging. A sense resistor RSENSE is connected
in series with the battery. The theoretical output voltage of the
circuit is VOUT = [ (RSENSE × R3) / R1 ] × ICHARGE. In reality,
however, due to the finite Current Gain, β, of the transistor the
current that travels through R3 will not be ICHARGE, but instead,
will be α × ICHARGE or β/( β+1) × ICHARGE. A Darlington pair can
be used to increase the β and performance of the measuring
circuit. Using the components shown in Figure 3 will result in
VOUT ≈ 4000 Ω × ICHARGE. This is ideal to amplify a 1 mA
ICHARGE to near full scale of an ADC with VREF at 4.1V. A resistor, R2 is used at the non-inverting input of the amplifier,
with the same value as R1 to minimize offset voltage. Selecting values per Figure 3 will limit the current traveling through
the R1 – Q1 – R3 leg of the circuit to under 1 µA which is on
the same order as the LPV521 supply current. Increasing resistors R1 , R2 , and R3 will decrease the measuring circuit
supply current and extend battery life. Decreasing RSENSE will
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LPV521
minimize error due to resistor tolerance, however, this will also decrease VSENSE = ICHARGE × RSENSE, and in turn the
amplifier offset voltage will have a more significant contribution to the total error of the circuit. With the components shown
in Figure 3 the measurement circuit supply current can be
kept below 1.5 µA and measure 100 µA to 1 mA..
TCVOS , low input bias current, high CMRR, and high PSRR
are other factors which make the LPV521 a great choice for
this application.
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FIGURE 4. Precision Oxygen Sensor
INPUT STAGE
The LPV521 has a rail-to-rail input which provides more flexibility for the system designer. Rail-to-rail input is achieved by
using in parallel, one PMOS differential pair and one NMOS
differential pair. When the common mode input voltage
(VCM) is near V+, the NMOS pair is on and the PMOS pair is
off. When VCM is near V−, the NMOS pair is off and the PMOS
pair is on. When VCM is between V+ and V−, internal logic
decides how much current each differential pair will get. This
special logic ensures stable and low distortion amplifier operation within the entire common mode voltage range.
Because both input stages have their own offset voltage
(VOS) characteristic, the offset voltage of the LPV521 becomes a function of VCM. VOS has a crossover point at 1.0V
below V+. Refer to the ’VOS vs. VCM’ curve in the Typical Performance Characteristics section. Caution should be taken in
situations where the input signal amplitude is comparable to
the VOS value and/or the design requires high accuracy. In
these situations, it is necessary for the input signal to avoid
the crossover point. In addition, parameters such as PSRR
and CMRR which involve the input offset voltage will also be
affected by changes in VCM across the differential pair transition region.
30054502
FIGURE 3. High Side Current Sensing
PORTABLE GAS DETECTION SENSOR
Gas sensors are used in many different industrial and medical
applications. They generate a current which is proportional to
the percentage of a particular gas sensed in an air sample.
This current goes through a load resistor and the resulting
voltage drop is measured. Depending on the sensed gas and
sensitivity of the sensor, the output current can be in the order
of tens of microamperes to a few milliamperes. Gas sensor
datasheets often specify a recommended load resistor value
or they suggest a range of load resistors to choose from.
Oxygen sensors are used when air quality or oxygen delivered to a patient needs to be monitored. Fresh air contains
20.9% oxygen. Air samples containing less than 18% oxygen
are considered dangerous. Oxygen sensors are also used in
industrial applications where the environment must lack oxygen. An example is when food is vacuum packed. There are
two main categories of oxygen sensors, those which sense
oxygen when it is abundantly present (i.e. in air or near an
oxygen tank) and those which detect traces of oxygen in ppm.
Figure 4 shows a typical circuit used to amplify the output of
an oxygen detector. The LPV521 makes an excellent choice
for this application as it only draws 345 nA of current and operates on supply voltages down to 1.6V. This application
detects oxygen in air. The oxygen sensor outputs a known
current through the load resistor. This value changes with the
amount of oxygen present in the air sample. Oxygen sensors
usually recommend a particular load resistor value or specify
a range of acceptable values for the load resistor. Oxygen
sensors typically have a life of one to two years. The use of
the nanopower LPV521 means minimal power usage by the
op amp and it enhances the battery life. With the components
shown in Figure 4 the circuit can consume less than 0.5 µA
of current ensuring that even batteries used in compact
portable electronics, with low mAh charge ratings, could last
beyond the life of the oxygen sensor. The precision specifications of the LPV521, such as its very low offset voltage, low
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OUTPUT STAGE
The LPV521 output voltage swings 3 mV from rails at 3.3V
supply, which provides the maximum possible dynamic range
at the output. This is particularly important when operating on
low supply voltages.
The LPV521 Maximum Output Voltage Swing defines the
maximum swing possible under a particular output load. The
LPV521 output swings 50 mV from the rail at 5V supply with
an output load of 100 kΩ.
DRIVING CAPACITIVE LOAD
The LPV521 is internally compensated for stable unity gain
operation, with a 6.2 kHz typical gain bandwidth. However,
the unity gain follower is the most sensitive configuration to
capacitive load. The combination of a capacitive load placed
at the output of an amplifier along with the amplifier’s output
impedance creates a phase lag, which reduces the phase
margin of the amplifier. If the phase margin is significantly reduced, the response will be under damped which causes
18
EMI SUPPRESSION
The near-ubiquity of cellular, bluetooth, and Wi-Fi signals and
the rapid rise of sensing systems incorporating wireless radios make electromagnetic interference (EMI) an evermore
important design consideration for precision signal paths.
Though RF signals lie outside the op amp band, RF carrier
switching can modulate the DC offset of the op amp. Also
some common RF modulation schemes can induce downconverted components. The added DC offset and the induced
signals are amplified with the signal of interest and thus corrupt the measurement. The LPV521 uses on chip filters to
reject these unwanted RF signals at the inputs and power
supply pins; thereby preserving the integrity of the precision
signal path.
Twisted pair cabling and the active front-end’s common-mode
rejection provide immunity against low frequency noise (i.e.
60 Hz or 50 Hz mains) but are ineffective against RF interference. Even a few centimeters of PCB trace and wiring for
sensors located close to the amplifier can pick up significant
1 GHz RF. The integrated EMI filters of the LPV521 reduce
or eliminate external shielding and filtering requirements,
thereby increasing system robustness. A larger EMIRR
means more rejection of the RF interference. For more information on EMIRR, please refer to AN-1698.
30054555
FIGURE 5. Resistive Isolation of Capacitive Load
Recommended minimum values for RISO are given in the following table, for 5V supply. Figure 6 shows the typical response obtained with the CL = 50 pF and RISO = 154 kΩ. The
other values of RISO in the table were chosen to achieve similar dampening at their respective capacitive loads. Notice
that for the LPV521 with larger CL a smaller RISO can be used
for stability. However, for a given CL a larger RISO will provide
a more damped response. For capacitive loads of 20 pF and
below no isolation resistor is needed.
CL
RISO
0 – 20 pF
not needed
50 pF
154 kΩ
100 pF
118 kΩ
500 pF
52.3 kΩ
1 nF
33.2 kΩ
5 nF
17.4 kΩ
10 nF
13.3 kΩ
POWER SUPPLIES AND LAYOUT
The LPV521 operates from a single 1.6V to 5.5V power supply. It is recommended to bypass the power supplies with a
0.1 μF ceramic capacitor placed close to the V+ and V− pins.
Ground layout improves performance by decreasing the
amount of stray capacitance and noise at the op amp's inputs
and outputs. To decrease stray capacitance, minimize PC
board trace lengths and resistor leads, and place external
components close to the op amps' pins.
30054580
FIGURE 6. Step Response
19
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LPV521
peaking in the transfer and, when there is too much peaking,
the op amp might start oscillating.
In order to drive heavy capacitive loads, an isolation resistor,
RISO, should be used, as shown in Figure 5. By using this
isolation resistor, the capacitive load is isolated from the
amplifier’s output. The larger the value of RISO, the more stable the amplifier will be. If the value of RISO is sufficiently large,
the feedback loop will be stable, independent of the value of
CL. However, larger values of RISO result in reduced output
swing and reduced output current drive.
LPV521
Physical Dimensions inches (millimeters) unless otherwise noted
5-Pin SC-70
NS Package Number MAA05A
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20
LPV521
Notes
21
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LPV521 Nanopower, 1.8V, RRIO, CMOS Input, Operational Amplifier
Notes
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