54ACTQ273 Quiet Series Octal D Flip-Flop General Description The ACTQ273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) input load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. The ACTQ utilizes NSC Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series™ features GTO™ output control and undershoot corrector in addition to a split ground bus for superior performance. Features n ICC reduced by 50% n Guaranteed simultaneous switching noise level and dynamic threshold performance n Improved latch-up immunity n Buffered common clock and asynchronous master reset n Outputs source/sink 24 mA n Faster prop delays than the standard ’AC/’ACT273 n 4 kV minimum ESD immunity n Standard Microcircuit Drawing (SMD) 5962-89735 Logic Symbols IEEE/IEC DS100240-1 DS100240-2 Pin Names Description D0–D7 Data Inputs MR Master Reset CP Clock Pulse Input Q0–Q7 Data Outputs GTO™ is a trademark of National Semiconductor Corporation. FACT ® is a registered trademark of Fairchild Semiconductor Corporation. FACT Quiet Series™ is a trademark of Fairchild Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100240 www.national.com 54ACTQ273 Quiet Series Octal D Flip-Flop August 1998 Connection Diagrams Pin Assignment for DIP and Flatpak Pin Assignment for LCC DS100240-4 DS100240-3 Mode Select-Function Table Operating Mode Inputs Outputs MR CP Dn Reset (Clear) L X X L Load “1” H N H H Load “0” H N L L Qn Note 1: H = HIGH Voltage Level Note 2: L = LOW Voltage Level Note 3: X = Immaterial Note 4: N = LOW-to-HIGH Transition Logic Diagram DS100240-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.national.com 2 Absolute Maximum Ratings (Note 5) DC Latch-up Source or Sink Current Junction Temperature (TJ) CDIP If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) −0.5V to +7.0V ± 300 mA 175˚C Recommended Operating Conditions −20 mA +20 mA −0.5V to VCC + 0.5V Supply Voltage (VCC) ’ACTQ Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 54ACTQ Minimum Input Edge Rate ∆V/∆t ’ACTQ Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V −20 mA +20 mA −0.5V to VCC + 0.5V ± 50 mA ± 50 mA −65˚C to +150˚C 4.5V to 5.5V 0V to VCC 0V to VCC −55˚C to +125˚C 125 mV/ns Note 5: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT ® circuits outside databook specifications. Note 6: All commercial packaging is not recommended for applications requiring greater than 2000 temperature cycles from −40˚C to +125˚C. DC Characteristics for ’ACTQ Family Devices Symbol Parameter VCC 54ACTQ TA = −55˚C (V) to +125˚C Units Conditions Guaranteed Limits VIH VIL VOH VOL IIN Minimum High Level 4.5 2.0 Input Voltage 5.5 2.0 Maximum Low Level 4.5 0.8 Input Voltage 5.5 0.8 Minimum High Level 4.5 4.4 Output Voltage 5.5 5.4 4.5 3.7 5.5 4.7 Maximum Low Level 4.5 0.1 Output Voltage 5.5 0.1 Maximum Input V VOUT = 0.1V V or VCC − 0.1V VOUT = 0.1V V or VCC − 0.1V IOUT = −50 µA V (Note 7) VIN = VIL or VIH IOH = −24 mA V IOH = −24 mA IOUT = 50 µA V (Note 7) VIN = VIL or VIH IOL = 24 mA 4.5 0.50 5.5 0.50 5.5 ± 1.0 µA IOL = 24 mA VI = VCC, GND 5.5 1.6 mA VI = VCC − 2.1V VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC Leakage Current ICCT Maximum ICC/Input IOLD Minimum Dynamic Output Current (Note 8) 5.5 50 mA IOHD 5.5 −50 mA ICC Maximum Quiescent 5.5 80.0 µA Supply Current or GND (Note 9) 3 www.national.com DC Characteristics for ’ACTQ Family Devices Symbol Parameter (Continued) VCC 54ACTQ TA = −55˚C (V) to +125˚C Units Conditions Guaranteed Limits VOLP Quiet Output 5.0 1.5 V (Note 10) 5.0 −1.2 V (Note 10) Maximum Dynamic VOL VOLV Quiet Output Minimum Dynamic VOL Note 7: All outputs loaded; thresholds on input associated with output under test. Note 8: Maximum test duration 2.0 ms, one output loaded at a time. Note 9: ICC for 54ACTQ @ 25˚C is identical to 74ACTQ @ 25˚C. Note 10: Max number of outputs defined as (n). n − 1 Data inputs are driven 0V to 3V; one output @ GND. Note 11: Max number of Data Inputs (n) switching. (n − 1) Inputs switching 0V to 3V (’ACTQ). Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD) f = 1 MHz. AC Electrical Characteristics 54ACTQ TA = −55˚C VCC Symbol Parameter (V) (Note 12) Min fmax Maximum Clock Fig. to +125˚C CL = 50 pF Units No. Max 5.0 85 MHz Frequency tPHL, tPLH Propagation Delay Clock to Output 5.0 1.5 10.0 ns tPHL Propagation Delay 5.0 1.5 11.0 ns Figure 4 Figure 4 MR to Output Note 12: Voltage Range 5.0 is 5.0V ± 0.5V. AC Operating Requirements 54ACTQ TA = −55˚C VCC Symbol Parameter (V) to +125˚C CL = 50 pF (Note 13) Fig. Units No. Guaranteed Minimum ts Setup Time, HIGH or LOW Figure 6 5.0 5.0 ns 5.0 2.0 ns 5.0 5.0 ns Figure 5 5.0 5.0 ns Figure 5 5.0 4.0 ns Figure 6 Data to CP th Hold Time, HIGH or LOW Figure 6 Data to CP tw Clock Pulse Width HIGH or LOW tw MR Pulse Width HIGH or LOW trec Recovery Time MR to CP Note 13: Voltage Range 5.0 is 5.0V ± 0.5V www.national.com 4 Capacitance Symbol Parameter CIN CPD Typ Units Input Capacitance 4.5 pF Power Dissipation 40.0 pF Conditions VCC = OPEN VCC = 5.0V Capacitance AC Loading AC Waveforms DS100240-33 FIGURE 4. Propogation Delay Waveforms for Inverting and Non-Inverting Functions DS100240-31 *Includes jig and probe capacitance FIGURE 1. Standard AC Test Load DS100240-34 FIGURE 5. Propogation Delay, Pulse Width Waveforms DS100240-32 FIGURE 2. Test Input Signal Levels Amplitude Rep.Rate tw tr tf 3.0V 1 MHz 500 ns 2.5 ns 2.5 ns FIGURE 3. Test Input Signal Requirements DS100240-35 FIGURE 6. Setup Time, Hold Time and Recovery Time Waveforms 5 www.national.com 6 Physical Dimensions inches (millimeters) unless otherwise noted 20-Terminal Ceramic Leadless Chip Carrier (L) NS Package Number E20A 20-Lead Ceramic Dual-In-Line Package (D) NS Package Number J20A 7 www.national.com 54ACTQ273 Quiet Series Octal D Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20 Lead Ceramic Flatpak (F) NS Package Number W20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. 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