STV7619DU ® Scan Driver for Plasma Display Panels Main Features ■ 64-output Scan Driver ■ 120 V Absolute Maximum Supply ■ 5 V Logic Supply ■ Optional 12 V Supply for driving the output stage ■ 150mA/1A Source/Sink Output ■ 1 A Source/Sink Output Diode ■ 64-bit Bi-directional Shift Register (8 MHz) ■ BCD Technology ■ 100-pin TQFP package with integrated heatsink TQFP100 (14 x 14 x 1.4 mm Slug-down) (Thin Plastic Quad Flat Pack) ORDER CODE: STV7619D Description The STV7619 is a scan driver for plasma display panels (PDP) implemented in ST’s proprietary BCD (Bi-polar CMOS DMOS) technology. Using a 64-bit cascadable 8 MHz shift register, it drives 64 highcurrent and high-voltage outputs. By connecting several STV7619 devices in series, any vertical pixel definition can be performed. The STV7619 is supplied with separate 110V power output and 5 V logic supplies. The logic section of the output stage is supplied either externally by a 5V or 12V supply or internally by a charge pump cell. The choice of the supply value is related to the PDP size. All command inputs are CMOS compatible. TQFP100 (14 x 14 x 1.4 mm) (Thin Plastic Quad Flat Pack) ORDER CODE: STV7619 The STV7619 package is a 100-pin TQFP with integrated heatsink located on the bottom (STV7619D) of the package. It is also available without heatsink (STV7619). August 2003 1/21 STV7619DU Table of Contents Chapter 1 1.1 Pin Allocation and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Pinout Diagrams ............................................................................................................... 3 Chapter 2 Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Chapter 3 Application Hints: Charge Pump Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.1 Power Supply ....................................................................................................................... 9 3.2 Sink Current Characteristics .............................................................................................. 10 3.3 Recommendations ............................................................................................................. 10 Chapter 4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.1 Absolute Maximum Ratings .............................................................................................. 11 4.2 Thermal Data .................................................................................................................... 12 4.3 Supply Characteristics ....................................................................................................... 12 4.4 Power Output Characteristics ........................................................................................... 13 4.5 SOUT Characteristics ....................................................................................................... 14 4.6 Input (CLK, STB, BLK, POC, SIN, CLR, F/R and ENABLE) Characteristics .................... 14 4.7 AC Timing Requirements ................................................................................................... 14 4.8 AC Timing Characteristics ................................................................................................. 15 Chapter 5 Input/Output Schematic Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Chapter 6 Package Mechanical Data Chapter 7 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 2/21 Pin Allocation and Descriptions STV7619DU 1 Pin Allocation and Descriptions 1.1 Pinout Diagrams SOUT VDD VSSLOG VSSP VSSP NC* VPP 85 83 82 81 80 79 OUT62 CLK 86 76 STB 87 OUT64 VCC 88 OUT63 BLK 89 77 POC 90 78 SIN 91 84 F/R CLR VSSP 94 92 NC* VSSP 96 93 OUT1 VPP 98 95 OUT2 99 OUT4 1 75 OUT61 OUT5 2 74 OUT60 OUT6 3 73 OUT59 OUT7 4 72 OUT58 OUT8 5 71 OUT57 OUT9 6 70 OUT56 OUT10 7 69 OUT55 OUT11 8 68 OUT54 OUT12 9 67 OUT53 OUT13 10 66 OUT52 OUT14 11 65 OUT51 OUT15 12 64 OUT50 OUT16 13 63 OUT49 OUT17 14 62 OUT48 OUT18 15 61 OUT47 OUT19 16 60 OUT46 OUT20 17 59 OUT45 OUT21 18 58 OUT44 OUT22 19 57 OUT43 OUT23 20 56 OUT42 OUT24 21 55 OUT41 OUT25 22 54 OUT40 OUT26 23 53 OUT39 OUT27 24 52 OUT38 OUT28 25 51 OUT37 47 48 49 50 OUT34 OUT35 OUT36 46 OUT33 43 VPP 45 42 VSSP 41 44 40 NC* VPP NC* VSSP 39 38 ENABLE VSSSUB 37 VSSLOG 36 VSSLOG 32 NC* VPP VSSSUB 31 VSSP 35 30 VSSP NC* 29 OUT32 34 28 OUT31 33 27 OUT30 VPP 26 OUT29 TQFP100 (Top View) *NC: Not Connected 3/21 97 OUT3 100 Figure 1: STV7619 and STV7619D (TQFP100) STV7619DU Pin Allocation and Descriptions Table 1: Supply Pins Pin No. Pin Name Pin Description 88 VCC 5V Logic Supply 84 VDD 5/12V Internal/External Logic Supply 33 VPP High Voltage Supply for Power Outputs 34 VPP High Voltage Supply for Power Outputs 42 VPP High Voltage Supply for Power Outputs 43 VPP High Voltage Supply for Power Outputs 79 VPP High Voltage Supply for Power Outputs 97 VPP High Voltage Supply for Power Outputs 36 VSSLOG Logic Ground 40 VSSLOG Logic Ground 83 VSSLOG Logic Ground 30 VSSP Ground for Power Outputs 31 VSSP Ground for Power Outputs 45 VSSP Ground for Power Outputs 46 VSSP Ground for Power Outputs 81 VSSP Ground for Power Outputs 82 VSSP Ground for Power Outputs 94 VSSP Ground for Power Outputs 95 VSSP Ground for Power Outputs 37 VSSSUB Substrate Ground 39 VSSSUB Substrate Ground Table 2: Shift Register and Input Pins Pin No. Pin Name Pin Description 38 ENABLE 85 SOUT 86 CLK Clock for Shift Register Data 87 STB Latch for Shift Register Data (Strobe Input) 89 BLK Blanking Control for Power Outputs 90 POC Polarity Output Control 91 SIN Shift Register Data Input 92 CLR Clear for Shift Register Data 93 F/R Foward/Reserve modes for selecting Shift Register Enable Charge Pump mode Shift Register Data Output 4/21 Pin Allocation and Descriptions STV7619DU Table 3: Power Output Pins Pin No. Pin Name 98 OUT1 99 5/21 Pin Description Pin No. Pin Name Pin Description Power Output 1 47 OUT33 Power Output 33 OUT2 Power Output 2 48 OUT34 Power Output 34 100 OUT3 Power Output 3 49 OUT35 Power Output 35 1 OUT4 Power Output 4 50 OUT36 Power Output 36 2 OUT5 Power Output 5 51 OUT37 Power Output 37 3 OUT6 Power Output 6 52 OUT38 Power Output 38 4 OUT7 Power Output 7 53 OUT39 Power Output 39 5 OUT8 Power Output 8 54 OUT40 Power Output 40 6 OUT9 Power Output 9 55 OUT41 Power Output 41 7 OUT10 Power Output 10 56 OUT42 Power Output 42 8 OUT11 Power Output 11 57 OUT43 Power Output 43 9 OUT12 Power Output 12 58 OUT44 Power Output 44 10 OUT13 Power Output 13 59 OUT45 Power Output 45 11 OUT14 Power Output 14 60 OUT46 Power Output 46 12 OUT15 Power Output 15 61 OUT47 Power Output 47 13 OUT16 Power Output 16 62 OUT48 Power Output 48 14 OUT17 Power Output 17 63 OUT49 Power Output 49 15 OUT18 Power Output 18 64 OUT50 Power Output 50 16 OUT19 Power Output 19 65 OUT51 Power Output 51 17 OUT20 Power Output 20 66 OUT52 Power Output 52 18 OUT21 Power Output 21 67 OUT53 Power Output 53 19 OUT22 Power Output 22 68 OUT54 Power Output 54 20 OUT23 Power Output 23 69 OUT55 Power Output 55 21 OUT24 Power Output 24 70 OUT56 Power Output 56 22 OUT25 Power Output 25 71 OUT57 Power Output 57 23 OUT26 Power Output 26 72 OUT58 Power Output 58 24 OUT27 Power Output 27 73 OUT59 Power Output 59 25 OUT28 Power Output 28 74 OUT60 Power Output 60 26 OUT29 Power Output 29 75 OUT61 Power Output 61 27 OUT30 Power Output 30 76 OUT62 Power Output 62 28 OUT31 Power Output 31 77 OUT63 Power Output 63 29 OUT32 Power Output 32 78 OUT64 Power Output 64 STV7619DU Pin Allocation and Descriptions Table 4: Miscellaneous Pins Pin No. Pin Name Pin Description 32 NC Not connected 35 NC Not connected 41 NC Not connected 44 NC Not connected 80 NC Not connected 96 NC Not connected 6/21 Circuit Description 2 STV7619DU Circuit Description Figure 2: Block Diagram CLR F/R CLK 64-bit Shift Register SIN (SOUT) SOUT (SIN) P 64 P1 S1 S64 Latch STB Q1 Q2 Q63 Q64 VCC BLK VSSSUB VSSP POC VSSLOG Voltage Generator VSSP STV7619 VSSP VPP VPP Vcc VPP VDD ENABLE OUT64 OUT1 The STV7619 includes all the necessary logic and power circuits to drive the rows of electrodes of a plasma display panel (PDP). Data is shifted at each low to high transition of the (CLK) shift clock. After 64 shifts, the first bit presented at the serial input (SIN) is available at the serial output (SOUT). This output is used to cascade several drivers to perform any vertical resolution (Table 5). CLK, STB, SIN and SOUT inputs are Schmitt trigger inputs. Table 5: Shift Register Truth Table F/R CLK SIN SOUT Comments H Rise In Out Forward Shift H L or H In Out Steady L Rise Out In Reverse Shift L L or H Out In Steady In reverse mode (F/R = low), data is input on the SOUT pin and output on the SIN pin. The clear signal (CLR) sets the shift register data to low. Shift register outputs (P1, ... P64) are transferred from the shift register to the latch stage when the latch input (STB) is at low level. All the data is kept memorized in the latch stage when the strobe input (STB) is pulled high. 7/21 STV7619DU Circuit Description Driver outputs can be simultaneously polarized at high or low level depending on the biasing of the POC input signal (Table 6). Table 6: Output State Configuration STB CLR POC BLK * * L * All at low level * * H H All at high level L H H L All at high level L L H L Inverted copy of input data H * H L Inverted copy of latched data Comments The STV7619 integrates a charge pump cell to manage the current drive capabilities of the output sink transistor, as explained in Table 7. More details are given in Chapter 3. Table 7: Voltage Generator Table ENABLE VDD Output Performances External Power Supply (VDD = 5V) Minimum Sink Current mode External Power Supply (VDD = 12V) Maximum Sink Current mode Internal Power Supply (Charge Pump mode) VDD connected to an external capacitance (CVDD = 100nF (20V)) Medium Sink Current mode L H 8/21 Application Hints: Charge Pump Function STV7619DU 3 Application Hints: Charge Pump Function 3.1 Power Supply The STV7619 is designed to drive panels up to 42” with low voltage logic supplies (pins VCC and VDD). In this case, pin VDD must be connected to pin VCC. The driving of large panels (50”, 60”) requires a 100 nF capacitor connected between pin VDD and the ground. An internal charge pump provides a higher driving voltage for the low stage. If requested, higher performances are obtained when a 12V power supply is directly connected to pin VDD. The logic supply management of the output stage mainly depends on the write current value of the plasma cells. The write current is related to the size of the PDP. The following figures illustrate the different possibilities to supply the STV7619 according to the current drive performances requested by the plasma panel. Figure 3: External Power Supply (Small-size PDP) 110V 5V VCC VPP STV7619 VDD ENABLE Figure 4: External Power Supply (Large-size PDP) 110V 5V VCC VPP STV7619 12V ENABLE VDD Figure 5: Internal Power Supply, Charge Pump mode (Medium- or Large-size PDP) 110V VCC VPP 5V STV7619 VDD 100nF (16V) 9/21 ENABLE STV7619DU 3.2 Application Hints: Charge Pump Function Sink Current Characteristics Figure 6: Typical Sink Stage Characteristics (Peak current and TAMB = 25 °C) 1400 1200 Idoutl(mA) 1000 800 Vgs=5V Vgs=chpum p 600 Vgs=12V 400 200 0 0 5 10 15 20 25 30 Vpoutl(V) 3.3 Recommendations The Sustain current must not be sunk in the power outputs to VPP when the power supply is applied. VSSSUB and VSSLOG must be connected close to the logical reference ground of the logic control signal buffers. 10/21 Electrical Characteristics STV7619DU 4 Electrical Characteristics 4.1 Absolute Maximum Ratings Symbol Parameter Value Units VCC Logic Supply -0.3, +7 V VDD Logic supply of power part -0.3, +14 V OUTi Output Pins -0.3, +120 V Logic Input Voltage -0.3, VCC +0.3 V VOUT Logic Output Voltage -0.3, VCC + 0.3 V VPOUT Driver Output Voltage (scanning mode) -0.3, +120 V VESD ESD Susceptibility (Human Body model: 100 pF capacitor discharged through 1.5 kΩ serial resistor) (See Note 1) ±2200 V IPOUT Driver Output Current (See Note 2, Note 5 and Note 6) -150 mA/+1.2 A IDOUT1 Diode Output Current (See Note 3 and Note 5) ±1 A IDOUT2 Diode Output Current (See Note 4 and Note 5) ±700 mA TJMAX Junction Temperature +150 °C TOPER Operating Temperature -20, +85 °C TSTG Storage Temperature -20, +150 °C VIN Note:1. All pins in relation to VCC = -1500V 2. Through one power output. 3. Through one diode 4. Through all power outputs (see test diagram): with power dissipation lower than or equal to Ptot and Junction temperature lower than or equal to Tjmax and VPP = VSSP. 5. These parameters are measured during ST’s internal qualification which includes temperature characterisation on standard batches and on corners batches of the process. These parameters are not tested on the parts. 6. For VDD = 9 V, IPOUT = 1.0 A, for VDD = 5 V, IPOUT = 0.5 A 11/21 STV7619DU 4.2 Electrical Characteristics Thermal Data Symbol Value Units Maximum Operating Junction 125 °C RthJA Junction-ambient Thermal Resistance (See Note 1) 20 °C/W RthJA Junction-ambient Thermal Resistance (See Note 2) 40 °C/W RthJA Junction-ambient Thermal Resistance (See Note 3) 29 °C/W TJOPER Parameter Note:1. For TQFP100 packaging with slug soldered on printed circuit board. 2. TQFP soldered on 4-layer printed circuit board. 3. For TQFP100 packaging with slug not soldered on printed circuit board. 4.3 Supply Characteristics (VSSP = 0 V, VSSLOG = 0 V, VSSSUB = 0 V, TAMB = 25°C and fCLK = 8 MHz, unless otherwise specified) Symbol Parameter Test Conditions Min. Typ. Max. Units 5 5.5 V VCC Logic Supply Voltage 4.5 VDD Logic Supply Voltage for Output Stage VCC 13 V VPP Power Output Supply Voltage 20 110 V 100 µA 2 mA ICCH Logic Supply Current ICCL Dynamic Logic Supply Current IPPH Power Output Supply Current (steady outputs) with VDD=5 or 12 V (ENABLE=L) with pump charge capacitor (ENABLE=H) 0.3 fCLK = 8 MHz TBD mA 100 µA 12/21 Electrical Characteristics 4.4 STV7619DU Power Output Characteristics Symbol VPOUTH VPOUTL Parameter Power Output High Level (Voltage drop versus VPP) Power Output Low Level voltage drop IPOUTL= +400 mA Power Output Low Level Peak current IPOULP VPOUTL=12 V (See Note 1) (Pulse ≤ 500ns) Test Conditions IPOUTH = - 60 mA TBD 4.2 Max. Units V 2.5 TBD V VDD=5V (ENABLE = L) 3.4 TBD V pump charge capacitor on VDD (ENABLE = H) 2.8 TBD V VDD=12 V (ENABLE = L) TBD 1100 mA VDD= 5V (ENABLE= L) TBD 530 mA pump charge capacitor on VDD (ENABLE = H) TBD 1000 mA Output Diode High Level (See Note 2 and Note 3) IDOUTH = +400 mA VDOUTL Output Diode Low Level (See Note 2 and Note 3) IDOUTL = - 400 mA Note:1. Peak current - Pulse mode 720 Hz - 0.2%. Duty cycle. 2. Compatible with power dissipation and TJOPER ≤ 125°C. 13/21 Typ. VDD=12V (ENABLE = L) VDOUTH 3. See Figure 8: Test Configuration on page 17. Min. 1.8 3.0 V -1.25 -3.00 V STV7619DU 4.5 Electrical Characteristics SOUT Characteristics Symbol Parameter Test Conditions VOH Logic Output High Level IOH = -1 mA VOL Logic Output Low Level IOL = +1 mA Min. Typ. 4.2 4.6 0.1 Max. Units V 0.4 V Input (CLK, STB, BLK, POC, SIN, CLR, F/R and ENABLE) Characteristics 4.6 Symbol Parameter VIH Input High Level VIL Input Low Level IIH High Level Input Current IIL IIL 4.7 Test Conditions Min. Typ. Max. 0.8 VCC Units V 0.2VCC V VIH = VCC ±10 µA Low Level Input Current for pins CLK, SIN, STB, CLR, BLK and POC VIL = 0 V ±10 µA Low Level Input Current for ENABLE pin VIL = 0 V -25 µA AC Timing Requirements VCC = 4.5 V to 5.5 V, TAMB = -20 to +85°C, max. leading/trailing edge for input signals (tr, tf) = 10 ns Symbol Parameter Min. Typ. Max. Units tWHCLK Duration of clock (CLK) pulse at high level 40 ns tWLCLK Duration of clock (CLK) pulse at low level 40 ns tSDAT Set-up Time of data input before clock (low to high) transition 10 ns tHDAT Hold Time of data input after clock (low to high) transition 20 ns tDSTB Minimum Delay to latch STB after clock (low to high) transition 25 ns tSSTB Set-up Time STB before clock (low to high) transition 10 ns tSTB Latch STB Low Level Pulse Duration 20 ns tBLK Blanking (BLK) Pulse Duration 100 ns 14/21 Electrical Characteristics 4.8 STV7619DU AC Timing Characteristics Symbol Parameter Min. Typ. Max. Units tCLK Data Clock Period tRDAT Logical Data Output Rise Time 25 tFDAT Logical Data Output Fall Time 15 tPHL1 Delay of logic data output (high to low transition) after clock (CLK) transition (CL=10pF) 45 tPLH1 Delay of logic data output (low to high transition) after clock (CLK) transition (CL=10 pF) 50 tPHL2 Delay of power output change (high to low transition) after clock (CLK) transition TBD 180 ns tPLH2 Delay of power output change (low to high transition) after clock (CLK) transition TBD 180 ns tPHL3 Delay of power output change (high to low transition) after Latch (STB) transition TBD 165 ns tPLH3 Delay of power output change (low to high transition) after Latch (STB) transition TBD 165 ns tPHL4 Delay of power output change (high to low transition) to POC transition 105 160 ns tPLH4 Delay of power output change (low to high transition) to POC transition 100 160 ns tROUT Power Output Rise Time (See Note 1) 100 ns tFOUT Power Output Fall Time (See Note 1) 30 ns 125 ns Note:1. One output among 64, loading capacitor COUT = 200 pF, other outputs at low or high level. 15/21 STV7619DU Electrical Characteristics Figure 7: AC Characteristics Waveform tCLK tWLCLK tWHCLK "1" CLK 50% 50% 50% "0" tSDAT tHDAT "1" 50% SIN 50% "0" tPHL1 tFDAT SOUT 10% 10% "1" 90% 90% 50% "0" tRDAT t PLH1 tSSTB tDSTB STB "1" STB 50% 50% "0" tPHL2 tPHL3 "1" OUTn 90% 90% 10% 10% "0" tPLH2 tPLH3 tBLK "1" POC 50% 50% "0" tPLH4 tPHL4 90% OUTn 10% "1" 90% 10% "0" tROUT tFOUT 16/21 Electrical Characteristics STV7619DU Figure 8: Test Configuration VPP=VSSP VPP=VSSP VDOUTH IDOUTH VDOUTL VSSP VSSP Output sinking current as positive value, sourcing current as negative value. 17/21 IDOUTL STV7619DU 5 Input/Output Schematic Diagrams Input/Output Schematic Diagrams Figure 9: ENABLE Input Figure 11: SIN, SOUT Input VCC VCC VCC VCC SIN, SOUT VCC ENABLE VSSLOG VSSLOG VSSLOG VSSLOG VSSLOG Figure 10: F/R, CLR, CLK, STB, BLK and POC Inputs VCC Figure 12: Power Outputs VCC VPP BLK, POC, F/R CLK, STB, CLR OUT1 to OUT64 VSSLOG VSSLOG VSSP 18/21 Package Mechanical Data 6 STV7619DU Package Mechanical Data Figure 13: TQFP100 Package D D1 D3 Seating Plane A A2 C A1 51 75 76 50 ccc C e H E3 E1 E S1 B 0.25mm .010 inch Gage Plane Pin 1 Identification 26 100 1 25 C K TQFP100M S L L1 Dimensions A A1 A2 B C D D1 D3 e E E1 E3 L L1 K H S S1 19/21 Millimeters Min. 0.05 1.35 0.17 0.09 0.45 8.80 8.80 Typ. 1.40 0.22 16.00 14.00 12.00 0.50 16.00 14.00 12.00 0.60 1.00 Inches Max. 1.60 0.15 1.45 0.27 0.20 0.75 Min. 0.002 0.053 0.007 0.004 0.018 0° (Min.), 7° (Max.) Slug Dimension For L/Frame Pad Size 10.00 x 10.00 mm 9.85 0.346 0.346 Typ. 0.055 0.009 0.630 0.551 0.472 0.20 0.630 0.551 0.472 0.024 0.039 0.388 Max. 0.063 0.006 0.057 0.011 0.008 0.030 STV7619DU 7 Revision History Revision History Table 8: Summary of Modifications Version Date Description Target Specification 1.0 April 2001 First version issued 1.1 April 2001 Corrections from the design 1.2 May 2001 Corrections in Table 1 and text added in Circuit description 1.3 May 2001 Inversion of BLK and POC pinsin block diagram and Table 1. Product Preview 2.0 September 2001 Pin connections - pins 30 to 50 corrected, Pin assignements: completed, Block diagram: voltage generator added, Circuit description: text modified, Application hints chapter added, Electrical characteristics: few precisions, Input/output schematics: corrections 2.1 October 2001 Pin connections - pins 38 added to pin description, Electrical characteristics: IIH and IIL, typical value is ±10, AC timing characteristics: tPHL4 and tPLH4: (BLK) replaced with (POC), Figure 5: AC characteristics waveform: STB and OUTn waveforms replaced, BLK renamed with POC. 2.2 November 2001 Page 10 - CVDD value replaced with 100 nF (1 previously), Page 11 - figure 3 - CVDD value replaced with 100 nF, Page 12 - Figure 4 replaced. Sentence modified in subsection 7.3 recommendations: the logical reference ground “of the application” replaced with “of the logic control signal buffers”. Page 13 - absolute maximum ratings - Ioutput value replaced with -150mA/ +1.2A. Note removed. Page 14- Electrical characteristics: values replaced. Page 15 - AC timing charactersitics: values replaced 2.3 January 2002 Electrical characteristics: First sentence: Vpp and Vdd removed, in the table: Vpp moved after Vdd. Preliminary Data 2.4 24 July 2002 2.5 13 January 2003 Reformatted datasheet. Deletion of STV7619U (Slug-up) device and related information. Modification of values in Note 6 on page 11. Addition of Note 3 on page 12. Update of typical values in Section 4. Addition of VESD information in Section 4.1: Absolute Maximum Ratings on page 11. Datasheet 3.0 August 2003 Published on internet. 20/21 STV7619DU Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics. © 2003 STMicroelectronics - All Rights Reserved Purchase of I2C Components of STMicroelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. 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