May 1994 54/74ETL16245 16-Bit Data Transceiver with Incident Wave Switching Y General Description Y The 54/74ETL16245 contains sixteen non-inverting bidirectional buffers with TRI-STATEÉ outputs designed with incident wave switching, live insertion support and enhanced noise margin for TTL backplane applications. Both the A and B ports include a bus hold circuit to latch the output to the value last forced on that pin. The B port of this device includes 25X series output resistors, which minimize undershoot and ringing. Features Y Y Y Y Y Y Y Y Y Supports the VME64 ETL specification Functionally and pin compatible with industry standard TTL 16245 SSOP pinout Logic Symbol Y Improved TTL-compatible input threshold range High drive TTL-compatible outputs (IOH e b60 mA, IOL e 90 mA) Supports 25X incident wave switching on the A port BiCMOS design significantly reduces power dissipation. Distributed VCC and GND pin configuration minimizes high-speed switching noise 25X series-dampening resistor on B-port Available in 48-pin SSOP and ceramic flatpak Guaranteed output skew Guaranteed simultaneous switching noise level and dynamic threshold performance Guaranteed latchup protection Connection Diagram Pin Assignment for SSOP and Flatpak TL/F/11654 – 1 Pin Description Pin Names DIR OE An Bn Description Transmit/Receive Input Output Enable Input (Active LOW) Backplane Bus Data Local Bus Data TL/F/11654 – 2 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/11654 RRD-B30M105/Printed in U. S. A. 54/74ETL16245 16-Bit Data Transceiver with Incident Wave Switching PRELIMINARY Functional Description Truth Table (Each 8-bit Section) The device uses byte-wide Direction (DIR) control and Output Enable (OE) controls. The DIR inputs determine the direction of data flow through the device. The OE inputs disable the A and the B ports. The part contains active circuitry which keeps all outputs disabled when VCC is less than 2.2V to aid in live insertion applications. Inputs Operation OE DIR L L H L H X A Data to B Bus B Data to A Bus Isolation Logic Diagrams (Positive Logic) TL/F/11654 – 4 TL/F/11654–3 ETL’s Improved Noise Immunity Incident Wave Switching TTL input thresholds are typically determined by temperature-dependent junction voltages which result in worst case input thresholds between 0.8V and 2.0V. By contrast, ETL provides greater noise immunity because its input thresholds are determined by current mode input circuits similar to those used for ECL or BTL. ETL’s worst case input thresholds, between 1.4V and 1.6V, are compensated for temperature, voltage and process variations. When TTL logic is used to drive fully loaded backplanes, the combination of low backplane bus characteristic impedance, wide TTL input threshold range and limited TTL drive generally require multiple waveform reflections before a valid signal can be received across the backplane. The VME International Trade Association (VITA) defined ETL to provide incident wave switching which increases the data transfer rate of a VME backplane and extends the life of VME applications. TTL compatibility with existing VME backplanes and modules was maintained. Improved Input Threshold Characteristics of ETL TL/F/11654–5 TL/F/11654 – 6 ABTC Worst Case VOUT – VIN ETL Worst Case VOUT –VIN 2 Incident Wave Switching (Continued) section at 1.2V for a falling edge and at 1.6V for a rising edge does not reach the worst case input threshold of a second ABTC circuit. This is shown in the two figures below. However, an ETL driver located at one end of the backplane is able to provide incident wave switching because it has a higher drive and a tighter input threshold. To demonstrate the incident wave switching capability, consider a VME application. A VME bus must be terminated to a 2.94V with 190X at each end of its 21 card backplane. The surge impedance presented by a fully loaded VME backplane is approximately 25X. If the output voltage/current of an ABTC driver is plotted with this load, the inter- Estimated ETL/ABTC Initial Falling Edge Step TL/F/11654 – 7 Because ETL has a much more precise input threshold region, an ETL receiver will interpret its predicted falling input of 0.85V as a logic ZERO and the initial rising edge of 1.9V as a logic ONE. This comparison is for the case of a 25X surge impedance backplane driven from one end. Estimated ETL/ABTC Initial Rising Edge Step TL/F/11654 – 8 The resulting ABTC and ETL waveform predictions and their input thresholds are compared below. This shows how ETL can achieve backplane speeds not always possible with conventional TTL compatible logic families. Comparing the Incident Wave Switching of ETL with ABTC TL/F/11654 – 9 3 Incident Wave Switching (Continued) The figure VCC Power-up Critical Voltages shows the relationship between OE and VCC while power is being applied and removed. TL/F/11654 – 10 VCC and OE Power-up Relationship 4 Absolute Maximum Ratings (Note 1) DC Latchup Source Current Over Voltage Latchup (I/O) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Ceramic Plastic VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Any Output in the Disabled or Power-off State in the HIGH State Current Applied to Output in LOW State (Max) b 500 mA 10V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. b 65§ C to a 150§ C b 55§ C to a 125§ C Recommended Operating Conditions b 55§ C to a 175§ C b 55§ C to a 150§ C Free Air Ambient Temperature Military Commercial Supply Voltage Military Commercial Minimum Input Edge Rate Data Input Enable Input b 0.5V to a 7.0V b 0.5V to a 7.0V b 50 mA to a 5.0 mA b 0.5V to 5.5V b 0.5V to VCC 128 mA b 55§ C to a 125§ C b 40§ C to a 85§ C a 4.5V to a 5.5V a 4.5V to a 5.5V (Dt/DV) 20 ns/V 50 ns/V DC Electrical Characteristics Symbol ETL16245 Parameter Min VIH VIL Input HIGH Voltage Input LOW Voltage VCD Input Clamp Diode Voltage VOH Output HIGH Voltage OE 2.0 Other Inputs 1.6 Typ Units Max OE 0.8 1.4 2.4 2.0 A Port 2.4 2.0 IHOLD Output LOW Voltage Recognized LOW Signal V b 1.2 V Min IIN e b18 mA (OEn, DIR) VCC b 1 V V V Min IOH e b100 mA IOH e b1 mA IOH e b12 mA V V V Min IOH e b1 mA IOH e b32 mA IOH e b60 mA VCC b 1 VOL B Port 0.4 0.8 V V Min IOL e 1 mA IOL e 12 mA A Port 0.55 0.9 V V Min IOL e 64 mA IOL e 90 mA Bus Hold Current A Port, B Port 100 mA Min Output Current, Power Down II Input Current Control Pins IIH a IOZH Output Leakage Current IIL a IOZL Output Leakage Current OE e HIGH, VO e 0.8V OE e HIGH, VO e 2.0V b 100 IOFF Conditions Recognized HIGH Signal V Other Inputs B Port VCC 100 mA 0.0 VCC Bias e 0V VI or VO s 4.5V 54ETL g 10 mA 5.5 VIN e 0 or VCC 74ETL g5 mA 5.5 VIN e 0 or VCC 50 mA 5.5 VOUT e 2.7V, OE e 2.0V b 50 mA 5.5 VOUT e 0.5V, OE e 2.0V 5 DC Electrical Characteristics Symbol (Continued) ETL16245 Parameter Units VCC Conditions 40 mA Max All Outputs HIGH, OE e LOW, DIR e HIGH or LOW 80 mA Max All Outputs LOW, OE e LOW, DIR e HIGH or LOW 40 mA Max OE e HIGH All Others at VCC or GND DIR e HIGH or LOW Dynamic ICC No Load (Note 1) 0.15 mA/ MHz Max Outputs Open OEn e GND, DIR e HIGH One Bit Toggling, 50% Duty Cycle VOLP Quiet Output Maximum Dynamic VOL 1.0 V VOLV Quiet Output Minimum Dynamic VOL VOHV Minimum High Level Dynamic Output Voltage (Note 1) VIHD Minimum High Level Dynamic Input Voltage (Note 1) VILD Maximum Low Level Dynamic Input Voltage (Note 1) Min ICCH Power Supply Current ICCL Power Supply Current ICCZ Power Supply Current ICCD Typ Max TA e 25§ C (Note 2) CL e 50 pF; RL e 500X V 5.0 TA e 25§ C (Note 2) CL e 50 pF; RL e 500X 2.7 V 5.0 TA e 25§ C (Note 4) CL e 50 pF; RL e 500X 1.5 V 5.0 TA e 25§ C (Note 3) CL e 50 pF; RL e 500X V 5.0 TA e 25§ C (Note 3) CL e 50 pF; RL e 500X b 1.4 2.0 5.0 1.2 0.8 Note 1: Guaranteed, but not tested. Note 2: Max. number of outputs defined as (n). n b 1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested. Note 3: Max. number of data inputs (n) switching. n b 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD). Guaranteed, but not tested. Note 4: Max. number of outputs defined as (n). n b 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested. AC Electrical Characteristics Symbol Parameter 74ETL 54ETL 74ETL TA e a 25§ C VCC e a 5V TA e b55§ C to a 125§ C VCC e 4.5V – 5.5V TA e b40§ C to a 85§ C VCC e 4.5V – 5.5V Min Min Max Propagation Delay An to Bn 1.5 1.5 7.0 7.0 1.5 1.5 7.0 7.0 ns 1, 2, 4 tPLH tPHL Propagation Delay Bn to An 1.5 1.5 7.0 7.0 1.5 1.5 7.0 7.0 ns 1, 2, 4 tPZH tPZL Output Enable Time 1.0 1.0 7.0 7.0 1.0 1.0 7.0 7.0 ns 1, 2, 3 tPHZ tPLZ Output Disable Time 1.0 1.0 7.0 7.0 1.0 1.0 7.0 7.0 ns 1, 2, 3 tr Rise Time 1V An Outputs 1.2 3.0 1.2 3.0 ns 1, 2, 4 tf Fall Time 2V An Outputs 1.2 3.0 1.2 3.0 ns 1, 2, 4 x 1V, Max Min 6 Max Fig. No. tPLH tPHL x 2V, Typ Units Skew Symbol Parameter 74ETL 54ETL TA e b40§ C to a 85§ C VCC e 4.5V – 5.5V 16 Outputs Switching TA e b55§ C to a 125§ C VCC e 4.5V – 5.5V 16 Outputs Switching Max Max Units Conditions tOHS (Notes 1, 2) Pin-to-Pin Skew LH/HL An to Bn 1.3 ns Figures 1, 2, 4 tOHS (Notes 1, 2) Pin-to-Pin Skew LH/HL Bn to An 1.3 ns Figures 1, 2, 4 tPS (Notes 1, 2) Duty Cycle Skew Bn to An 2.0 ns Figures 1, 2, 4 tPS (Notes 1, 2) Duty Cycle Skew An to Bn 2.0 ns Figures 1, 2, 4 VME Extended Skew Symbol Parameter 74ETL 54ETL TA e b40§ C to a 85§ C VCC e 4.5V – 5.5V TA e b55§ C to a 125§ C VCC e 4.5V – 5.5V 16 Outputs Switching 16 Outputs Switching Max Max Units Conditions tPV (Notes 1, 2) Device-to-Device Skew LH/HL Transitions Bn to An 4.0 ns Figures 1, 2, 4 tCP (Notes 1, 2) Device-to-Device Skew LH/HL Transitions An to Bn 2.5 ns Figures 1, 2, 4 tCP (Note 1, 3) Change in Propagation Delay with Load Bn to An 4.0 ns Figures 1, 2, 4 tCPV (Notes 1, 2, 3) Device-to-Device, Change in Propagation Delay with with Load Bn to An 6.0 ns Figures 1, 2, 4 Note 1: Skew is defined as the absolute difference in delay between two outputs. The specification applies to any outputs switching HIGH to LOW, LOW to HIGH, or any combination switching HIGH-to-LOW or LOW-to-HIGH. This specification is guaranteed but not tested. Note 2: This is measured with both devices at the same value of VCC g 1% and with package temperature differences of 20§ C from each other. Note 3: This is measured with Rx in Figure 1 at 13X for one unit and at 56X for the other unit. Capacitance Typ Max Units Conditions, TA e 25§ C CIN Input Capacitance 5 8 pF VCC e 0.0V (OEn, DIR) CI/O (Note 1) Output Capacitance 9 12 pF VCC e 5.0V (An) Symbol Parameter Note 1: CI/O is measured at frequency f e 1 MHz, per MIL-STD-883B, Method 3012. 7 AC Loading Test Port SW1 SW2 tPHZ, tPLZ A, B a7 Open tPZH, tPZL A, B a7 Open tPLH, tPHL A Open Closed tPLH, tPHL B Open Open tr, tf A Open Closed 26 tPV A Open Closed 26 FIGURE 1. Standard AC Test Load tCP B Open Open Note 1: Defined to emulate the range of VME bus transmission line loading as a function of board population and driver location. Rx e 13X, 26X or 56X depending on test. tCP A Open Closed 13 then 56 tCPV A Open Closed 13 and 56 TL/F/11654 – 11 *Includes jig and probe capacitance Rx 26 FIGURE 1a TL/F/11654 – 13 FIGURE 3. TRI-STATE Output HIGH and LOW Enable and Disable Times TL/F/11654 – 12 FIGURE 2. Input Pulse Requirements Amplitude Rep. Rate tw tr tf 3.0V 1 MHz 500 ns 2.5 ns 2.5 ns FIGURE 2a. Test Input Signal Requirements TL/F/11654 – 14 FIGURE 4. Rise, Fall Time and Propagation Delay Waveforms 8 Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows: 54/74 ETL16245 SS C X Temperature Range Family VME74 e Commercial VME54 e Military Special Variations X e Devices shipped in 13× reels QB e Military grade device with environmental and burn-in processing shipped in tubes. Device Type Package Code SS e Small Outline (SSOP) FPFP e Fine Pitch Flatpak Temperature Range C e Commercial (b40§ C to a 85§ C) M e Military (b55§ C to a 125§ C) Physical Dimensions inches (millimeters) 48-Lead SSOP (0.300× Wide) (SS) NS Package Number MS48A 9 54/74ETL16245 16-Bit Data Transceiver with Incident Wave Switching Physical Dimensions inches (millimeters) (Continued) 48-Pin Ceramic Flatpak (FPFP) NS Package Number WA48A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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