TPS3610U18, TPS3610T50 BATTERY-BACKUP SUPERVISORS FOR RAM RETENTION SLVS327 – DECEMBER 2000 features typical applications D D D D D D D D D D D D D D D D D D D D D D Supply Current of 40 µA (Max) Battery Supply Current of 20 nA (Max) Precision Supply-Voltage Monitor, 1.8 V, 5 V; Other Options on Request Watchdog Timer With 800-ms Time-Out Backup-Battery Voltage can Exceed VDD Power-On Reset Generator With Fixed 100-ms Reset Delay Time Battery-OK Output Voltage Monitor for Power-Fail or Low-Battery Monitoring Manual Switchover to Battery-Backup Mode Chip-Enable Gating . . . 3 ns (at VDD = 5 V) Max Propagation Delay Battery-Freshness Seal 14-pin TSSOP Package Temperature Range . . . –40°C to 85°C Fax Machines Set-Top Boxes Advanced Voice Mail Systems Portable Battery-Powered Equipment Computer Equipment Advanced Modems Automotive Systems Portable Long-Time Monitoring Equipment Point of Sale Equipment PW PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 OUT VDD GND MSWITCH CEIN BATTON PFI – 14 13 12 11 10 9 8 VBAT RESET WDI LOWLINE CEOUT BATTOK PFO typical operating circuit Address Decoder Power Supply 0.1 µF External Source CEIN Rx VDD VBAT TPS3610 PFI Backup Battery MR WDI I/O I/O BATTOK I/O MSWITCH V OUT GND 8 RESET PFO BATTON CE CMOS RAM VCC Address Bus uC RESET Ry Manual Reset CEOUT CE CMOS RAM VCC RealTime Clock VCC 8 Data Bus 16 I/O Switchover Capacitor 0.1 µF VCC GND Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TPS3610U18, TPS3610T50 BATTERY-BACKUP SUPERVISORS FOR RAM RETENTION SLVS327 – DECEMBER 2000 description The TPS3610 family of supervisory circuits monitors and controls processor activity by providing backup-battery switchover for data retention of CMOS RAM. Other features include an additional power-fail comparator, low-line indication, watchdog function, battery-status indicator, manual switchover, and write protection for CMOS RAM. The TPS3610 family allow usage of 3-V or 3.6-V lithium batteries as the backup supply in systems with, e.g., VDD = 1.8 V. During power-on, RESET is asserted when the supply voltage (VDD or VBAT) becomes higher than 1.1 V. Thereafter, the supply-voltage supervisor monitors VDD and keeps RESET output active as long as VDD remains below the threshold voltage VIT. An internal timer delays the return of the output to the inactive state (high) to ensure proper system reset. The delay time starts after VDD has risen above the threshold voltage VIT. When the supply voltage drops below the threshold voltage VIT, the output becomes active (low) again. The product spectrum is designed for supply voltages of 1.8 V and 5 V. The circuits are available in a 14-pin TSSOP package. TPS3610 devices are characterized for operation over a temperature range of –40°C to 85°C. standard and application-specific versions TPS3610U 18 PW R Standard Versions Tape and Reel TI Package Designator Nominal Supply Voltage Nominal Battok Threshold Voltage TA TPS3610U18PWR –40°C to 85°C APPLICATION-SPECIFIC VERSIONS, NOMINAL SUPPLY VOLTAGE TA –40°C 40°C to 85°C 85 C NOMINAL SUPPLY VOLTAGE, VDD(NOM) (V) PACKAGED DEVICES TSSOP (PW)† 1.8 TPS3610x18PWR 2.5 TPS3610x25PWR 3 TPS3610x30PWR 3.3 TPS3610x33PWR PACKAGED DEVICES TPS3610T50PWR APPLICATION-SPECIFIC VERSIONS, BATTOK SUPPLY VOLTAGE TA –40°C 40°C to 85°C 5 NOMINAL BATTOK THRESHOLD VOLTAGE‡, VIT(BOK) (V) PACKAGED DEVICES TSSOP (PW)† 2.4 TPS3610TXxPWR 1.6 TPS3610UXXPWR TPS3610x50PWR † The PW package is only available taped and reeled (indicated by the R suffix on the device type). ‡ Application specific versions for the BATTOK threshold voltage can be manufactured in the range from 1.5 V to 4.8 V in 50-mV steps. NOTE: For the application specific versions, contact your local TI sales office for availability and order lead time. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS3610U18, TPS3610T50 BATTERY-BACKUP SUPERVISORS FOR RAM RETENTION SLVS327 – DECEMBER 2000 TRUTH TABLES OUTPUTS INPUTS VDD > VLL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VDD > VIT 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VDD > VBAT 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 MSWITCH CEIN OUT BATTON LOWLINE RESET CEOUT 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VBAT VBAT VBAT VBAT VDD VDD VBAT VBAT VDD VDD VBAT VBAT VDD VDD VBAT VBAT VDD VDD VBAT VBAT VDD VDD VBAT VBAT 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DIS DIS DIS DIS DIS DIS DIS DIS 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 BATTOK VBAT > VBOK 0 1 POWER-FAIL BATTOK PFI > VPFI PFO 0 1 0 1 0 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 COND.: VDD > VDD min 3 TPS3610U18, TPS3610T50 BATTERY-BACKUP SUPERVISORS FOR RAM RETENTION SLVS327 – DECEMBER 2000 functional block diagram MSWITCH VBAT + _ Switch Control OUT VDD BATTON + _ Reference Voltage of 1.15 V _ + GND BATTOK RESET Logic + Timer RESET + _ LOWLINE Oscillator _ WDI PFO + PFI Transition Detector Watchdog Logic + Control VO 40 kΩ CEOUT CEIN timing diagram 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS3610U18, TPS3610T50 BATTERY-BACKUP SUPERVISORS FOR RAM RETENTION SLVS327 – DECEMBER 2000 Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION BATTOK 9 O Battery status output BATTON 6 O Logic output/external bypass switch driver output CEIN 5 I Chip-enable input CEOUT 10 O Chip-enable output GND 3 I Ground LOWLINE 11 O Early power-fail warning output MSWITCH 4 I Manual switch to force device into battery-backup mode OUT 1 O Supply output PFI 7 I Power-fail comparator input PFO 8 O Power-fail comparator output RESET 13 O Active-low reset output VBAT VDD 14 I Backup-battery input 2 I Input supply voltage WDI 12 I Watchdog timer input detailed description battery freshness seal The battery freshness seal of the TPS3610 family disconnects the backup battery from internal circuitry until it is needed. This function ensures that the backup battery connected to VBAT will be fresh when the final product is put to use. The following steps explain how to enable the freshness seal mode: 1. Connect VBAT (VBAT > VBATmin or VDDmin) 2. Ground PFO 3. Connect PFI to VDD (PFI = VDD) 4. Connect VDD to power supply (VDD > VIT) and keep connected for 5 ms < t < 35 ms The battery freshness seal mode is disabled by the positive-going edge of RESET when VDD is applied. BATTOK output BATTOK is a logic feedback of the device to indicate the status of the backup battery. The supervisor checks the battery voltage every 200 ms with a voltage divider load of approximately 100 kΩ and a measurement cycle on-time of 25 µs. The measurement cycle starts after the reset is released. If the battery voltage VBAT is below the negative-going threshold voltage VIT(BOK), the indicator BATTOK does a high-to-low transition. Otherwise it retains its status to VOUT level. I 25 µs 200 ms 100 µA t Figure 1. BATTOK Timing POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TPS3610U18, TPS3610T50 BATTERY-BACKUP SUPERVISORS FOR RAM RETENTION SLVS327 – DECEMBER 2000 detailed description (continued) chip-enable signal gating The internal gating of chip-enable, CE, signals prevents erroneous data from corrupting CMOS RAM during an undervoltage condition. The TPS3610 use a series transmission gate from CEIN to CEOUT. During normal operation (reset not asserted), the CE transmission gate is enabled and passes all CE transitions. When reset is asserted, this path becomes disabled, preventing erroneous data from corrupting the CMOS RAM. The short CE propagation delay from CEIN to CEOUT enables TPS3610 devices to be used with most processors. The CE transmission gate is disabled and CEIN is high-impedance (disable mode) while reset is asserted. During a power-down sequence, when VDD crosses the reset threshold, the CE transmission gate will be disabled and CEIN immediately becomes high impedance if the voltage at CEIN is high. If CEIN is low while reset is asserted, the CE transmission gate will be disabled at the same time CEIN goes high, or 10 µs after rest asserts, whichever occurs first. This will allow the current write cycle to complete during power-down. When the CE transmission gate is enabled, the impedance of CEIN appears as a 50-Ω resistor in series with the load at CEOUT. To achieve minimum propagation delay, the capacitive load at CEOUT should be minimized, and a low-output-impedance driver should be used. During disable mode, the transmission gate is off and an active pull-up connects CEOUT to OUT. The pullup turns off when the transmission gate is enabled. VDD VBAT V(BOK) V(SWP) V(SWN) VIT 1.1 V VDD VBAT CEIN V(BOK) V(SWP) V(SWN) VIT 10 µs COUT RESET td 10 µs td V(SWN) VIT Undefined Behavior Figure 2. Chip-Enable Timing 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 td TPS3610U18, TPS3610T50 BATTERY-BACKUP SUPERVISORS FOR RAM RETENTION SLVS327 – DECEMBER 2000 detailed description (continued) VDD VDD VBAT 3.6 V TPS3610 25-Ω Equivalent Source Impedance 50-Ω Cable CEIN 50 Ω 50 Ω CEOUT GND CL† 50 pF † Includes load capacitance and scope-probe capacitance. Figure 3. CE Propagation Delay Test Circuit power-fail comparator (PFI and PFO) An additional comparator is provided to monitor voltages other than the nominal supply voltage. The power-fail-input (PFI) will be compared with an internal voltage reference of 1.15 V. If the input voltage falls below the power-fail threshold VIT(PFI) of typical 1.15 V, the power-fail output (PFO) goes low. If VIT(PFI) goes above 1.15 V, plus about 20-mV hysteresis, the output returns to high. By connecting two external resistors, it is possible to supervise any voltages above 1.15 V. The sum of both resistors should be about 1 MΩ, to minimize power consumption and also to guarantee that the current in the PFI pin can be neglected compared with the current through the resistor network. The tolerance of the external resistors should be not more than 1% to ensure minimal variation of sensed voltage. If the power-fail comparator is unused, PFI should be connected to ground and PFO left unconnected. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TPS3610U18, TPS3610T50 BATTERY-BACKUP SUPERVISORS FOR RAM RETENTION SLVS327 – DECEMBER 2000 detailed description (continued) LOWLINE The lowline comparator monitors VDD with a threshold voltage typically 2% above the reset threshold (VIT). For normal operation (VDD above the reset threshold), LOWLINE is pulled to VDD. LOWLINE can be used to provide a nonmaskable interrupt (NMI) to the processor when power begins to fall. In most battery-operated portable systems, reserve energy in the battery provides enough time to complete the shutdown routine once the low-line warning is encountered and before reset asserts. If the system must also contend with a more rapid VDD fall time, such as when the main battery is disconnected or a high-side switch is opened during normal operation, a capacitor can be used on the VDD line to provide enough time for executing the shutdown routine. First of all, the worst-case settling time (tsd) required for the system to perform its shutdown routine needs to be defined. Now, using the worst-case load current (IL) that can be drained from the capacitor, and the minimum reset threshold voltage (VITmin), the capacitor value (CH) can be calculated as follows: CH +V I L t sd 0.012 ITmin BATTON Most often BATTON is used as a gate or base drive for an external pass transistor for high-current applications. In addition it can be used as a logic output to indicate the battery switchover status. BATTON is high when OUT is connected to VBAT. BATTON can be connected directly to the base of a PNP transistor (see Figure 4a) or to the gate of a PMOS transistor (see Figure 4b). No current-limiting resistor is required, but a resistor connecting the base of the PNP to BATTON can be used to limit the current drawn from VDD—prolonging battery life in portable equipment. However, if a PMOS transistor is used, it must be connected in the reverse of the traditional method (see Figure 4b), which orients the body diode from VDD to VOUT and prevents the backup battery from discharging through the FET when its gate is high. PMOS FET Body Diode 3 V or 3.3 V To CMOS RAM D S G VDD BATTON VO VDD BATTON VO TPS3610 TPS3610 GND GND (a) (b) Figure 4. Driving an External Transistor With BATTON 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS3610U18, TPS3610T50 BATTERY-BACKUP SUPERVISORS FOR RAM RETENTION SLVS327 – DECEMBER 2000 detailed description (continued) backup-battery switchover In case of a brownout or power failure, it may be necessary to preserve the contents of RAM. If a backup battery is installed at VBAT, the device automatically switches the connected RAM to backup power when VDD fails. In order to allow the backup battery (e.g., a 3.6-V lithium cell) to have a higher voltage than VDD, these supervisors will not connect VBAT to OUT when VBAT is greater than VDD. VBAT only connects to OUT (through a 20-Ω switch) when VDD falls below VIT and VBAT is greater than VDD. When VDD recovers, switchover is deferred either until VDD crosses VBAT, or until VDD rises above the reset threshold VIT. OUT will connect to VDD through a 1-Ω (max) PMOS switch when VDD crosses the reset threshold. VDD – Normal Supply Voltage – V FUNCTION TABLE VDD > VBAT 1 VDD > VIT 1 1 0 0 1 0 0 VDD Mode OUT VDD VDD VDD VBAT VIT Hysteresis VBAT Mode VBSW Hysteresis Undefined VBAT – Backup-Battery Supply Voltage – V Figure 5. Normal Supply Voltage vs Backup-Battery Supply Voltage POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TPS3610U18, TPS3610T50 BATTERY-BACKUP SUPERVISORS FOR RAM RETENTION SLVS327 – DECEMBER 2000 detailed description (continued) manual switchover (MSWITCH) While operating in the normal mode from VDD, the device can be forced manually to operate in battery-backup mode by connecting MSWITCH to VDD. Refer to Table 1 for different switchover modes. Table 1. Switchover Modes MSWITCH GND VDD mode Battery backup mode Battery-backup VDD GND VDD STATUS VDD mode Switch to battery-backup mode Battery-backup mode Battery-backup mode If the manual switchover feature is not used, MSWITCH must be connected to ground. watchdog In a microprocessor- or DSP-based system, it is important not only to supervise the supply voltage, but also to ensure correct program execution. The task of a watchdog is to ensure that the program is not stalled in an indefinite loop. The microprocessor, microcontroller or DSP has to toggle the watchdog input within typically 0.8 s to avoid the occurence of a time-out. Either a low-to-high or a high-to-low transition resets the internal watchdog timer. If the input is unconnected, the watchdog is disabled and will be retriggered internally. saving current while using the watchdog The watchdog input is internally driven low during the first 7/8 of the watchdog time-out period, then the input momentarily pulses high, resetting the watchdog counter. For minimum watchdog input current (minimum overall power consumption), WDI should be left low for the majority of the watchdog time-out period, and pulsed low-high-low once within 7/8 of the watchdog time-out period to reset the watchdog timer. If instead WDI is externally driven high for the majority of the timeout period, a current of, e.g., 5 V/40 kΩ ≈ 125 µA, can flow into WDI. VDD VIT VBAT WDI Time-Out RESET td td Figure 6. Watchdog Timing 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS3610U18, TPS3610T50 BATTERY-BACKUP SUPERVISORS FOR RAM RETENTION SLVS327 – DECEMBER 2000 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage, VDD (see Note1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V All other pins (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V Continuous output current at OUT, IO(OUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 mA Continuous output current (all other pins) IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to GND. For reliable operation the device must not be operated at 7 V for more than t=1000h continuously. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING PW 700 mW 5.6 mW/°C 448 mW 364 mW recommended operating conditions Supply voltage, VDD Battery supply voltage, VBAT Input voltage, VI High-level input voltage, VIH MIN MAX 1.65 5.5 V 1.5 5.5 V 0 VDD+0.3 V 0.7xVDD Low-level input voltage, VIL V 0.3×VDD 300 Continuous output current at OUT, IO(OUT) Input transition rise and fall rate at WDI, MSWITCH, ∆t/∆V Slew rate at VDD or VBAT Operating free-air temperature range, TA –40 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT V mA 100 ns/V 1 V/µs 85 °C 11 TPS3610U18, TPS3610T50 BATTERY-BACKUP SUPERVISORS FOR RAM RETENTION SLVS327 – DECEMBER 2000 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL High-level out output ut voltage Low-level output voltage TEST CONDITIONS VOUT Battery backup mode Battery-backup MAX RESET, RESET BATTOK VDD–0.2 V VO(OUT) = 1.8 V, VO(OUT) = 3.3 V, VO(OUT) = 5 V, IOH = –400 µA IOH = –2 mA, IOH = –3 mA VOUT–0.2 V BATTON LOWLINE, LOWLINE PFO VDD = 1.8 V, VDD = 3.3 V, VDD = 5 V, IOH = –20 µA IOH = –80 µA, IOH = –120 µA VDD–0.3 V CEOUT, Enable mode, CEIN = VOUT VO(OUT) = 1.8 V, VO(OUT) = 3.3 V, VO(OUT) = 5 V, IOH = –1 mA IOH = –2 mA, IOH = –5 mA VOUT–0.2 V CEOUT, Enable mode VO(OUT) = 3.3 V, IOH = –0.5 mA VOUT–0.4 V RESET, PFO, BATTOK, LOWLINE VDD = 1.8 V, VDD = 3.3 V, VDD = 5 V, IOL = 400 µA IOH = 2 mA, IOH = 3 mA 0.2 VO(OUT) = 1.8 V, VO(OUT) = 3.3 V, VO(OUT) = 5 V, IOH = 500 µA IOH = 3 mA, IOH = 5 mA 0.2 BATTON CEOUT, Enable mode, CEIN = 0 V VO(OUT) = 1.8 V, VO(OUT) = 3.3 V, VO(OUT) = 5 V, IOH = 1 mA IOH = 2 mA IOH = 5 mA 0.2 VDD = 0 V to 5.5 V, OR VBAT = 0 V, to 5.5 V, IOL = 20 µA IO(OUT) = 8.5 mA, VBAT = 0 V VBAT > 1.1 V, OR VDD > 1.1 V, IO(OUT) = 125 mA, VBAT = 0 V VDD = 3.3 V, IO(OUT) = 200 mA, VBAT = 0 V VDD = 5 V, IO(OUT) = 0.5 mA, VBAT = 1.5 V VDD = 0 V, VDD = 1.8 V, IO(OUT) = 7.5 mA, VDD = 0 V, VBAT = 3.3 V NOTE 2: The lowest supply voltage at which RESET becomes active. tr, VDD ≥ 15 µs/V 12 TYP IOH = –400 µA IOH = –2 mA, IOH = –3 mA Power-up reset voltage (see Note 2) Normal mode MIN VDD = 1.8 V, VDD = 3.3 V, VDD = 5 V, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT VDD–0.4 V VOUT–0.4 V V VDD–0.4 V VOUT–0.3 V 0.4 0.4 V 0.3 0.4 V VDD–50 mV VDD–150 mV VDD–200 mV VBAT–20 mV VBAT–113 mV V TPS3610U18, TPS3610T50 BATTERY-BACKUP SUPERVISORS FOR RAM RETENTION SLVS327 – DECEMBER 2000 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) PARAMETER VIT Negative going Negative-going input threshold voltage l ( (see N Note 3)) MIN TYP MAX TPS3610x18 TEST CONDITIONS 1.68 1.71 1.74 TPS3610x25 2.21 2.25 2.30 TPS3610x30 2.59 2.63 2.69 TPS3610x33 2.88 2.93 3 4.46 4.55 4.64 PFI 1.13 1.15 1.17 TPS3610Txx 2.33 2.4 2.47 TPS3610Uxx 1.55 1.6 1.65 VIT+1.2% VIT+2% 20 VIT+2.8% TPS3610x50 VIT(PFI) VIT(BOK) VIT(LL) TA = –40°C 40°C to 85°C LOWLINE 1.65 V < VIT < 2.5 V VIT LOWLINE Vhys Hysteresis BATTOK 2.5 V < VIT < 3.5 V 40 3.5 V < VIT < 5.5 V 60 1.65 V < VLL < 2.5 V 20 2.5 V < VLL < 3.5 V 40 3.5 V < VLL < 5.5 V 60 1.65 V < VBOK < 2.5 V 20 2.5 V < VBOK < 3.5 V 40 3.5 V < VIBOK< 5.5 V 60 PFI IIH IIL High-level input current II Input current PFI, MSWITCH IOS Short-circuit output current PFO WDI (see Note 4) IDD Supply Su ly current at VDD IBAT Supply Su ly current (see Figure 2) at VBAT Ilkg V V mV 12 VBSW (see Note 5) Low-level input current UNIT VDD = 1.8 V 55 WDI = VDD = 5 V WDI = 0 V, 150 VDD = 5 V –150 –25 PFO = 0 V 25 VDD = 1.8 V VDD = 3.3 V –0.3 VDD = 5 V –2.4 –1.1 VO(OUT) = VDD 40 VO(OUT) = VBAT 40 VO(OUT) = VDD –0.1 0.1 VO(OUT) = VBAT 0.5 Leakage current at CEIN Disable mode ±1 rDS(on) DS( ) VDD to OUT on-resistance VBAT to OUT on-resistance VDD = 5 V VBAT = 3.3 V Ci Input capacitance 0.6 1 8 15 µA nA mA µA µA µA Ω VI = 0 V to 5 V 5 pF NOTES: 3. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 µF) should be placed near to the supply terminals. 4. For details on how to optimize current consumption when using WDI. Refer to detailed description section, watchdog. 5. For VDD < 1.6 V, VO(OUT) switches to VBAT regardless of VBAT timing requirements at RL = 1 MΩ, CL = 50 pF, TA = –40°C to 85°C PARAMETER tw Pulse width TEST CONDITIONS At VDD At WDI VIH = VIT + 0.2 V, VIL = VIT –0.2 V VDD = VIT + 0.2 V, VIL = 0.3 × VDD, VIH = 0.7 × VDD POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MIN TYP MAX UNIT 6 µs 100 ns 13 TPS3610U18, TPS3610T50 BATTERY-BACKUP SUPERVISORS FOR RAM RETENTION SLVS327 – DECEMBER 2000 switching characteristics at RL = 1 MΩ, CL = 50 pF, TA =–40°C to 85°C PARAMETER td TEST CONDITIONS Delay time VDD > VIT +0.2 V (see timing diagram Watchdog timeout tPLH Propagation (delay) time, low-tohigh-level output tPHL tt Pro agation (delay) time, Propagation time high-tolow-level output Transition time VDD to RESET VDD = 5 V VIL = VIT–0.2 V, VIH = VIT+0.2 V PFI to PFO VIL = VPFI–0.2 V, VIH = VPFI+0.2 V VDD to BATTON VIH = VBAT + 200 mV, VIL = VBAT – 200 mV, VBAT = VIT POST OFFICE BOX 655303 MAX UNIT 100 140 ms 0.48 0.8 1.12 s VDD = 1.8 V VDD = 3.3 V NOTE 6: Specified by design 14 TYP 60 µs 15 50% RESET to 50% CEOUT 50% CEIN to 50% CEOUT, CL = 50 pF only (see Figure 4 and Note 6) MIN • DALLAS, TEXAS 75265 15 5 ns 3 2 5 3 5 µs 3 µs TPS3610U18, TPS3610T50 BATTERY-BACKUP SUPERVISORS FOR RAM RETENTION SLVS327 – DECEMBER 2000 MECHANICAL DATA PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 2000, Texas Instruments Incorporated