TI TPS3613

SLVS340B – DECEMBER 2000 – REVISED DECEMBER 2002
D Supply Current of 40 µA (Max)
D Battery Supply Current of 100 nA (Max)
D Supply Voltage Supervision Range:
D
D
D
D
D
D
typical applications
D
D
D
D
D
D
D
D
D
– Adjustable
– Other Versions Available on Request
Backup-Battery Voltage Can Exceed VDD
Power-On Reset Generator With Fixed
100-ms Reset Delay Time
Active-High and Active-Low Reset Output
Chip-Enable Gating . . . 3 ns (at VDD = 5 V)
Max Propagation Delay
10-Pin MSOP Package
Temperature Range . . . –40°C to 85°C
Fax Machines
Set-Top Boxes
Advanced Voice Mail Systems
Portable Battery Powered Equipment
Computer Equipment
Advanced Modems
Automotive Systems
Portable Long-Time Monitoring Equipment
Point-of-Sale Equipment
MSOP (DGS) Package
(TOP VIEW)
description
VOUT
VDD
GND
MR
CEIN
The TPS3613-01 supervisory circuit monitors
and controls processor activity by providing
backup-battery switchover for data retention of
CMOS RAM.
VBAT
RESET
SENSE
RESET
CEOUT
ACTUAL SIZE
3,05 mm x 4,98 mm
During power on, RESET is asserted when the supply voltage (VDD or VBAT) becomes higher than 1.1 V.
Thereafter, the supply voltage supervisor monitors VDD and keeps RESET output active as long as VDD remains
below the threshold voltage VIT. An internal timer delays the return of the output to the inactive state (high) to
ensure proper system reset. The delay time starts after VDD has risen above the threshold voltage VIT.
When the supply voltage drops below the threshold voltage VIT, the output becomes active (low) again.
The TPS3613-01 is available in a 10-pin MSOP package and is characterized for operation over a temperature
range of –40°C to 85°C.
typical operating circuit
Address
Decoder
Power
Supply
0.1 µF
Monitored
Voltage
CEIN
Rx
CEOUT
VDD
VBAT
CE
CMOS
RAM
VCC
Address Bus
Backup
Battery
uC
SENSE
8
RESET
RESET
Ry
CE
CMOS
RAM
VCC
RealTime
Clock
VCC
8
Data Bus
16
TPS3613
MR
Switchover
Capacitor
Manual
Reset
VOUT
GND
0.1 µF
VCC
GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2002, Texas Instruments Incorporated
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1
SLVS340B – DECEMBER 2000 – REVISED DECEMBER 2002
PACKAGE INFORMATION
DEVICE NAME
TPS3613–01DGSR†
TA
–40°C to 85°C
MARKING
AFK
† The DGSR passive indicates tape and reel of 2500 parts.
ordering information application specific versions
TPS361
3 – 01
DGS
R
NOMINAL VOLTAGE‡, VNOM
DEVICE NAME
Adjustable
TPS3613–01 DGS
‡ For other threshold voltages, contact the local TI sales office
for availability and lead-time.
Reel
Package
Nominal Supply Voltage
Functionality
Family
FUNCTION TABLE
SENSE > VIT
2
MR
CEIN
0
VDD > VBAT
0
0
0
VOUT
VBAT
RESET
RESET
CEOUT
0
1
DIS
0
0
0
1
0
0
1
0
VBAT
VBAT
0
1
DIS
0
1
DIS
0
0
1
1
0
1
0
0
VBAT
VDD
0
1
DIS
0
1
0
1
0
1
DIS
VDD
VDD
0
1
DIS
0
1
1
0
0
1
1
1
0
1
DIS
VDD
VDD
0
1
DIS
1
0
0
0
1
0
0
1
0
1
DIS
VDD
VDD
0
1
1
0
1
0
DIS
1
0
DIS
1
0
1
1
1
1
0
0
VDD
VDD
1
0
EN
0
1
DIS
1
1
0
1
0
1
DIS
0
VDD
VDD
1
1
1
1
1
1
1
0
DIS
1
VDD
1
0
EN
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SLVS340B – DECEMBER 2000 – REVISED DECEMBER 2002
functional schematic
TPS3613
VBAT
+
_
Switch
Control
VOUT
VDD
R
RESET
Logic
+
Timer
MR
+
_
SENSE
Reference
Voltage
or 1.15 V
RESET
RESET
VOUT
CEOUT
CEIN
timing diagram
VBAT
VDD
VIT
t
VOUT
t
RESET
td
td
t
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3
SLVS340B – DECEMBER 2000 – REVISED DECEMBER 2002
Terminal Functions
TERMINAL
NAME
I/O
DESCRIPTION
NO.
CEIN
5
I
Chip-enable input
CEOUT
6
O
Chip-enable output
GND
3
I
Ground
MR
4
I
Manual reset input
RESET
7
O
Active-high reset output
RESET
9
O
Active-low reset output
SENSE
8
I
Adjustable sense input
VBAT
10
I
Backup-battery input
VDD
VOUT
2
I
Input supply voltage
1
O
Supply output
detailed description
backup-battery switchover
VDD – Normal Supply Voltage
In case of a brownout or power failure, it may be necessary to preserve the contents of RAM. If a backup battery
is installed at VBAT, the device automatically switches the connected RAM to backup power when VDD fails. In
order to allow the backup battery (e.g., 3.6-V lithium cells) to have a higher voltage than VDD, these supervisors
do not connect VBAT to VOUT when VBAT is greater than VDD. VBAT only connects to VOUT (through a 15-Ω switch)
when VDD falls below VIT and VBAT is greater than VDD. When VDD recovers, switchover is deferred either until
VDD crosses VBAT, or when VDD rises above the reset threshold VIT. VOUT connects to VDD through a 1-Ω (max)
PMOS switch when VDD crosses the reset threshold.
VDD>VBAT
1
VDD>VIT
1
VOUT
VDD
1
0
0
1
VDD
VDD
0
0
VBAT
VDD – Mode
VIT Hysteresis
VBAT – Mode
VBSW Hysteresis
Undefined
VBAT – Backup-Battery Supply Voltage
Figure 1. VDD – VBAT Switchover
4
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SLVS340B – DECEMBER 2000 – REVISED DECEMBER 2002
detailed description (continued)
chip-enable signal gating
The internal gating of chip-enable (CE) signals prevents erroneous data from corrupting CMOS RAM during
an under-voltage condition. The TPS3613 use a series transmission gate from CEIN to CEOUT. During normal
operation (reset not asserted), the CE transmission gate is enabled and passes all CE transitions. When reset
is asserted, this path becomes disabled, preventing erroneous data from corrupting the CMOS RAM. The short
CE propagation delay from CEIN to CEOUT enables the TPS3613 device to be used with most processors.
The CE transmission gate is disabled and CEIN is high impedance (disable mode) while reset is asserted.
During a power-down sequence when VDD crosses the reset threshold, the CE transmission gate is disabled
and CEIN immediately becomes high impedance if the voltage at CEIN is high. If CEIN is low when reset is
asserted, the CE transmission gate is disabled when CEIN goes high, or 15 µs after reset asserts, whichever
occurs first. This allows the current write cycle to complete during power down. When the CE transmission gate
is enabled, the impedance of CEIN appears as a resistor in series with the load at CEOUT. The overall device
propagation delay through the CE transmission gate depends on VOUT, the source impedance of the drive
connected to CEIN, and the load at CEOUT. To achieve minimum propagation delay, the capacitive load at
CEOUT should be minimized, and a low-output-impedance driver is used.
In the disabled mode, the transmission gate is off and an active pullup connects CEOUT to VOUT. This pullup
turns off when the transmission gate is enabled.
CEIN
t
CEOUT
15 µs
t
RESET
t
Figure 2. Chip-Enable Timing
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5
SLVS340B – DECEMBER 2000 – REVISED DECEMBER 2002
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage: VDD (see Note1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
MR and SENSE pins (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to (VDD + 0.3 V)
Continuous output current at VOUT: IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 mA
All other pins, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND. For reliable operation the device must not be operated at 7 V for more than t=1000h
continuously.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
DGS
424 mW
3.4 mW/°C
271 mW
220 mW
recommended operating conditions
Supply voltage, VDD
Battery supply voltage, VBAT
Input voltage, VI
MIN
MAX
UNIT
1.65
5.5
V
1.5
5.5
V
VDD + 0.3
V
0
High-level input voltage, VIH
0.7 x VDD
Low-level input voltage, VIL
V
0.3 x VDD
V
Continuous output current at VOUT, IO
300
mA
Input transition rise and fall rate at MR, ∆t/∆V
100
ns/V
1
V/µs
85
°C
Slew rate at VDD or Vbat
Operating free-air temperature range, TA
6
–40
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SLVS340B – DECEMBER 2000 – REVISED DECEMBER 2002
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VDD = 1.8 V IOH = –400 µA
VDD = 3.3 V, IOH = –2 mA
VDD = 5 V,
IOH = –3 mA
VDD = 1.8 V, IOH = –20 µA
RESET
RESET
VOH
VOUT = 3.3 V, IOH = –2 mA
VOUT = 5 V, IOH = –5 mA
VOUT – 0.3 V
CEOUT
Disable mode
VOUT = 3.3 V, IOH = –0.5 mA
VOUT – 0.4 V
RESET
CEOUT
Enable mode
CEIN = 0 V
Vres
Power-up reset voltage (see Note 2)
Normal mode
VOUT
Battery backup mode
Battery-backup
RDS(on)
DS( )
VDD to VOUT on-resistance
VBAT to VOUT on-resistance
VIT
Negative-going input threshold voltage
(see Note 3)
Vhys
h
Hysteresis
IIH
IIL
High-level input current
II
Input current
Low-level input current
IDD
VDD supply current
IBAT
VBAT supply current
VDD – 0.4 V
V
VOUT – 0.2 V
IOL = 400 µA
IOL = 2 mA
IOL = 3 mA
IOL = 1.0 mA
0.2
0.4
0.2
VOUT = 3.3 V, IOL = 2 mA
VOUT = 5 V, IOL = 5 mA
VDD > 1.1 V or VBAT > 1.1 V,
IOL = 20 µA
IO = 8.5 mA,
VDD = 1.8 V, VBAT = 0 V
IO = 125 mA,
VDD = 3.3 V, VBAT = 0 V
IO = 200 mA,
VDD = 5 V,
VBAT = 0 V
IO = 0.5 mA,
VBAT = 1.5 V, VDD = 0 V
IO = 7.5 mA,
VBAT = 3.3 V, VDD = 0 V
0.4
VDD – 150 mV
VDD – 200 mV
V
VBAT – 20 mV
VBAT – 113 mV
1.13
0.6
1
8
15
1.15
1.17
Sense
1.1 V < VIT < 1.65 V
12
VDD = 1.8 V
MR = 0.7 x VDD, VDD = 5 V
55
SENSE
VDD = 5 V
VDD = 1.15 V
VOUT = VDD
VOUT = VBAT
VOUT = VDD
VOUT = VBAT
Disable mode,
V
VDD – 50 mV
VDD = 5 V
VBAT = 3.3 V
MR = 0 V,
V
0.3
VBSW (see Note 4)
MR
UNIT
VDD – 0.3 V
Enable mode
CEIN = VOUT
VDD = 1.8 V,
VDD = 3.3 V,
VDD = 5 V,
VOUT = 1.8 V,
MAX
VDD – 0.4 V
CEOUT
High-level
High
level output
out ut voltage
Low level output voltage
Low-level
TYP
VDD = 3.3 V,
VDD = 5 V,
VOUT = 1.8 V,
RESET
VOL
IOH = –80 µA
IOH = –120 µA
IOH = –1 mA
MIN
VDD – 0.2 V
Ω
V
mV
–33
–76
–110
–255
–25
25
nA
40
µA
40
–0.1
0.1
0.5
µA
µA
VI < VDD
±1
µA
VI = 0 V to 5 V
5
pF
NOTES: 2. The lowest supply voltage at which RESET becomes active. tr,(VDD) ≥ 15 µs/V.
3. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 µF) should be placed near to the supply terminals.
4. For VDD < 1.6 V, VOUT switches to VBAT regardless of VBAT
Ilkg
Ci
CEIN leakage current
Input capacitance
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SLVS340B – DECEMBER 2000 – REVISED DECEMBER 2002
timing requirements at RL = 1 MΩ, CL = 50 pF, TA = –40°C to 85°C
PARAMETER
tw
Pulse width
TEST CONDITIONS
SENSE
VIH = VIT + 0.2 V,
VIL = VIT – 0.2 V
MIN
TYP
MAX
UNIT
µs
6
switching characteristics at RL = 1 MΩ, CL= 50 pF, TA = –40°C to 85°C
PARAMETER
td
Delay time
tPLH
Propagation (delay) time,
low-to-high-level output
TEST CONDITIONS
VSENSE ≥ VIT + 0.2 V,
MR ≥ 0.7 x VDD,
See timing diagram
50% RESET to 50% CEOUT
50% CEIN tto 50% CEOUT
CEOUT,
CL = 50 pF only (see Note 5)
tPHL
Propagation (delay) time,
high-to-low-level output
SENSE to RESET
MR to RESET
Transition time
VDD to VBAT
VOUT = VIT
VDD = 1.8 V
VDD = 3.3 V
VDD = 5 V
VIL = VIT – 0.2 V,
VIH = VIT + 0.2 V
VSENSE ≥ VIT + 0.2 V,
VIL = 0.3 x VDD,
VIH = 0.7 x VDD
VIH = VBAT + 0.2 V,
VIL = VBAT – 0.2 V,
VBAT < VIT
NOTE 5: Assured by design
8
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MIN
60
TYP
100
MAX
140
15
UNIT
ms
µs
5
15
1.6
5
1
3
2
5
0.1
1
ns
µs
µs
3
µs
SLVS340B – DECEMBER 2000 – REVISED DECEMBER 2002
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
rDS(on)
IDD
VIT
Static drain-source on-state resistance (VDD to VOUT)
vs Output current
3
Static drain-source on-state resistance (VBAT to VOUT)
vs Output current
4
Static drain-source on-state resistance (CEIN to CEOUT)
vs Input voltage at CEIN
5
Supply current
vs Supply voltage
6
Input threshold voltage at RESET
vs Free-air temperature
7
High-level output voltage at RESET
r DS(on)
10, 11, 12,
13
Low-level output voltage at RESET
vs Low-level output current
14, 15
Low-level output voltage at CEOUT
vs Low-level output current
16, 17
High-level output voltage at CEOUT
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
(VDD to VOUT)
vs
OUTPUT CURRENT
1000
VDD = 3.3 V
VBAT = GND
900
TA = 85°C
800
TA = 25°C
700
TA = 0°C
TA = –40°C
600
500
50
75
100
125
150
175
200
– Static Drain-Source On-State Resistance – Ω
– Static Drain-Source On-State Resistance – mΩ
VOL
8, 9
vs High-level output current
rDS(on)
VOH
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
(VBAT to VOUT)
vs
OUTPUT CURRENT
20
VBAT = 3.3 V
17.5
15
TA = 85°C
12.5
TA = 25°C
TA = 0°C
10
7.5
5
2.5
TA = –40°C
4.5
IO – Output Current – mA
6.5
8.5
10.5
12.5
IO – Output Current – mA
14.5
Figure 4
Figure 3
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9
SLVS340B – DECEMBER 2000 – REVISED DECEMBER 2002
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
(CEIN to CEOUT)
vs
INPUT VOLTAGE AT CEIN
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
40
30
35
TA = 85°C
25
20
TA = 0°C
15
TA = –40°C
10
ICEOUT = 5 mA
VDD = 5 V
5
1
2
3
4
VI(CEIN) – Input Voltage at CEIN – V
20
TA = 25°C
TA = –40°C
10
0
5
0
1
2
3
4
VDD – Supply Voltage – V
Figure 6
INPUT THRESHOLD VOLTAGE AT RESET
vs
FREE-AIR TEMPERATURE
1.001
VIT – Input Threshold Voltage at RESET – V
TA = 0°C
TA = 85°C
15
Figure 5
1
0.999
0.998
0.997
0.996
0.995
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80
TA – Free-Air Temperature – °C
Figure 7
10
VDD Mode
VBAT = GND
or
5
0
0
VBAT Mode
VBAT = 2.6 V
25
TA = 25°C
30
I DD – Supply Current – µ A
rDS(on) – Static Drain Source On-State Resistance
(CEIN to CEOUT) – Ω
TYPICAL CHARACTERISTICS
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5
6
SLVS340B – DECEMBER 2000 – REVISED DECEMBER 2002
TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE AT RESET
vs
HIGH-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE AT RESET
vs
HIGH-LEVEL OUTPUT CURRENT
5.1
VDD = 5 V
VBAT = GND
VOH – High-Level Output Voltage at RESET – V
VOH – High-Level Output Voltage at RESET – V
6
5
TA = –40°C
TA = 25°C
4
TA = 0°C
3
2
TA = 85°C
1
0
–35
–30
–25
–20
–15
–10
–5
IOH – High-Level Output Current – mA
Expanded View
5
TA = –40°C
4.9
TA = 25°C
TA = 0°C
4.8
4.7
TA = 85°C
4.6
VDD = 5 V
VBAT = GND
4.5
–5 –4.5
0
Figure 9
HIGH-LEVEL OUTPUT VOLTAGE AT CEOUT
vs
HIGH-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE AT CEOUT
vs
HIGH-LEVEL OUTPUT CURRENT
3.5
3.35
V(CEIN)= 3.3 V
VDD = 5 V
Enable Mode
3
TA = –40°C
2.5
TA = 25°C
TA = 0°C
1.5
1
TA = 85°C
0.5
0
–150 –130 –110 –90
–70
–50 –30
–10
IOH – High-Level Output Current – mA
VOH – High-Level Output Voltage at CEOUT – V
VOH – High-Level Output Voltage at CEOUT – V
0
IOH – High-Level Output Current – mA
Figure 8
2
–4 –3.5 –3 –2.5 –2 –1.5 –1 –0.5
V(CEIN) = 3.3 V
VDD = 5 V
Expanded View
Enable Mode
3.30
TA = –40°C
3.25
TA = 25°C
TA = 0°C
3.20
TA = 85°C
3.15
3.10
–5 –4.5 –4 –3.5 –3 –2.5 –2 –1.5 –1 –0.5
IOH – High-Level Output Current – mA
Figure 10
0
Figure 11
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11
SLVS340B – DECEMBER 2000 – REVISED DECEMBER 2002
TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE AT CEOUT
vs
HIGH-LEVEL OUTPUT CURRENT
3.5
3.5
3
VOH – High-Level Output Voltage at CEOUT – V
VOH – High-Level Output Voltage at CEOUT – V
HIGH-LEVEL OUTPUT VOLTAGE AT CEOUT
vs
HIGH-LEVEL OUTPUT CURRENT
TA = –40°C
2.5
TA = 25°C
TA = 0°C
2
1.5
TA = 85°C
1
Disable Mode
V(CEIN) = Open
VDD = 1.65 V
0.5
0
–4.5 –4 –3.5
–3 –2.5
–2 –1.5
–1
–0.5
3.4
V(CEIN) = Open
VDD = 1.65 V
3.3
TA = –40°C
3.2
TA = 25°C
TA = 0°C
3.1
TA = 85°C
3
2.9
2.8
2.7
–1 –0.9 –0.8 –0.7 –0.6 –0.5 –0.4 –0.3 –0.2 –0.1
IOH – High-Level Output Current – mA
Figure 12
Figure 13
LOW-LEVEL OUTPUT VOLTAGE AT RESET
vs
LOW-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE AT RESET
vs
LOW-LEVEL OUTPUT CURRENT
500
3.5
VOL – Low-Level Output Voltage at RESET – mV
VOL – Low-Level Output Voltage at RESET – V
0
0
IOH – High-Level Output Current – mA
VDD = 3.3 V
VBAT = GND
3
2.5
TA = 0°C
2
TA = 25°C
1.5
TA = 85°C
1
TA = –40°C
0.5
0
0
5
10
15
20
IOL – Low-Level Output Current – mA
25
Expanded View
TA = 85°C
VDD = 3.3 V
VBAT = GND
400
TA = 25°C
300
TA = 0°C
200
TA = –40°C
100
0
0
1
2
3
4
IOL – Low-Level Output Current – mA
Figure 14
12
Expanded View
Disable Mode
Figure 15
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SLVS340B – DECEMBER 2000 – REVISED DECEMBER 2002
TYPICAL CHARACTERISTICS
LOW-LEVEL OUTPUT VOLTAGE AT CEOUT
vs
LOW-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE AT CEOUT
vs
LOW-LEVEL OUTPUT CURRENT
VOL– Low-Level Output Voltage at CEOUT – mV
VOL– Low-Level Output Voltage at CEOUT – V
3.5
Enable Mode
V(CEIN) = GND
VDD = 5 V
3
2.5
TA = 85°C
2
TA = 25°C
TA = 0°C
1.5
TA = –40°C
1
0.5
140
V(CEIN) = GND
VDD = 5 V
Enable Mode
Expanded View
120
TA = 85°C
100
TA = 25°C
80
TA = 0°C
60
TA = –40°C
40
20
0
0
0
10 20 30 40 50 60 70 80 90
IOL – Low-Level Output Current – mA
100
0
1
2
3
4
5
IOL – Low-Level Output Current – mA
Figure 16
Figure 17
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13
SLVS340B – DECEMBER 2000 – REVISED DECEMBER 2002
MECHANICAL DATA
DGS (S-PDSO-G10)
PLASTIC SMALL-OUTLINE PACKAGE
0,27
0,17
0,50
10
0,25 M
6
0,15 NOM
3,05
2,95
4,98
4,78
Gage Plane
0,25
1
0°–ā6°
5
3,05
2,95
0,69
0,41
Seating Plane
1,07 MAX
0,15
0,05
0,10
4073272/A 03/98
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
14
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