WS512K16-XXX 512Kx16 SRAM MODULE ADVANCED* FEATURES ■ Access Times 17, 20, 25, 35ns ■ MIL-STD-883 Compliant Devices Available ■ Packaging •44 pin Ceramic SOJ (Package 102) • 44 lead Ceramic Flatpack (Package 209) ■ Organized as two banks of 256Kx16 ■ Data I/O Compatible with 3.3V devices ■ 2V Minimum Data Retention for battery back up operation ■ Commercial, Industrial and Military Temperature Range ■ 5 Volt Power Supply (3.3V parts also available) ■ Low Power CMOS ■ TTL Compatible Inputs and Outputs ■ Data Byte Control: * Lower Byte (LB) = I/O1-8 This data sheet describes a product that may or may not be under development and is subject to change or cancellation without notice. Upper Byte (UB) = I/O9-16 PIN DESCRIPTION 44 CSOJ 44 FLATPACK TOP VIEW A0 A1 A2 A3 A4 CS1 I/O1 I/O2 I/O3 I/O4 VCC GND I/O5 I/O6 I/O7 I/O8 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A17 A16 A15 OE UB LB I/O16 I/O15 I/O14 I/O13 GND VCC I/O12 I/O11 I/O10 I/O9 CS2 A14 A13 A12 A11 A10 A0-17 Address Inputs LB Lower-Byte Control (I/O1-8) UB Upper-Byte Control (I/O9-16) I/O1-16 Data Input/Output CS1-2 Chip Select OE Output Enable WE Write Enable VCC +5.0V Power GND Ground NC No Connection BLOCK DIAGRAM A0-17 WE OE UB LB 256K x 16 256K x 16 CS1 CS2 I/O1-16 April 1998 1 White Microelectronics • Phoenix, AZ • (602) 437-1520 SRAM MONOLITHICS PIN CONFIGURATION FOR WS512K16-XXX 3 WS512K16-XXX TRUTH TABLE CS1 3 CS2 H L H L H H H L H L H L L H H L L H WE OE LB UB X X X X H H X X X X H H H L L X L H L L H L H L L H L L Mode SRAM MONOLITHICS Operating Temperature Storage Temperature Signal Voltage Relative to GND Junction Temperature Supply Voltage Symbol Min TA Not Select Standby Output Disable High Z High Z Active Data Out High Z Data Out Data In High Z Data In High Z Data Out Data Out High Z Data In Data In Read Write TSTG VG +150 -0.5 -0.5 Active Symbol Min Max Unit °C Supply Voltage VCC 4.5 5.5 V °C Input High Voltage VIH 2.2 V CC + 0.3 V V Input Low Voltage VIL -0.3 +0.8 V Operating Temp. (Mil.) TA -55 +125 °C Vcc+0.5 TJ VCC Parameter Unit +125 -65 Active RECOMMENDED OPERATING CONDITIONS Max -55 Power I/O9-16 High Z ABSOLUTE MAXIMUM RATINGS Parameter Data I/O I/O1-8 High Z 150 °C 7.0 V CAPACITANCE (TA = +25°C) Parameter Symbol Condition Input capacitance CIN VIN = 0V, f = 1.0MHz Max Unit 25 pF Output capicitance COUT VOUT = 0V, f = 1.0MHz 25 pF This parameter is guaranteed by design but not tested. DC CHARACTERISTICS (VCC = 5.0V, GND = 0V, TA = -55°C to +125°C) Parameter Sym Conditions Units Min Max 10 µA Input Leakage Current ILI VCC = 5.5, VIN = GND to VCC Output Leakage Current ILO CS = VIH, OE = VIH, VOUT = GND to VCC 10 µA Operating Supply Current ICC CS = VIL, OE = VIH, f = 5MHz, Vcc = 5.5 290 mA Standby Current ISB CS = VIH, OE = VIH, f = 5MHz, Vcc = 5.5 30 mA Output Low Voltage VOL IOL = 8mA, VCC = 4.5 0.4 V Output High Voltage VOH IOH = -4.0mA, VCC = 4.5 2.4 V NOTE: DC test conditions: VIH = VCC -0.3V, VIL = 0.3V DATA RETENTION CHARACTERISTICS (TA = -55°C to +125°C) Parameter Symbol Conditions Units Min V DR CS ≥ V CC -0.2V I CCDR1 V CC = 3V Data Retention Supply Voltage Data Retention Current * Also available in Low Power version. Please call factory for informaion. White Microelectronics • Phoenix, AZ • (602) 437-1520 2 Typ Max 5.5 V 2.0 12.0* mA 2.0 WS512K16-XXX AC CHARACTERISTICS (VCC = 5.0V, GND = 0V, TA = -55°C to +125°C) Parameter Symbol Read Cycle -17 Min Read Cycle Time t RC Address Access Time t AA Output Hold from Address Change t OH Chip Select Access Time t ACS -20 Max Min 17 -25 Max Min 20 25 17 0 ns 35 ns 35 ns 20 ns 0 20 ns 25 Output Enable to Output Valid t OE Chip Select to Output in Low Z t CLZ 1 2 5 5 5 Output Enable to Output in Low Z t OLZ 1 0 0 0 0 Chip Disable to Output in High Z t CHZ 1 9 10 12 15 ns Output Disable to Output in High Z t OHZ 1 9 10 12 15 ns 17 ns 15 ns t BA LB, UB Enable to Low Z Output t BLZ 1 LB, UB Disable to High Z Output t BHZ 1 12 10 15 12 0 ns 14 0 0 9 ns 0 10 ns 12 1. This parameter is guaranteed by design but not tested. AC CHARACTERISTICS (VCC = 5.0V, GND = 0V, TA = -55°C to +125°C) Parameter Symbol Write Cycle -17 Min -20 Max Min -25 Max Min -35 Max Min Units Max Write Cycle Time t WC 17 20 25 35 ns Chip Select to End of Write t CW 14 17 20 25 ns Address Valid to End of Write t AW 14 17 20 25 ns Data Valid to End of Write t DW 10 12 15 20 ns Write Pulse Width t WP 14 17 20 25 ns Address Setup Time t AS 0 0 0 0 ns Address Hold Time t AH 0 0 0 0 ns Output Active from End of Write t OW 1 0 0 0 0 Write Enable to Output in High Z t WHZ 1 9 10 ns 10 15 ns Data Hold Time t DH 0 0 0 0 ns LB, UB Valid to End of Write t BW 14 17 20 25 ns 1. This parameter is guaranteed by design but not tested. AC TEST CIRCUIT AC TEST CONDITIONS I OL Parameter Current Source VZ D.U.T. ≈ 1.5V (Bipolar Supply) C eff = 50 pf I OH Current Source 3 Typ Unit Input Pulse Levels VIL = 0, VIH = 3.0 V Input Rise and Fall 5 ns Input and Output Reference Level 1.5 V Output Timing Reference Level 1.5 V NOTES: V Z is programmable from -2V to +7V. IOL & I OH programmable from 0 to 16mA. Tester Impedance Z0 = 75 Ω. V Z is typically the midpoint of VOH and V OL. IOL & I OH are adjusted to simulate a typical resistive load circuit. ATE tester includes jig capacitance. White Microelectronics • Phoenix, AZ • (602) 437-1520 3 SRAM MONOLITHICS LB, UB Access Time 10 Units Max 25 0 17 Min 35 20 0 -35 Max WS512K16-XXX TIMING WAVEFORM - READ CYCLE tRC ADDRESS tAA CS tACS tCHZ tBA tBLZ tCLZ tBHZ LB, UB tRC ADDRESS tAA OE tOH 3 DATA I/O tOE tOLZ PREVIOUS DATA VALID DATA VALID tOHZ DATA I/O DATA VALID HIGH IMPEDANCE SRAM MONOLITHICS READ CYCLE 1 (CS = OE = VIL, UB or LB = VIL, WE = VIH) READ CYCLE 2 (WE = VIH) WRITE CYCLE - WE CONTROLLED tWC ADDRESS tAW tAH tCW CS tBW LB, UB tAS tWP WE tOW tWHZ tDW DATA I/O tDH DATA VALID WRITE CYCLE 1, WE CONTROLLED WRITE CYCLE - CS CONTROLLED WRITE CYCLE - LB, UB CONTROLLED tWC tWC ADDRESS ADDRESS tAS tAW WS32K32-XHX t tAH tCW tAS CS AW tAH tCW CS tBW tBW LB, UB LB, UB tWP tWP WE WE tDW DATA I/O tDH tDW DATA I/O DATA VALID WRITE CYCLE 2, CS CONTROLLED White Microelectronics • Phoenix, AZ • (602) 437-1520 DATA VALID WRITE CYCLE 3, LB, UB CONTROLLED 4 tDH WS512K16-XXX PACKAGE 102: 44 LEAD, CERAMIC SOJ 28.70 (1.13) ± 0.25 (0.010) 3.96 (0.156) MAX 0.89 (0.035) Radius TYP 0.2 (0.008) ± 0.05 (0.002) 11.3 (0.446) ± 0.2 (0.009) 9.55 (0.376) ± 0.25 (0.010) 1.27 (0.050) ± 0.25 (0.010) 3 1.27 (0.050) TYP 26.7 (1.050) TYP ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES PACKAGE 209: 44 LEAD, CERAMIC FLAT PACK 28.45 (1.120) ± 0.26 (0.010) PIN 1 IDENTIFIER 3.18 (0.125) MAX 12.95 (0.510) ± 0.13 (0.005) 9.90 (0.390) ± 0.13 (0.005) 10.16 (0.400) ± 0.51 (0.020) 0.43 (0.017) ± 0.05 (0.002) 0.13 (0.005) ± 0.05 (0.002) 1.27 (0.050) TYP 26.67 (1.050) TYP ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES 5 White Microelectronics • Phoenix, AZ • (602) 437-1520 SRAM MONOLITHICS PIN 1 IDENTIFIER WS512K16-XXX ORDERING INFORMATION W S 512K16 - XX X X X LEAD FINISH: Blank = Gold plated leads A = Solder dip leads DEVICE GRADE: 3 M = Military Screened -55°C to +125°C I = Industrial -40°C to +85°C C = Commercial 0°C to +70°C PACKAGE: SRAM MONOLITHICS DL = 44 Lead Ceramic SOJ (Package 102) FL = 44 Lead Ceramic Flatpack (Package 209) ACCESS TIME (ns) ORGANIZATION, two banks of 256K x 16 SRAM WHITE MICROELECTRONICS White Microelectronics • Phoenix, AZ • (602) 437-1520 6