NTHS5445T1 Power MOSFET P-Channel ChipFET 5.2 Amps, 8 Volts Features • Low RDS(on) for Higher Efficiency • Logic Level Gate Drive • Miniature ChipFET Surface Mount Package Saves Board Space http://onsemi.com 5.2 AMPS 8 VOLTS RDS(on) = 35 m Applications • Power Management in Portable and Battery–Powered Products; i.e., Cellular and Cordless Telephones and PCMCIA Cards S MAXIMUM RATINGS (TA = 25°C unless otherwise noted) Rating Symbol 5 secs G Steady State Unit Drain–Source Voltage VDS –8.0 V Gate–Source Voltage VGS 8.0 V Continuous Drain Current (TJ = 150°C) (Note 1.) TA = 25°C TA = 85°C ID IS Maximum Power Dissipation (Note 1.) TA = 25°C TA = 85°C PD –2.1 A –1.1 A W 2.5 1.3 TJ, Tstg 5.2 3.7 20 IDM Continuous Source Current (Note 1.) Operating Junction and Storage Temperature Range P–Channel MOSFET 7.1 5.2 Pulsed Drain Current D A ChipFET CASE 1206A STYLE 1 1.3 0.7 °C –55 to +150 1. Surface Mounted on 1″ x 1″ FR4 Board. MARKING DIAGRAM PIN CONNECTIONS 8 1 D 1 8 D 7 2 D 2 7 D 6 3 D 3 6 S 5 4 G 4 5 A5 D A5 = Specific Device Code ORDERING INFORMATION Semiconductor Components Industries, LLC, 2001 October, 2001 – Rev. 5 1 Device Package Shipping NTHS5445T1 ChipFET 3000/Tape & Reel Publication Order Number: NTHS5445T1/D NTHS5445T1 THERMAL CHARACTERISTICS Characteristic Symbol Maximum Junction–to–Ambient (Note 2.) t 5 sec Steady State RthJA Maximum Junction–to–Foot (Drain) Steady State RthJF Typ Max 40 80 50 95 15 20 Unit °C/W °C/W ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Test Condition Min Typ Max Unit VGS(th) VDS = VGS, ID = –250 µA –0.45 – – V Gate–Body Leakage IGSS VDS = 0 V, VGS = 8.0 V – – 100 nA Zero Gate Voltage Drain Current IDSS VDS = –6.4 V, VGS = 0 V – – –1.0 µA VDS = –6.4 V, VGS = 0 V, TJ = 85°C – – –5.0 ID(on) VDS –5.0 V, VGS = –4.5 V –20 – – A rDS(on) ( ) VGS = –4.5 V, ID = –5.2 A – 0.030 0.035 Ω VGS = –2.5 V, ID = –4.5 A – 0.040 0.047 VGS = –1.8 V, ID = –2.0 A – 0.052 0.062 gfs VDS = –5.0 V, ID = –5.2 A – 18 – S VSD IS = –1.1 A, VGS = 0 V – –0.8 –1.2 V – 17 26 nC Static Gate Threshold Voltage On–State Drain Current (Note 3.) Drain–Source On–State Resistance (Note 3.) Forward Transconductance (Note 3.) Diode Forward Voltage (Note 3.) Dynamic (Note 4.) Total Gate Charge Qg 40V 45V VDS = –4.0 V, VGS = –4.5 V, ID = –5.2 A Gate–Source Charge Qgs – 2.8 – Gate–Drain Charge Qgd – 2.6 – Turn–On Delay Time td(on) – 15 25 – 45 70 – 110 165 – 65 100 – 30 60 Rise Time Turn–Off Delay Time tr td(off) Fall Time tf Source–Drain Reverse Recovery Time trr VDD = –4.0 V, RL = 4 Ω ID –1.0 –1 0 A, A VGEN = –4 –4.5 5V V, RG = 6 Ω IF = –1.1 A, di/dt = 100 A/µs 2. Surface Mounted on 1″ x 1″ FR4 Board. 3. Pulse Test: Pulse Width 300 µs, Duty Cycle 2%. 4. Guaranteed by design, not subject to production testing. http://onsemi.com 2 ns NTHS5445T1 TYPICAL ELECTRICAL CHARACTERISTICS 20 20 VGS = 5 thru 2.5 V TC = –55°C 16 2V ID,Drain Current (A) ID,Drain Current (A) 16 12 8 1.5 V 4 25°C 125°C 12 8 4 1V 0 0 0.5 1.0 1.5 2.0 2.5 VDS, Drain–to–Source Voltage (V) 0 3.0 0 0.5 1.0 1.5 2.0 VGS, Gate–to–Source Voltage (V) Figure 1. Output Characteristics Figure 2. Transfer Characteristics 3000 0.08 2500 VGS = 1.8 V C, Capacitance (pF) r DS(on),On–Resistance ( Ω ) 0.10 0.06 VGS = 2.5 V 0.04 VGS = 4.5 V 0.02 Ciss 2000 1500 Coss 1000 500 Crss 0 0 0 4 8 12 ID, Drain Current (A) 16 0 20 2 4 6 VDS, Drain–to–Source Voltage (V) Figure 3. On–Resistance vs. Drain Current 1.6 r DS(on),On–Resistance ( Ω ) (Normalized) VGS,Gate–to–Source Voltage (V) 8 Figure 4. Capacitance 5 VDS = 4 V ID = 5.2 A 4 3 2 1 0 2.5 0 4 8 12 Qg, Total Gate Charge (nC) 16 1.4 1.2 1.0 0.8 0.6 –50 20 VGS = 4.5 V ID = 5.2 A Figure 5. Gate Charge –25 0 25 50 75 100 TJ, Junction Temperature (°C) 125 Figure 6. On–Resistance vs. Junction Temperature http://onsemi.com 3 150 NTHS5445T1 TYPICAL ELECTRICAL CHARACTERISTICS 0.10 rDS(on),On–Resistance ( Ω ) 20 TJ = 150°C I S,Source Current (A) 10 TJ = 25°C 1 0.08 0.04 0.02 0 0 0.2 0.4 0.6 0.8 1.0 VDS, Drain–to–Source Voltage (V) ID = 5.2 A 0.06 1.2 0 Figure 7. Source–Drain Diode Forward Voltage 1 2 3 4 VGS, Gate–to–Source Voltage (V) 5 Figure 8. On–Resistance vs. Gate–to–Source Voltage 50 0.4 0.3 40 V GS (th),Varience (V) ID = 250 µA Power (W) 0.2 0.1 30 20 0.0 10 –0.1 –0.2 –50 –25 0 25 50 75 100 TJ, Temperature (°C) 125 0 10–3 150 Figure 9. Threshold Voltage 10–2 10 –1 1 Time (sec) 10 100 Figure 10. Single Pulse Power http://onsemi.com 4 600 NTHS5445T1 TYPICAL ELECTRICAL CHARACTERISTICS Normalized Effective Transient Thermal Impedance 2 1 Duty Cycle = 0.5 Notes: 0.2 PDM t1 0.1 t2 0.1 t1 1. Duty Cycle, D = t 2 2. Per Unit Base = RthJA = 80°C/W 3. TJM – TA = PDMZthJA(t) 4. Surface Mounted 0.05 0.02 Single Pulse 0.01 10–4 10–3 10–2 10 –1 1 Square Wave Pulse Duration (sec) 10 100 600 Figure 11. Normalized Thermal Transient Impedance, Junction–to–Ambient Normalized Effective Transient Thermal Impedance 2 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 10–4 10–3 10–2 10 –1 Square Wave Pulse Duration (sec) 1 Figure 12. Normalized Thermal Transient Impedance, Junction–to–Foot http://onsemi.com 5 10 NTHS5445T1 PACKAGE DIMENSIONS CHIPFET CASE 1206A–01 ISSUE A A 8 7 M 6 K 5 S 5 6 7 8 4 3 2 1 B 1 2 3 L 4 D NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE. 4. LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTAL AND VERTICAL SHALL NOT EXCEED 0.08 MM. 5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS. 6. NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD SURFACE. J G STYLE 1: PIN 1. 2. 3. 4. 5. 6. 7. 8. C 0.05 (0.002) DRAIN DRAIN DRAIN GATE SOURCE DRAIN DRAIN DRAIN http://onsemi.com 6 DIM A B C D G J K L M S MILLIMETERS MIN MAX 2.95 3.10 1.55 1.70 1.00 1.10 0.25 0.35 0.65 BSC 0.10 0.15 0.30 0.45 0.55 BSC 5 ° NOM --1.80 INCHES MIN MAX 0.116 0.122 0.061 0.067 0.039 0.043 0.010 0.014 0.025 BSC 0.004 0.008 0.012 0.018 0.022 BSC 5 ° NOM --0.071 NTHS5445T1 80 mil 80 mil 18 mil 25 mil 68 mil 26 mil 28 mil 26 mil Figure 13. 28 mil Figure 14. BASIC PAD PATTERNS confines of the basic footprint. The drain copper area is 0.0054 sq. in. (or 3.51 sq. mm). This will assist the power dissipation path away from the device (through the copper leadframe) and into the board and exterior chassis (if applicable) for the single device. The addition of a further copper area and/or the addition of vias to other board layers will enhance the performance still further. The basic pad layout with dimensions is shown in Figure 14. This is sufficient for low power dissipation MOSFET applications, but power semiconductor performance requires a greater copper pad area, particularly for the drain leads. The minimum recommended pad pattern shown in Figure 13 improves the thermal area of the drain connections (pins 1, 2, 3, 6, 7, 8) while remaining within the http://onsemi.com 7 NTHS5445T1 ChipFET is a trademark of Vishay Siliconix ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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