ETC PI74ALVCH162601A

PI74ALVCH162601
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18-Bit Universal Bus Transceiver
with 3-State Outputs
Product Features
Product Description
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Pericom Semiconductor’s PI74ALVCH series of logic circuits are
produced in the Company’s advanced 0.5 micron CMOS technology,
achieving industry leading speed.
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PI74ALVCH162601 is designed for low voltage operation
VCC = 2.3V to 3.6V
Hysteresis on all inputs
Typical VOLP (Output Ground Bounce)
< 0.8V at VCC = 3.3V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
< 2.0V at VCC = 3.3V, TA = 25°C
Bus Hold retains last active bus state during 3-STATE,
eliminating the need for external pullup resistors
Industrial operation at –40°C to +85°C
Packages available:
– 56-pin 240 mil wide plastic TSSOP (A)
– 56-pin 300 mil wide plastic SSOP (V)
The PI74ALVCH162601 uses D-type latches and D-type flip-flops
with 3-state outputs to allow data flow in transparent, latched, and
clocked modes.
Data flow in each direction is controlled by Output Enable (OEAB
and OEBA), Latched Enable (LEAB and LEBA), and Clock (CLKAB
and CLKBA) inputs. The clock can be controlled by the Clock Enable
(CLKENAB and CLKENBA) inputs. For A-to-B data flow, the device
operates in the transparent mode when LEAB is HIGH. When LEAB
is LOW, the A data is latched if CLKAB is held at a high or low logic
level. If LEAB is low, the A-bus is stored in the latch/flip-flop on the
low-to-high transition of CLKAB. When OEAB is low, the outputs
are active. When OEAB is HIGH, the outputs are in the highimpedance state.
Data flow for B to A is similar to that of A to B but uses OEBA, LEBA,
CLKBA, and CLKENBA.
To reduce overshoot and undershoot, the B-port outputs include
26Ω series resistors.
Logic Block Diagram
To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
The PI74ALVCH162601 has “Bus Hold” which retains the data
input’s last state whenever the data input goes to high-impedance
preventing “floating” inputs and eliminating the need for pullup/
down resistors.
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PS8093C 12/26/97
PI74ALVCH162601
18-BIT
UNIVERSAL
BUS
TRANSCEIVER
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Product Pin Description
Pin Name
CLKEN
OE
LE
CLK
Ax
Bx
GND
VCC
Truth Table(1)†
Description
Clock Enable Input (Active LOW)
Output Enable Input (Active LOW)
Latch Enable (Active HIGH)
Clock Input (Active HIGH)
Data I/O
Data I/O
Ground
Power
Inputs
CLKENAB OEAB LEAB
Product Pin Configuration
OEAB
LEAB
A1
GND
A2
A3
1
2
56
55
CLKENAB
3
4
5
54
53
52
B1
6
7
8
56-PIN 51
A-56
50
V-56
GND
B2
B3
VCC
B4
9
10
48
47
B5
B6
11
12
13
46
45
44
GND
43
42
41
B9
A11
14
15
16
A12
GND
17
18
40
39
B12
A13
38
37
36
B13
A15
19
20
21
VCC
A16
A17
22
23
24
35
34
33
GND
25
26
32
31
GND
27
28
30
29
CLKBA
CLKENBA
A5
A6
GND
A7
A8
A9
A10
A14
A18
OEBA
LEBA
A
Output B
X
H
X
X
X
Z
X
L
H
X
L
L
X
L
H
X
H
H
H
L
L
X
X
B0‡
H
L
L
X
X
B0‡
L
L
L
­
L
L
L
L
L
­
H
H
L
L
L
L
X
B0‡
L
L
L
H
X
B0§
Notes:
1. H = High Signal Level
L = Low Signal Level
Z = High Impedance
↑ = LOW-to-HIGH Transition
† A-to-B data flow is shown: B-to-A flow is similar but
uses OEBA, LEBA, CLKBA, and CLKENBA.
‡ Output level before the indicated steady-state input
conditions were established.
§ Output level before the indicated steady-state input
conditions were established, provided that CLKAB is
LOW before LEAB goes LOW.
CLKAB
49
VCC
A4
CLKAB
B7
B8
B10
B11
GND
B14
B15
VCC
B16
B17
B18
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PS8093C 12/26/97
PI74ALVCH162601
18-BIT
UNIVERSAL
BUS
TRANSCEIVER
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Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .............................................................. –65°C to +150°C
Supply Voltage Range, VCC ......................................................... –0.5V to 4.6V
Input Voltage Range,VI :
Except I/O ports (See Note 1): ..................................................... –0.5V to 4.6V
I/O ports (See Notes 1 and 2) ........................................... –0.5V to VCC + 0.5V
Output Voltage Range, VO (See Notes1and 2) ................. –0.5V to VCC + 0.5V
Input Clamp current, IIK (VI < 0) ........................................................... –50mA
Output Clamp current, IOK (VO < 0 or VO > VCC) ................................ ±50mA
Continous Output Current, IO (VO = 0 to VCC) .................................... ±50mA
Continous Current through each VCC or GND .................................... ±100mA
Maximum Power Dissipation:
A package ................................................................................................... 1W
V package ................................................................................................. 1.4W
Note:
Stresses greater than those listed under
MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only
and functional operation of the device at these or
any other conditions above those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Notes:
1. The input and output negative-voltage ratings maybe exceeded if the input and outputclamp-current ratings are observed.
2. This value is limited to 4.6V maximum.
3. The maximumpackage power dissipation is calculated using a junction temperature of 150ºC and a board trace lengthof 750mils.
Recommended Operating Conditions(1)
Parame te rs
De s cription
VCC
Supply Voltage
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VIN
Input Voltage
0
VCC
VOUT
Output Voltage
0
VCC
VCC = 2.3V
- 12
IOH
High- level
Output Current
(A Port)
VCC = 2.7V
- 12
VCC = 3.0V
- 24
Low- level
Output Current
(A Port)
VCC = 2.3V
12
VCC = 2.7V
12
VCC = 3.0V
24
High- level
Output Current
(B Port)
VCC = 2.3V
-6
Low- level
Output Current
(B Port)
IOL
IOH
IOL
TA
Te s t Conditions
M in.
2.3
VCC = 2.3V to 2.7V
1.7
VCC = 2.7V to 3.6V
2.0
VCC = 2.3V to 2.7V
Typ.
M ax.
3.6
0.7
VCC = 2.7V to 3.6V
V
0.8
VCC = 2.7V
-8
VCC = 3.0V
- 12
VCC = 2.3V
6
VCC = 2.7V
8
VCC = 3.0V
12
Operating Free- Air Temperature
Units
- 40
85
mA
°C
Note:
1. Unused control inputs must be held HIGH or LOW to prevent them from floating.
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PS8093C 12/26/97
PI74ALVCH162601
18-BIT
UNIVERSAL
BUS
TRANSCEIVER
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DC Electrical Characteristics (Over the Operating Range, TA = –40°C to +85°C, VCC = 3.3V ± 10%)
Parame te rs
VCC(1)
Te s t Conditions
IOH = - 100 mA
IOH = - 4 mA
VOH (B Port)
VIH = 1.7V
2.3V
VIH = 1.7V
2.3V
1.7
3.0V
2.4
IOH = - 8 mA
VIH = 2.0V
2.7V
2.0
IOH = - 12 mA
VIH = 2.0V
3.0V
2.0
IOH = - 6 mA
IOH = - 12 mA
IOH = - 24 mA
VOL (B Port)
VIH = 1.7V
2.3V
VIH = 1.7V
2.3V
1.7
VIH = 2.0V
2.7V
2.2
VIH = 2.0V
3.0V
2.4
VIH = 2.0V
3.0V
2.0
2.3V
0.4
2.3V
0.55
VIL = 0.8V
3.0V
0.55
IOL = 8 mA
VIL = 0.8V
2.7V
0.6
IOL= 12 mA
VIL = 0.8V
3.0V
0.8
Min. to Max.
0.2
IOL = 12 mA
IOL = 24 mA
VIL = 0.7V
2.3V
0.4
VIL = 0.7V
2.3V
0.7
VIL = 0.8V
2.7V
0.4
VIL = 0.8V
3.0V
0.55
3.6V
±5
VI = VCC or GND
VI = 0.7V
II (Hold)(3)
2.3V
VI = 1.7V
VI = 0.8V
3.0V
VI = 2.0V
IOZ(4)
ICC
DICC
0.2
VIL = 0.7V
IOL = 6 mA
II
V
Min. to Max.
IOL = 100 mA
VOL (A Port)
2.0
VIL = 0.7V
IOL = 6 mA
45
- 45
75
- 75
mA
VI = 0 to 3.6V
3.6V
±500
VO = VCCor GND
3.6V
±10
3.6V
40
3V to 3.6V
750
VI = VCC or GND
Units
Min. to Max. VCC - 0.2
IOL = 100 mA
IOL = 4 mA
M ax.
1.9
VIH = 2.0V
IOH = - 6 mA
Typ.(2)
Min. to Max. VCC - 0.2
IOH = - 100 mA
VOH (A Port)
M in.
IO = 0
One input at VCC - 0.6V, Other inputs at VCC or GND
CI Control Inputs VI = VCC or GND
3.3V
4
CIO A or B ports VO = VCC or GND
3.3V
8
pF
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 3.3V, +25°C ambient and maximum loading.
3. Bus Hold maximum dynamic current required to switch the input from one state to another.
4. For I/O ports, the IOZ includes the input leakage current.
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PS8093C 12/26/97
PI74ALVCH162601
18-BIT
UNIVERSAL
BUS
TRANSCEIVER
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Timing Requirements over Operating Range
Parame te rs
D e s cription
fCLOCK
tW Pulse
Duration
tSUSetup
time
tH Hold
time
Dt/Dv(1)
VCC = 2.5V ± 0.2V
VCC = 2.7V
VCC = 3.3V ± 0.3V
M in.
M ax.
M in.
M ax.
M in.
M ax.
Clock frequency
0
140
0
150
0
150
LE high
3.3
3.3
3.3
CLK high or low
3.3
3.3
3.3
Data before CLK high
2.3
2.4
2.1
Data before LE low, CLK high
2.0
1.6
1.6
Data before LE low, CLK low
1.3
1.2
1.1
CLK EN before CLK high
2.0
2.0
1.7
Data after CLK high
0.7
0.7
0.8
Data after LE low, CLK high
1.3
1.6
1.4
Data after LE low, CLK low
1.7
2.0
1.7
CLK EN after CLK high
0.3
0.5
0.6
Input Transition Rise or Fall
0
10
0
10
Units
MHz
ns
0
10
ns/V
Note:
1. Unused control inputs must be held HIGH or LOW to prevent them from floating.
Switching Characteristics over Operating Range(1)
Parame te rs
From(INPUT) To(OUTPUT)
VCC = 2.5V ±0.2V
M in.(2)
VCC = 2.7V
M ax. M in.(2)
140
fMAX
VCC = 3.3 V ± 0.3V
M ax.
150
M in.(2)
150
MHz
tPD
A
B
1.8
5.4
5.2
1.6
4.5
tPD
B
A
1.3
4.9
4.6
1
4.1
tPD
LEAB
B
1.5
6.1
5.9
1.5
5.1
tPD
LEBA
A
1.4
5.6
5.3
1
4.7
tPD
CLKAB
B
2
6.7
6.3
1.6
5.5
tPD
CLKBA
A
1.8
6.2
5.8
1.4
5
tEN
OEAB
B
1.7
6.6
6.7
1.6
5.7
tDIS
OEAB
B
2.5
5.9
5.3
1.8
4.8
tEN
OEBA
A
1.2
6
OEBA
A
2.1
5.4
tDIS
Notes:
1. See test circuit and wave forms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
Units
M ax.
6.1
1.1
5.2
4.8
1.6
4.4
ns
Operating Characteristics, TA = 25ºC
Parame te r
CPD Power Dissipation
Capacitance
Te s t Conditions
Outputs Enabled
Outputs Disabled
CL = 50pF,
f = 10 MHz
VCC = 2.5V ± 0.2V
VCC = 3.3V ± 0.3V
Typical
41
50
6
6
Units
pF
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
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PS8093C 12/26/97