µPD98412 ADVANCED ATM SWITCH LSI TM (NEASCOT-X15 ) Features • Conforms to the ATM FORUM UNI Version 3.1 & 4.0 • All switching functions are integrated in a single chip • Non-blocking architecture with 1.5Gbps switching capacity • Up to 64K unicast virtual paths/virtual channels, up to 4K multicast virtual paths/virtual channels • Shared buffer architecture that uses standard SRAMs • Cell buffer capacity up to 51.2K cells • Selectable UTOPIA Level2 data bit width • Supports four QOS classes (CBR, VBR, ABR, UBR) (8-bit x 4 ports, 8-bit x 2 ports + 16-bit x 1 port, • ABR traffic control (binary mode) 16-bit x 2 ports) • EPD(Early Packet Discard), PPD(Partial Packet Discard) • Some polling modes on UTOPIA Level2 Interface • + 3.3 V supply (+ 5 V tolerant inputs) • Supporting 30 logical ports • JTAG(IEEE 1149.1) support • Multiple speed (622Mbps, 155Mbps, 52Mbps, • 576-pin tape BGA (40 x 40) 25Mbps etc.) • Supports microprocessor port for signaling and OAM cell processing Block Diagram UTOPIA receive port 2 UTOPIA receive port 3 Input header separator Microprocessor interface Microprocessor Output payload selector Cell buffer interface Queue controller HTT & Control memory interface HTT & Control Memory Output header selector Output arbiter UTOPIA transmit port 0 Output port interface UTOPIA receive port 1 Input port interface UTOPIA receive port 0 Test interface Input payload separator Cell Buffer Memory UTOPIA transmit port 1 UTOPIA transmit port 2 UTOPIA transmit port 3 TEST The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S14301EJ3V0PF00 (3rd edition) Data Published November 2001 NS CP(K) Printed in Japan 1999 System Configuration Example Microprocessor 16-bit 50 MHz UTOPIA Level 2 PHY #29 µPD98412 NEASCOT-X15 #2 8-bit 33MHz PHY #28 #1 Physical Outport #0 #1 Logical Outport #0 PHY 8-bit 33MHz #2 #3 UTOPIA Level 2 PHY #0 Physical Inport #0 UTOPIA Level 2 UTOPIA Level 2 Logical Inport 16-bit 50 MHz #3 32bit + parity HTT & Control Memory #28 PHY #29 PHY 88-bit or 92-bit Cell Buffer (Memory) HTT : Header Translation Table NEASCOT-X15 is a trademark of NEC Corporation. • The information in this document is current as of November, 2001. The information is subject to change without notice. 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(Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4