LMC6064 Precision CMOS Quad Micropower Operational Amplifier General Description Features The LMC6064 is a precision quad low offset voltage, micropower operational amplifier, capable of precision single supply operation. Performance characteristics include ultra low input bias current, high voltage gain, rail-to-rail output swing, and an input common mode voltage range that includes ground. These features, plus its low power consumption make the LMC6064 ideally suited for battery powered applications. Other applications using the LMC6064 include precision full-wave rectifiers, integrators, references, sample-and-hold circuits, and true instrumentation amplifiers. This device is built with National’s advanced double-Poly Silicon-Gate CMOS process. For designs that require higher speed, see the LMC6084 precision quad operational amplifier. For single or dual operational amplifier with similar features, see the LMC6061 or LMC6062 respectively. PATENT PENDING (Typical Unless Otherwise Noted) n Low offset voltage: 100 µV n Ultra low supply current: 16 µA/Amplifier n Operates from 4.5V to 15V single supply n Ultra low input bias current: 10 fA n Output swing within 10 mV of supply rail, 100k load n Input common-mode range includes V− n High voltage gain: 140 dB n Improved latchup immunity Applications n n n n n n n Instrumentation amplifier Photodiode and infrared detector preamplifier Transducer amplifiers Hand-held analytic instruments Medical instrumentation D/A converter Charge amplifier for piezoelectric transducers Connection Diagram 14-Pin DIP/SO 01146601 Top View Low-Leakage Sample and Hold 01146613 © 2001 National Semiconductor Corporation DS011466 www.national.com LMC6064 Precision CMOS Quad Micropower Operational Amplifier April 2001 LMC6064 Absolute Maximum Ratings ± 10 mA ± 30 mA Current at Input Pin (Note 1) Current at Output Pin If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Current at Power Supply Pin 40 mA Power Dissipation (Note 3) ± Supply Voltage Differential Input Voltage (V+) +0.3V, Voltage at Input/Output Pin Operating Ratings (Note 1) (V−) −0.3V Supply Voltage (V+ − V−) Temperature Range 16V + Output Short Circuit to V Output Short Circuit to V− −55˚C ≤ TJ ≤ +125˚C LMC6064AM (Note 11) −40˚C ≤ TJ ≤ +85˚C LMC6064AI, LMC6064I (Note 2) 4.5V ≤ V+ ≤ 15.5V Supply Voltage Lead Temperature (Soldering, 10 sec.) 260˚C Storage Temp. Range −65˚C to +150˚C Junction Temperature Thermal Resistance (θJA) (Note 12) 14-Pin Molded DIP 150˚C ESD Tolerance (Note 4) 81˚C/W 14-Pin SO 126˚C/W Power Dissipation 2 kV (Note 10) DC Electrical Characteristics Unless otherwise specified, all limits guaranteed for TJ = 25˚C. Boldface limits apply at the temperature extremes. V+ = 5V, V− = 0V, VCM = 1.5V, VO = 2.5V and RL > 1M unless otherwise specified. Typ Symbol Parameter Conditions (Note 5) VOS Input Offset Voltage 100 TCVOS Input Offset Voltage 1.0 LMC6064AM LMC6064AI LMC6064I Limit Limit Limit (Note 6) (Note 6) (Note 6) 350 350 800 1200 900 1300 Units µV Max µV/˚C Average Drift IB IOS Input Bias Current 0.010 Input Offset Current 4 Max 100 2 2 Max 75 75 66 dB 70 72 63 Min pA Tera Ω > 10 Input Resistance CMRR Common Mode 0V ≤ VCM ≤ 12.0V Rejection Ratio V+ = 15V Positive Power Supply 5V ≤ V+ ≤ 15V Rejection Ratio VO = 2.5V Negative Power Supply 0V ≤ V− ≤ −10V −PSRR 4 0.005 RIN +PSRR pA 100 85 85 75 75 66 dB 70 72 63 Min 84 84 74 dB 70 81 71 Min −0.1 −0.1 −0.1 V 0 0 0 Max V+ − 2.3 V+ − 2.3 V+ − 2.3 V 100 Rejection Ratio VCM Input Common-Mode V+ = 5V and 15V Voltage Range for CMRR ≥ 60 dB −0.4 V+ − 1.9 + AV Large Signal RL = 100 kΩ Voltage Gain (Note 7) RL = 25 kΩ + V − 2.6 V − 2.5 V − 2.5 Min Sourcing 4000 400 400 300 V/mV 200 300 200 Min Sinking 3000 180 180 90 V/mV 70 100 60 Min Sourcing 3000 400 400 200 V/mV 150 150 80 Min 100 100 70 V/mV 35 50 35 Min (Note 7) Sinking www.national.com + 2000 2 (Continued) Unless otherwise specified, all limits guaranteed for TJ = 25˚C. Boldface limits apply at the temperature extremes. V+ = 5V, V− = 0V, VCM = 1.5V, VO = 2.5V and RL > 1M unless otherwise specified. Symbol VO Parameter Output Swing Conditions Typ LMC6064AM LMC6064AI LMC6064I (Note 5) Limit Limit Limit (Note 6) (Note 6) (Note 6) 4.990 4.990 4.950 V 4.970 4.980 4.925 Min 0.010 0.010 0.050 V 0.030 0.020 0.075 Max V+ = 5V 4.995 RL = 100 kΩ to 2.5V 0.005 V+ = 5V 4.990 RL = 25 kΩ to 2.5V 0.010 V+ = 15V 14.990 RL = 100 kΩ to 7.5V 0.010 V+ = 15V 14.965 RL = 25 kΩ to 7.5V 0.025 IO Output Current Sourcing, VO = 0V 22 V+ = 5V IO Output Current 4.975 4.950 V 4.965 4.850 Min 0.020 0.020 0.050 V 0.045 0.035 0.150 Max 14.975 14.975 14.950 V 14.955 14.965 14.925 Min 0.025 0.025 0.050 V 0.050 0.035 0.075 Max 14.900 14.900 14.850 V 14.800 14.850 14.800 Min 0.050 0.050 0.100 V 0.200 0.150 0.200 Max 16 16 13 mA 8 10 8 Min 16 16 mA Min 21 16 7 8 8 Sourcing, VO = 0V 25 15 15 15 mA 9 10 10 Min 26 20 20 20 mA 7 8 8 Min 64 76 76 92 µA 120 92 112 Max 94 94 114 µA 140 110 132 Max Sinking, VO = 13V (Note 11) Supply Current 4.975 4.955 Sinking, VO = 5V V+ = 15V IS Units All Four Amplifiers V+ = +5V, VO = 1.5V All Four Amplifiers V+ = +15V, VO = 7.5V 80 AC Electrical Characteristics Unless otherwise specified, all limits guaranteed for TJ = 25˚C, Boldface limits apply at the temperature extremes. V+ = 5V, V− = 0V, VCM = 1.5V, VO = 2.5V and RL > 1M unless otherwise specified. Typ Symbol Parameter SR Slew Rate GBW Gain-Bandwidth Product θm Phase Margin Conditions (Note 5) (Note 8) 35 LMC6064AM LMC6064AI LMC6064I Limit Limit Limit (Note 6) (Note 6) (Note 6) 20 20 15 8 10 7 Units V/ms Min 100 kHz 50 Deg Amp-to-Amp Isolation (Note 9) 155 dB en Input-Referred Voltage Noise F = 1 kHz 83 in Input-Referred Current Noise F = 1 kHz 0.0002 T.H.D. Total Harmonic Distortion F = 1 kHz, AV = −5 RL = 100 kΩ, VO = 2 VPP 0.01 % ± 5V Supply 3 www.national.com LMC6064 DC Electrical Characteristics LMC6064 AC Electrical Characteristics (Continued) Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Note 2: Applies to both single-supply and split-supply operation. Continous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150˚C. Output currents in excess of ± 30 mA over long term may adversely affect reliability. Note 3: The maximum power dissipation is a function of TJ(Max), θJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(Max) − TA)/θJA. Note 4: Human body model, 1.5 kΩ in series with 100 pF. Note 5: Typical values represent the most likely parametric norm. Note 6: All limits are guaranteed by testing or statistical analysis. Note 7: V+ = 15V, VCM = 7.5V and RL connected to 7.5V. For Sourcing tests, 7.5V ≤ VO ≤ 11.5V. For Sinking tests, 2.5V ≤ VO ≤ 7.5V. Note 8: V+ = 15V. Connected as Voltage Follower with 10V step input. Number specified is the slower of the positive and negative slew rates. Note 9: Input referred V+ = 15V and RL = 100 kΩ connected to 7.5V. Each amp excited in turn with 100 Hz to produce VO = 12 VPP. Note 10: For operating at elevated temperatures the device must be derated based on the thermal resistance θJA with PD = (TJ–TA)/θJA. Note 11: Do not connect output to V+, when V+ is greater than 13V or reliability witll be adversely affected. Note 12: All numbers apply for packages soldered directly into a PC board. Note 13: For guaranteed Military Temperature Range parameters see RETSMC6064X. www.national.com 4 LMC6064 Typical Performance Characteristics Distribution of LMC6064 Input Offset Voltage (TA = −55˚C) Distribution of LMC6064 Input Offset Voltage (TA = +25˚C) 01146615 01146616 Distribution of LMC6064 Input Offset Voltage (TA = +125˚C) Input Bias Current vs Temperature 01146618 01146617 Supply Current vs Supply Voltage Input Voltage vs Output Voltage 01146619 01146620 5 www.national.com LMC6064 Typical Performance Characteristics (Continued) Common Mode Rejection Ratio vs Frequency Power Supply Rejection Ratio vs Frequency 01146621 01146622 Input Voltage Noise vs Frequency Output Characteristics Sourcing Current 01146623 01146624 Gain and Phase Response vs Temperature (−55˚C to +125˚C) Output Characteristics Sinking Current 01146626 01146625 www.national.com 6 LMC6064 Typical Performance Characteristics (Continued) Gain and Phase Response vs Capacitive Load with RL = 500 kΩ Gain and Phase Response vs Capacitive Load with RL = 20 kΩ 01146627 01146628 Open Loop Frequency Response Inverting Small Signal Pulse Response 01146630 01146629 Inverting Large Signal Pulse Response Non-Inverting Small Signal Pulse Response 01146631 01146632 7 www.national.com LMC6064 Typical Performance Characteristics (Continued) Non-Inverting Large Signal Pulse Response Crosstalk Rejection vs Frequency 01146633 01146634 Stability vs Capacitive Load, RL = 20 kΩ Stability vs Capacitive Load RL = 1 MΩ 01146636 01146635 www.national.com 8 AMPLIFIER TOPOLOGY location of the dominate pole is affected by the resistive load on the amplifier. Capacitive load driving capability can be optimized by using an appropriate resistive load in parallel with the capacitive load (see typical curves). The LMC6064 incorporates a novel op-amp design topology that enables it to maintain rail-to-rail output swing even when driving a large load. Instead of relying on a push-pull unity gain output buffer stage, the output stage is taken directly from the internal integrator, which provides both low output impedance and large gain. Special feed-forward compensation design techniques are incorporated to maintain stability over a wider range of operating conditions than traditional micropower op-amps. These features make the LMC6064 both easier to design with, and provide higher speed than products typically found in this ultra-low power class. Direct capacitive loading will reduce the phase margin of many op-amps. A pole in the feedback loop is created by the combination of the op-amp’s output impedance and the capacitive load. This pole induces phase lag at the unity-gain crossover frequency of the amplifier resulting in either an oscillatory or underdamped pulse response. With a few external components, op amps can easily indirectly drive capacitive loads, as shown in Figure 2. COMPENSATING FOR INPUT CAPACITANCE It is quite common to use large values of feedback resistance for amplifiers with ultra-low input current, like the LMC6064. Although the LMC6064 is highly stable over a wide range of operating conditions, certain precautions must be met to achieve the desired pulse response when a large feedback resistor is used. Large feedback resistors and even small values of input capacitance, due to transducers, photodiodes, and circuit board parasitics, reduce phase margins. When high input impedances are demanded, guarding of the LMC6064 is suggested. Guarding input lines will not only reduce leakage, but lowers stray input capacitance as well. (See Printed-Circuit-Board Layout for High Impedance Work). The effect of input capacitance can be compensated for by adding a capacitor. Place a capacitor, Cf, around the feedback resistor (as in Figure 1 ) such that: 01146605 FIGURE 2. LMC6064 Noninverting Gain of 10 Amplifier, Compensated to Handle Capacitive Loads In the circuit of Figure 2, R1 and C1 serve to counteract the loss of phase margin by feeding the high frequency component of the output signal back to the amplifier’s inverting input, thereby preserving phase margin in the overall feedback loop. Capacitive load driving capability is enhanced by using a pull up resistor to V+ (Figure 3). Typically a pull up resistor conducting 10 µA or more will significantly improve capacitive load responses. The value of the pull up resistor must be determined based on the current sinking capability of the amplifier with respect to the desired output swing. Open loop gain of the amplifier can also be affected by the pull up resistor (see Electrical Characteristics). or R1 CIN ≤ R2 Cf Since it is often difficult to know the exact value of CIN, Cf can be experimentally adjusted so that the desired pulse response is achieved. Refer to the LMC660 and the LMC662 for a more detailed discussion on compensating for input capacitance. 01146604 01146606 FIGURE 1. Canceling the Effect of Input Capacitance FIGURE 3. Compensating for Large Capacitive Loads with a Pull Up Resistor CAPACITIVE LOAD TOLERANCE All rail-to-rail output swing operational amplifiers have voltage gain in the output stage. A compensation capacitor is normally included in this integrator stage. The frequency 9 www.national.com LMC6064 Applications Hints LMC6064 Applications Hints (Continued) PRINTED-CIRCUIT-BOARD LAYOUT FOR HIGH-IMPEDANCE WORK It is generally recognized that any circuit which must operate with less than 1000 pA of leakage current requires special layout of the PC board. When one wishes to take advantage of the ultra-low bias current of the LMC6064, typically less than 10 fA, it is essential to have an excellent layout. Fortunately, the techniques of obtaining low leakages are quite simple. First, the user must not ignore the surface leakage of the PC board, even though it may sometimes appear acceptably low, because under conditions of high humidity or dust or contamination, the surface leakage will be appreciable. To minimize the effect of any surface leakage, lay out a ring of foil completely surrounding the LMC6064’s inputs and the terminals of capacitors, diodes, conductors, resistors, relay terminals etc. connected to the op-amp’s inputs, as in Figure 4. To have a significant effect, guard rings should be placed on both the top and bottom of the PC board. This PC foil must then be connected to a voltage which is at the same voltage as the amplifier inputs, since no leakage current can flow between two points at the same potential. For example, a PC board trace-to-pad resistance of 1012Ω, which is normally considered a very large resistance, could leak 5 pA if the trace were a 5V bus adjacent to the pad of the input. This would cause a 100 times degradation from the LMC6064’s actual performance. However, if a guard ring is held within 5 mV of the inputs, then even a resistance of 1011Ω would cause only 0.05 pA of leakage current. See Figure 5 for typical connections of guard rings for standard op-amp configurations. 01146608 Inverting Amplifier 01146609 Non-Inverting Amplifier 01146610 Follower FIGURE 5. Typical Connections of Guard Rings The designer should be aware that when it is inappropriate to lay out a PC board for the sake of just a few circuits, there is another technique which is even better than a guard ring on a PC board: Don’t insert the amplifier’s input pin into the board at all, but bend it up in the air and use only air as an insulator. Air is an excellent insulator. In this case you may have to forego some of the advantages of PC board construction, but the advantages are sometimes well worth the effort of using point-to-point up-in-the-air wiring. See Figure 6. 01146607 FIGURE 4. Example of Guard Ring in P.C. Board Layout Latchup CMOS devices tend to be susceptible to latchup due to their internal parasitic SCR effects. The (I/O) input and output pins look similar to the gate of the SCR. There is a minimum current required to trigger the SCR gate lead. The LMC6064 and LMC6082 are designed to withstand 100 mA surge current on the I/O pins. Some resistive method should be used to isolate any capacitance from supplying excess current to the I/O pins. In addition, like an SCR, there is a minimum holding current for any latchup mode. Limiting current to the supply pins will also inhibit latchup susceptibility. www.national.com 10 LMC6064 Latchup (Continued) 01146611 (Input pins are lifted out of PC board and soldered directly to components. All other pins connected to PC board). FIGURE 6. Air Wiring Figure 7 shows an instrumentation amplifier that features high differential and common mode input resistance ( > 1014Ω), 0.01% gain accuracy at AV = 100, excellent CMRR with 1 kΩ imbalance in bridge source resistance. Input current is less than 100 fA and offset drift is less than 2.5 µV/˚C. R2 provides a simple means of adjusting gain over a wide range without degrading CMRR. R7 is an initial trim used to maximize CMRR without using super precision matched resistors. For good CMRR over temperature, low drift resistors should be used. Typical Single-Supply Applications (V+ = 5.0 VDC) The extremely high input impedance, and low power consumption, of the LMC6064 make it ideal for applications that require battery-powered instrumentation amplifiers. Examples of these types of applications are hand-held pH probes, analytic medical instruments, magnetic field detectors, gas detectors, and silicon based pressure transducers. 01146612 If R1 = R5, R3 = R6, and R4 = R7; then ∴AV ≈ 100 for circuit shown (R2 = 9.822k). FIGURE 7. Instrumentation Amplifier 11 www.national.com LMC6064 Typical Single-Supply Applications (Continued) 01146613 FIGURE 8. Low-Leakage Sample and Hold 01146614 FIGURE 9. 1 Hz Square Wave Oscillator Ordering Information Temperature Range Package Military −55˚C to +125˚C Industrial −40˚C to +85˚C 14-Pin LMC6064AIN Molded DIP LMC6064IN 14-Pin LMC6064AIM, LMC6064AIMX Small Outline 14-Pin Transport Media N14A Rail M14A Rail LMC6064IM, LMC6064IMX LMC6064AMJ/883 Tape and Reel J14A Ceramic DIP www.national.com NSC Drawing 12 Rail LMC6064 Physical Dimensions inches (millimeters) unless otherwise noted 14-Pin Ceramic Dual-In-Line Package Order Number LMC6064AMJ/883 NS Package Number J14A 13 www.national.com LMC6064 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Pin Small Outline Package Order Number LMC6064AIM, LMC6064AIMX, LMC6064IM or LMC6064IMX NS Package Number M14A 14-Pin Molded Dual-In-Line Package Order Number LMC6064AIN or LMC6064IN NS Package Number N14A www.national.com 14 LMC6064 Precision CMOS Quad Micropower Operational Amplifier Notes LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: [email protected] www.national.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: [email protected] National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.